1 //===- X86DisassemblerTables.cpp - Disassembler tables ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the X86 Disassembler Emitter.
11 // It contains the implementation of the disassembler tables.
12 // Documentation for the disassembler emitter in general can be found in
13 // X86DisasemblerEmitter.h.
15 //===----------------------------------------------------------------------===//
17 #include "X86DisassemblerShared.h"
18 #include "X86DisassemblerTables.h"
20 #include "llvm/TableGen/TableGenBackend.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/Support/ErrorHandling.h"
23 #include "llvm/Support/Format.h"
27 using namespace X86Disassembler;
29 /// inheritsFrom - Indicates whether all instructions in one class also belong
32 /// @param child - The class that may be the subset
33 /// @param parent - The class that may be the superset
34 /// @return - True if child is a subset of parent, false otherwise.
35 static inline bool inheritsFrom(InstructionContext child,
36 InstructionContext parent,
37 bool VEX_LIG = false) {
43 return(inheritsFrom(child, IC_64BIT) ||
44 inheritsFrom(child, IC_OPSIZE) ||
45 inheritsFrom(child, IC_ADSIZE) ||
46 inheritsFrom(child, IC_XD) ||
47 inheritsFrom(child, IC_XS));
49 return(inheritsFrom(child, IC_64BIT_REXW) ||
50 inheritsFrom(child, IC_64BIT_OPSIZE) ||
51 inheritsFrom(child, IC_64BIT_ADSIZE) ||
52 inheritsFrom(child, IC_64BIT_XD) ||
53 inheritsFrom(child, IC_64BIT_XS));
55 return inheritsFrom(child, IC_64BIT_OPSIZE);
60 return inheritsFrom(child, IC_64BIT_XD);
62 return inheritsFrom(child, IC_64BIT_XS);
64 return inheritsFrom(child, IC_64BIT_XD_OPSIZE);
66 return inheritsFrom(child, IC_64BIT_XS_OPSIZE);
68 return(inheritsFrom(child, IC_64BIT_REXW_XS) ||
69 inheritsFrom(child, IC_64BIT_REXW_XD) ||
70 inheritsFrom(child, IC_64BIT_REXW_OPSIZE));
72 return(inheritsFrom(child, IC_64BIT_REXW_OPSIZE));
74 return(inheritsFrom(child, IC_64BIT_REXW_XD));
76 return(inheritsFrom(child, IC_64BIT_REXW_XS));
77 case IC_64BIT_XD_OPSIZE:
78 case IC_64BIT_XS_OPSIZE:
80 case IC_64BIT_REXW_XD:
81 case IC_64BIT_REXW_XS:
82 case IC_64BIT_REXW_OPSIZE:
85 return inheritsFrom(child, IC_VEX_W) ||
86 (VEX_LIG && inheritsFrom(child, IC_VEX_L));
88 return inheritsFrom(child, IC_VEX_W_XS) ||
89 (VEX_LIG && inheritsFrom(child, IC_VEX_L_XS));
91 return inheritsFrom(child, IC_VEX_W_XD) ||
92 (VEX_LIG && inheritsFrom(child, IC_VEX_L_XD));
94 return inheritsFrom(child, IC_VEX_W_OPSIZE) ||
95 (VEX_LIG && inheritsFrom(child, IC_VEX_L_OPSIZE));
105 case IC_VEX_L_OPSIZE:
106 return inheritsFrom(child, IC_VEX_L_W_OPSIZE);
107 case IC_VEX_L_W_OPSIZE:
110 llvm_unreachable("Unknown instruction class");
114 /// outranks - Indicates whether, if an instruction has two different applicable
115 /// classes, which class should be preferred when performing decode. This
116 /// imposes a total ordering (ties are resolved toward "lower")
118 /// @param upper - The class that may be preferable
119 /// @param lower - The class that may be less preferable
120 /// @return - True if upper is to be preferred, false otherwise.
121 static inline bool outranks(InstructionContext upper,
122 InstructionContext lower) {
123 assert(upper < IC_max);
124 assert(lower < IC_max);
126 #define ENUM_ENTRY(n, r, d) r,
127 static int ranks[IC_max] = {
132 return (ranks[upper] > ranks[lower]);
135 /// stringForContext - Returns a string containing the name of a particular
136 /// InstructionContext, usually for diagnostic purposes.
138 /// @param insnContext - The instruction class to transform to a string.
139 /// @return - A statically-allocated string constant that contains the
140 /// name of the instruction class.
141 static inline const char* stringForContext(InstructionContext insnContext) {
142 switch (insnContext) {
144 llvm_unreachable("Unhandled instruction class");
145 #define ENUM_ENTRY(n, r, d) case n: return #n; break;
151 /// stringForOperandType - Like stringForContext, but for OperandTypes.
152 static inline const char* stringForOperandType(OperandType type) {
155 llvm_unreachable("Unhandled type");
156 #define ENUM_ENTRY(i, d) case i: return #i;
162 /// stringForOperandEncoding - like stringForContext, but for
163 /// OperandEncodings.
164 static inline const char* stringForOperandEncoding(OperandEncoding encoding) {
167 llvm_unreachable("Unhandled encoding");
168 #define ENUM_ENTRY(i, d) case i: return #i;
174 void DisassemblerTables::emitOneID(raw_ostream &o, unsigned &i, InstrUID id,
175 bool addComma) const {
177 o.indent(i * 2) << format("0x%hx", id);
179 o.indent(i * 2) << 0;
187 o << InstructionSpecifiers[id].name;
193 /// emitEmptyTable - Emits the modRMEmptyTable, which is used as a ID table by
194 /// all ModR/M decisions for instructions that are invalid for all possible
195 /// ModR/M byte values.
197 /// @param o - The output stream on which to emit the table.
198 /// @param i - The indentation level for that output stream.
199 static void emitEmptyTable(raw_ostream &o, unsigned &i) {
200 o.indent(i * 2) << "0x0, /* EmptyTable */\n";
203 /// getDecisionType - Determines whether a ModRM decision with 255 entries can
204 /// be compacted by eliminating redundant information.
206 /// @param decision - The decision to be compacted.
207 /// @return - The compactest available representation for the decision.
208 static ModRMDecisionType getDecisionType(ModRMDecision &decision) {
209 bool satisfiesOneEntry = true;
210 bool satisfiesSplitRM = true;
211 bool satisfiesSplitReg = true;
213 for (unsigned index = 0; index < 256; ++index) {
214 if (decision.instructionIDs[index] != decision.instructionIDs[0])
215 satisfiesOneEntry = false;
217 if (((index & 0xc0) == 0xc0) &&
218 (decision.instructionIDs[index] != decision.instructionIDs[0xc0]))
219 satisfiesSplitRM = false;
221 if (((index & 0xc0) != 0xc0) &&
222 (decision.instructionIDs[index] != decision.instructionIDs[0x00]))
223 satisfiesSplitRM = false;
225 if (((index & 0xc0) == 0xc0) &&
226 (decision.instructionIDs[index] != decision.instructionIDs[index&0xf8]))
227 satisfiesSplitReg = false;
229 if (((index & 0xc0) != 0xc0) &&
230 (decision.instructionIDs[index] != decision.instructionIDs[index&0x38]))
231 satisfiesSplitReg = false;
234 if (satisfiesOneEntry)
235 return MODRM_ONEENTRY;
237 if (satisfiesSplitRM)
238 return MODRM_SPLITRM;
240 if (satisfiesSplitReg)
241 return MODRM_SPLITREG;
246 /// stringForDecisionType - Returns a statically-allocated string corresponding
247 /// to a particular decision type.
249 /// @param dt - The decision type.
250 /// @return - A pointer to the statically-allocated string (e.g.,
251 /// "MODRM_ONEENTRY" for MODRM_ONEENTRY).
252 static const char* stringForDecisionType(ModRMDecisionType dt) {
253 #define ENUM_ENTRY(n) case n: return #n;
256 llvm_unreachable("Unknown decision type");
262 /// stringForModifierType - Returns a statically-allocated string corresponding
263 /// to an opcode modifier type.
265 /// @param mt - The modifier type.
266 /// @return - A pointer to the statically-allocated string (e.g.,
267 /// "MODIFIER_NONE" for MODIFIER_NONE).
268 static const char* stringForModifierType(ModifierType mt) {
269 #define ENUM_ENTRY(n) case n: return #n;
272 llvm_unreachable("Unknown modifier type");
278 DisassemblerTables::DisassemblerTables() {
281 for (i = 0; i < array_lengthof(Tables); i++) {
282 Tables[i] = new ContextDecision;
283 memset(Tables[i], 0, sizeof(ContextDecision));
286 HasConflicts = false;
289 DisassemblerTables::~DisassemblerTables() {
292 for (i = 0; i < array_lengthof(Tables); i++)
296 void DisassemblerTables::emitModRMDecision(raw_ostream &o1, raw_ostream &o2,
297 unsigned &i1, unsigned &i2,
298 ModRMDecision &decision) const {
299 static uint32_t sTableNumber = 0;
300 static uint32_t sEntryNumber = 1;
301 ModRMDecisionType dt = getDecisionType(decision);
303 if (dt == MODRM_ONEENTRY && decision.instructionIDs[0] == 0)
305 o2.indent(i2) << "{ /* ModRMDecision */" << "\n";
308 o2.indent(i2) << stringForDecisionType(dt) << "," << "\n";
309 o2.indent(i2) << 0 << " /* EmptyTable */\n";
312 o2.indent(i2) << "}";
316 o1 << "/* Table" << sTableNumber << " */\n";
321 llvm_unreachable("Unknown decision type");
323 emitOneID(o1, i1, decision.instructionIDs[0], true);
326 emitOneID(o1, i1, decision.instructionIDs[0x00], true); // mod = 0b00
327 emitOneID(o1, i1, decision.instructionIDs[0xc0], true); // mod = 0b11
330 for (unsigned index = 0; index < 64; index += 8)
331 emitOneID(o1, i1, decision.instructionIDs[index], true);
332 for (unsigned index = 0xc0; index < 256; index += 8)
333 emitOneID(o1, i1, decision.instructionIDs[index], true);
336 for (unsigned index = 0; index < 256; ++index)
337 emitOneID(o1, i1, decision.instructionIDs[index], true);
343 o2.indent(i2) << "{ /* struct ModRMDecision */" << "\n";
346 o2.indent(i2) << stringForDecisionType(dt) << "," << "\n";
347 o2.indent(i2) << sEntryNumber << " /* Table" << sTableNumber << " */\n";
350 o2.indent(i2) << "}";
354 llvm_unreachable("Unknown decision type");
372 void DisassemblerTables::emitOpcodeDecision(raw_ostream &o1, raw_ostream &o2,
373 unsigned &i1, unsigned &i2,
374 OpcodeDecision &decision) const {
375 o2.indent(i2) << "{ /* struct OpcodeDecision */" << "\n";
377 o2.indent(i2) << "{" << "\n";
380 for (unsigned index = 0; index < 256; ++index) {
383 o2 << "/* 0x" << format("%02hhx", index) << " */" << "\n";
385 emitModRMDecision(o1, o2, i1, i2, decision.modRMDecisions[index]);
394 o2.indent(i2) << "}" << "\n";
396 o2.indent(i2) << "}" << "\n";
399 void DisassemblerTables::emitContextDecision(raw_ostream &o1, raw_ostream &o2,
400 unsigned &i1, unsigned &i2,
401 ContextDecision &decision,
402 const char* name) const {
403 o2.indent(i2) << "static const struct ContextDecision " << name << " = {\n";
405 o2.indent(i2) << "{ /* opcodeDecisions */" << "\n";
408 for (unsigned index = 0; index < IC_max; ++index) {
409 o2.indent(i2) << "/* ";
410 o2 << stringForContext((InstructionContext)index);
414 emitOpcodeDecision(o1, o2, i1, i2, decision.opcodeDecisions[index]);
416 if (index + 1 < IC_max)
421 o2.indent(i2) << "}" << "\n";
423 o2.indent(i2) << "};" << "\n";
426 void DisassemblerTables::emitInstructionInfo(raw_ostream &o,
428 unsigned NumInstructions = InstructionSpecifiers.size();
430 o << "static const struct OperandSpecifier x86OperandSets[]["
431 << X86_MAX_OPERANDS << "] = {\n";
433 typedef std::vector<std::pair<const char *, const char *> > OperandListTy;
434 std::map<OperandListTy, unsigned> OperandSets;
436 unsigned OperandSetNum = 0;
437 for (unsigned Index = 0; Index < NumInstructions; ++Index) {
438 OperandListTy OperandList;
440 for (unsigned OperandIndex = 0; OperandIndex < X86_MAX_OPERANDS;
442 const char *Encoding =
443 stringForOperandEncoding((OperandEncoding)InstructionSpecifiers[Index]
444 .operands[OperandIndex].encoding);
446 stringForOperandType((OperandType)InstructionSpecifiers[Index]
447 .operands[OperandIndex].type);
448 OperandList.push_back(std::make_pair(Encoding, Type));
450 unsigned &N = OperandSets[OperandList];
451 if (N != 0) continue;
455 o << " { /* " << (OperandSetNum - 1) << " */\n";
456 for (unsigned i = 0, e = OperandList.size(); i != e; ++i) {
457 o << " { " << OperandList[i].first << ", "
458 << OperandList[i].second << " },\n";
464 o.indent(i * 2) << "static const struct InstructionSpecifier ";
465 o << INSTRUCTIONS_STR "[" << InstructionSpecifiers.size() << "] = {\n";
469 for (unsigned index = 0; index < NumInstructions; ++index) {
470 o.indent(i * 2) << "{ /* " << index << " */" << "\n";
473 o.indent(i * 2) << stringForModifierType(
474 (ModifierType)InstructionSpecifiers[index].modifierType);
477 o.indent(i * 2) << "0x";
478 o << format("%02hhx", (uint16_t)InstructionSpecifiers[index].modifierBase);
481 OperandListTy OperandList;
482 for (unsigned OperandIndex = 0; OperandIndex < X86_MAX_OPERANDS;
484 const char *Encoding =
485 stringForOperandEncoding((OperandEncoding)InstructionSpecifiers[index]
486 .operands[OperandIndex].encoding);
488 stringForOperandType((OperandType)InstructionSpecifiers[index]
489 .operands[OperandIndex].type);
490 OperandList.push_back(std::make_pair(Encoding, Type));
492 o.indent(i * 2) << (OperandSets[OperandList] - 1) << ",\n";
494 o.indent(i * 2) << "/* " << InstructionSpecifiers[index].name << " */";
498 o.indent(i * 2) << "}";
500 if (index + 1 < NumInstructions)
507 o.indent(i * 2) << "};" << "\n";
510 void DisassemblerTables::emitContextTable(raw_ostream &o, unsigned &i) const {
511 o.indent(i * 2) << "static const uint8_t " CONTEXTS_STR
515 for (unsigned index = 0; index < 256; ++index) {
518 if ((index & ATTR_VEXL) && (index & ATTR_REXW) && (index & ATTR_OPSIZE))
519 o << "IC_VEX_L_W_OPSIZE";
520 else if ((index & ATTR_VEXL) && (index & ATTR_OPSIZE))
521 o << "IC_VEX_L_OPSIZE";
522 else if ((index & ATTR_VEXL) && (index & ATTR_XD))
524 else if ((index & ATTR_VEXL) && (index & ATTR_XS))
526 else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_OPSIZE))
527 o << "IC_VEX_W_OPSIZE";
528 else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_XD))
530 else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_XS))
532 else if (index & ATTR_VEXL)
534 else if ((index & ATTR_VEX) && (index & ATTR_REXW))
536 else if ((index & ATTR_VEX) && (index & ATTR_OPSIZE))
537 o << "IC_VEX_OPSIZE";
538 else if ((index & ATTR_VEX) && (index & ATTR_XD))
540 else if ((index & ATTR_VEX) && (index & ATTR_XS))
542 else if (index & ATTR_VEX)
544 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && (index & ATTR_XS))
545 o << "IC_64BIT_REXW_XS";
546 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && (index & ATTR_XD))
547 o << "IC_64BIT_REXW_XD";
548 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) &&
549 (index & ATTR_OPSIZE))
550 o << "IC_64BIT_REXW_OPSIZE";
551 else if ((index & ATTR_64BIT) && (index & ATTR_XD) && (index & ATTR_OPSIZE))
552 o << "IC_64BIT_XD_OPSIZE";
553 else if ((index & ATTR_64BIT) && (index & ATTR_XS) && (index & ATTR_OPSIZE))
554 o << "IC_64BIT_XS_OPSIZE";
555 else if ((index & ATTR_64BIT) && (index & ATTR_XS))
557 else if ((index & ATTR_64BIT) && (index & ATTR_XD))
559 else if ((index & ATTR_64BIT) && (index & ATTR_OPSIZE))
560 o << "IC_64BIT_OPSIZE";
561 else if ((index & ATTR_64BIT) && (index & ATTR_ADSIZE))
562 o << "IC_64BIT_ADSIZE";
563 else if ((index & ATTR_64BIT) && (index & ATTR_REXW))
564 o << "IC_64BIT_REXW";
565 else if ((index & ATTR_64BIT))
567 else if ((index & ATTR_XS) && (index & ATTR_OPSIZE))
569 else if ((index & ATTR_XD) && (index & ATTR_OPSIZE))
571 else if (index & ATTR_XS)
573 else if (index & ATTR_XD)
575 else if (index & ATTR_OPSIZE)
577 else if (index & ATTR_ADSIZE)
587 o << " /* " << index << " */";
593 o.indent(i * 2) << "};" << "\n";
596 void DisassemblerTables::emitContextDecisions(raw_ostream &o1, raw_ostream &o2,
597 unsigned &i1, unsigned &i2) const {
598 emitContextDecision(o1, o2, i1, i2, *Tables[0], ONEBYTE_STR);
599 emitContextDecision(o1, o2, i1, i2, *Tables[1], TWOBYTE_STR);
600 emitContextDecision(o1, o2, i1, i2, *Tables[2], THREEBYTE38_STR);
601 emitContextDecision(o1, o2, i1, i2, *Tables[3], THREEBYTE3A_STR);
602 emitContextDecision(o1, o2, i1, i2, *Tables[4], THREEBYTEA6_STR);
603 emitContextDecision(o1, o2, i1, i2, *Tables[5], THREEBYTEA7_STR);
606 void DisassemblerTables::emit(raw_ostream &o) const {
613 raw_string_ostream o1(s1);
614 raw_string_ostream o2(s2);
616 emitInstructionInfo(o, i2);
619 emitContextTable(o, i2);
622 o << "static const InstrUID modRMTable[] = {\n";
624 emitEmptyTable(o1, i1);
626 emitContextDecisions(o1, o2, i1, i2);
637 void DisassemblerTables::setTableFields(ModRMDecision &decision,
638 const ModRMFilter &filter,
641 for (unsigned index = 0; index < 256; ++index) {
642 if (filter.accepts(index)) {
643 if (decision.instructionIDs[index] == uid)
646 if (decision.instructionIDs[index] != 0) {
647 InstructionSpecifier &newInfo =
648 InstructionSpecifiers[uid];
649 InstructionSpecifier &previousInfo =
650 InstructionSpecifiers[decision.instructionIDs[index]];
653 continue; // filtered instructions get lowest priority
655 if(previousInfo.name == "NOOP" && (newInfo.name == "XCHG16ar" ||
656 newInfo.name == "XCHG32ar" ||
657 newInfo.name == "XCHG32ar64" ||
658 newInfo.name == "XCHG64ar"))
659 continue; // special case for XCHG*ar and NOOP
661 if (outranks(previousInfo.insnContext, newInfo.insnContext))
664 if (previousInfo.insnContext == newInfo.insnContext &&
665 !previousInfo.filtered) {
666 errs() << "Error: Primary decode conflict: ";
667 errs() << newInfo.name << " would overwrite " << previousInfo.name;
669 errs() << "ModRM " << index << "\n";
670 errs() << "Opcode " << (uint16_t)opcode << "\n";
671 errs() << "Context " << stringForContext(newInfo.insnContext) << "\n";
676 decision.instructionIDs[index] = uid;
681 void DisassemblerTables::setTableFields(OpcodeType type,
682 InstructionContext insnContext,
684 const ModRMFilter &filter,
688 ContextDecision &decision = *Tables[type];
690 for (unsigned index = 0; index < IC_max; ++index) {
691 if (is32bit && inheritsFrom((InstructionContext)index, IC_64BIT))
694 if (inheritsFrom((InstructionContext)index,
695 InstructionSpecifiers[uid].insnContext, ignoresVEX_L))
696 setTableFields(decision.opcodeDecisions[index].modRMDecisions[opcode],