1 //===- SubtargetEmitter.cpp - Generate subtarget enumerations -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend emits subtarget enumerations.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "subtarget-emitter"
16 #include "CodeGenTarget.h"
17 #include "CodeGenSchedule.h"
18 #include "llvm/ADT/STLExtras.h"
19 #include "llvm/ADT/StringExtras.h"
20 #include "llvm/MC/MCInstrItineraries.h"
21 #include "llvm/Support/Debug.h"
22 #include "llvm/Support/Format.h"
23 #include "llvm/TableGen/Error.h"
24 #include "llvm/TableGen/Record.h"
25 #include "llvm/TableGen/TableGenBackend.h"
33 class SubtargetEmitter {
34 // Each processor has a SchedClassDesc table with an entry for each SchedClass.
35 // The SchedClassDesc table indexes into a global write resource table, write
36 // latency table, and read advance table.
37 struct SchedClassTables {
38 std::vector<std::vector<MCSchedClassDesc> > ProcSchedClasses;
39 std::vector<MCWriteProcResEntry> WriteProcResources;
40 std::vector<MCWriteLatencyEntry> WriteLatencies;
41 std::vector<std::string> WriterNames;
42 std::vector<MCReadAdvanceEntry> ReadAdvanceEntries;
44 // Reserve an invalid entry at index 0
46 ProcSchedClasses.resize(1);
47 WriteProcResources.resize(1);
48 WriteLatencies.resize(1);
49 WriterNames.push_back("InvalidWrite");
50 ReadAdvanceEntries.resize(1);
54 struct LessWriteProcResources {
55 bool operator()(const MCWriteProcResEntry &LHS,
56 const MCWriteProcResEntry &RHS) {
57 return LHS.ProcResourceIdx < RHS.ProcResourceIdx;
61 RecordKeeper &Records;
62 CodeGenSchedModels &SchedModels;
65 void Enumeration(raw_ostream &OS, const char *ClassName, bool isBits);
66 unsigned FeatureKeyValues(raw_ostream &OS);
67 unsigned CPUKeyValues(raw_ostream &OS);
68 void FormItineraryStageString(const std::string &Names,
69 Record *ItinData, std::string &ItinString,
71 void FormItineraryOperandCycleString(Record *ItinData, std::string &ItinString,
72 unsigned &NOperandCycles);
73 void FormItineraryBypassString(const std::string &Names,
75 std::string &ItinString, unsigned NOperandCycles);
76 void EmitStageAndOperandCycleData(raw_ostream &OS,
77 std::vector<std::vector<InstrItinerary> >
79 void EmitItineraries(raw_ostream &OS,
80 std::vector<std::vector<InstrItinerary> >
82 void EmitProcessorProp(raw_ostream &OS, const Record *R, const char *Name,
84 void EmitProcessorResources(const CodeGenProcModel &ProcModel,
86 Record *FindWriteResources(const CodeGenSchedRW &SchedWrite,
87 const CodeGenProcModel &ProcModel);
88 Record *FindReadAdvance(const CodeGenSchedRW &SchedRead,
89 const CodeGenProcModel &ProcModel);
90 void ExpandProcResources(RecVec &PRVec, std::vector<int64_t> &Cycles,
91 const CodeGenProcModel &ProcModel);
92 void GenSchedClassTables(const CodeGenProcModel &ProcModel,
93 SchedClassTables &SchedTables);
94 void EmitSchedClassTables(SchedClassTables &SchedTables, raw_ostream &OS);
95 void EmitProcessorModels(raw_ostream &OS);
96 void EmitProcessorLookup(raw_ostream &OS);
97 void EmitSchedModelHelpers(std::string ClassName, raw_ostream &OS);
98 void EmitSchedModel(raw_ostream &OS);
99 void ParseFeaturesFunction(raw_ostream &OS, unsigned NumFeatures,
103 SubtargetEmitter(RecordKeeper &R, CodeGenTarget &TGT):
104 Records(R), SchedModels(TGT.getSchedModels()), Target(TGT.getName()) {}
106 void run(raw_ostream &o);
109 } // End anonymous namespace
112 // Enumeration - Emit the specified class as an enumeration.
114 void SubtargetEmitter::Enumeration(raw_ostream &OS,
115 const char *ClassName,
117 // Get all records of class and sort
118 std::vector<Record*> DefList = Records.getAllDerivedDefinitions(ClassName);
119 std::sort(DefList.begin(), DefList.end(), LessRecord());
121 unsigned N = DefList.size();
125 errs() << "Too many (> 64) subtarget features!\n";
129 OS << "namespace " << Target << " {\n";
131 // For bit flag enumerations with more than 32 items, emit constants.
132 // Emit an enum for everything else.
133 if (isBits && N > 32) {
135 for (unsigned i = 0; i < N; i++) {
137 Record *Def = DefList[i];
139 // Get and emit name and expression (1 << i)
140 OS << " const uint64_t " << Def->getName() << " = 1ULL << " << i << ";\n";
147 for (unsigned i = 0; i < N;) {
149 Record *Def = DefList[i];
152 OS << " " << Def->getName();
154 // If bit flags then emit expression (1 << i)
155 if (isBits) OS << " = " << " 1ULL << " << i;
157 // Depending on 'if more in the list' emit comma
158 if (++i < N) OS << ",";
171 // FeatureKeyValues - Emit data of all the subtarget features. Used by the
174 unsigned SubtargetEmitter::FeatureKeyValues(raw_ostream &OS) {
175 // Gather and sort all the features
176 std::vector<Record*> FeatureList =
177 Records.getAllDerivedDefinitions("SubtargetFeature");
179 if (FeatureList.empty())
182 std::sort(FeatureList.begin(), FeatureList.end(), LessRecordFieldName());
184 // Begin feature table
185 OS << "// Sorted (by key) array of values for CPU features.\n"
186 << "extern const llvm::SubtargetFeatureKV " << Target
187 << "FeatureKV[] = {\n";
190 unsigned NumFeatures = 0;
191 for (unsigned i = 0, N = FeatureList.size(); i < N; ++i) {
193 Record *Feature = FeatureList[i];
195 const std::string &Name = Feature->getName();
196 const std::string &CommandLineName = Feature->getValueAsString("Name");
197 const std::string &Desc = Feature->getValueAsString("Desc");
199 if (CommandLineName.empty()) continue;
201 // Emit as { "feature", "description", featureEnum, i1 | i2 | ... | in }
203 << "\"" << CommandLineName << "\", "
204 << "\"" << Desc << "\", "
205 << Target << "::" << Name << ", ";
207 const std::vector<Record*> &ImpliesList =
208 Feature->getValueAsListOfDefs("Implies");
210 if (ImpliesList.empty()) {
213 for (unsigned j = 0, M = ImpliesList.size(); j < M;) {
214 OS << Target << "::" << ImpliesList[j]->getName();
215 if (++j < M) OS << " | ";
222 // Depending on 'if more in the list' emit comma
223 if ((i + 1) < N) OS << ",";
235 // CPUKeyValues - Emit data of all the subtarget processors. Used by command
238 unsigned SubtargetEmitter::CPUKeyValues(raw_ostream &OS) {
239 // Gather and sort processor information
240 std::vector<Record*> ProcessorList =
241 Records.getAllDerivedDefinitions("Processor");
242 std::sort(ProcessorList.begin(), ProcessorList.end(), LessRecordFieldName());
244 // Begin processor table
245 OS << "// Sorted (by key) array of values for CPU subtype.\n"
246 << "extern const llvm::SubtargetFeatureKV " << Target
247 << "SubTypeKV[] = {\n";
249 // For each processor
250 for (unsigned i = 0, N = ProcessorList.size(); i < N;) {
252 Record *Processor = ProcessorList[i];
254 const std::string &Name = Processor->getValueAsString("Name");
255 const std::vector<Record*> &FeatureList =
256 Processor->getValueAsListOfDefs("Features");
258 // Emit as { "cpu", "description", f1 | f2 | ... fn },
260 << "\"" << Name << "\", "
261 << "\"Select the " << Name << " processor\", ";
263 if (FeatureList.empty()) {
266 for (unsigned j = 0, M = FeatureList.size(); j < M;) {
267 OS << Target << "::" << FeatureList[j]->getName();
268 if (++j < M) OS << " | ";
272 // The "0" is for the "implies" section of this data structure.
275 // Depending on 'if more in the list' emit comma
276 if (++i < N) OS << ",";
281 // End processor table
284 return ProcessorList.size();
288 // FormItineraryStageString - Compose a string containing the stage
289 // data initialization for the specified itinerary. N is the number
292 void SubtargetEmitter::FormItineraryStageString(const std::string &Name,
294 std::string &ItinString,
297 const std::vector<Record*> &StageList =
298 ItinData->getValueAsListOfDefs("Stages");
301 unsigned N = NStages = StageList.size();
302 for (unsigned i = 0; i < N;) {
304 const Record *Stage = StageList[i];
306 // Form string as ,{ cycles, u1 | u2 | ... | un, timeinc, kind }
307 int Cycles = Stage->getValueAsInt("Cycles");
308 ItinString += " { " + itostr(Cycles) + ", ";
311 const std::vector<Record*> &UnitList = Stage->getValueAsListOfDefs("Units");
314 for (unsigned j = 0, M = UnitList.size(); j < M;) {
315 // Add name and bitwise or
316 ItinString += Name + "FU::" + UnitList[j]->getName();
317 if (++j < M) ItinString += " | ";
320 int TimeInc = Stage->getValueAsInt("TimeInc");
321 ItinString += ", " + itostr(TimeInc);
323 int Kind = Stage->getValueAsInt("Kind");
324 ItinString += ", (llvm::InstrStage::ReservationKinds)" + itostr(Kind);
328 if (++i < N) ItinString += ", ";
333 // FormItineraryOperandCycleString - Compose a string containing the
334 // operand cycle initialization for the specified itinerary. N is the
335 // number of operands that has cycles specified.
337 void SubtargetEmitter::FormItineraryOperandCycleString(Record *ItinData,
338 std::string &ItinString, unsigned &NOperandCycles) {
339 // Get operand cycle list
340 const std::vector<int64_t> &OperandCycleList =
341 ItinData->getValueAsListOfInts("OperandCycles");
343 // For each operand cycle
344 unsigned N = NOperandCycles = OperandCycleList.size();
345 for (unsigned i = 0; i < N;) {
346 // Next operand cycle
347 const int OCycle = OperandCycleList[i];
349 ItinString += " " + itostr(OCycle);
350 if (++i < N) ItinString += ", ";
354 void SubtargetEmitter::FormItineraryBypassString(const std::string &Name,
356 std::string &ItinString,
357 unsigned NOperandCycles) {
358 const std::vector<Record*> &BypassList =
359 ItinData->getValueAsListOfDefs("Bypasses");
360 unsigned N = BypassList.size();
363 ItinString += Name + "Bypass::" + BypassList[i]->getName();
364 if (++i < NOperandCycles) ItinString += ", ";
366 for (; i < NOperandCycles;) {
368 if (++i < NOperandCycles) ItinString += ", ";
373 // EmitStageAndOperandCycleData - Generate unique itinerary stages and operand
374 // cycle tables. Create a list of InstrItinerary objects (ProcItinLists) indexed
375 // by CodeGenSchedClass::Index.
377 void SubtargetEmitter::
378 EmitStageAndOperandCycleData(raw_ostream &OS,
379 std::vector<std::vector<InstrItinerary> >
382 // Multiple processor models may share an itinerary record. Emit it once.
383 SmallPtrSet<Record*, 8> ItinsDefSet;
385 // Emit functional units for all the itineraries.
386 for (CodeGenSchedModels::ProcIter PI = SchedModels.procModelBegin(),
387 PE = SchedModels.procModelEnd(); PI != PE; ++PI) {
389 if (!ItinsDefSet.insert(PI->ItinsDef))
392 std::vector<Record*> FUs = PI->ItinsDef->getValueAsListOfDefs("FU");
396 const std::string &Name = PI->ItinsDef->getName();
397 OS << "\n// Functional units for \"" << Name << "\"\n"
398 << "namespace " << Name << "FU {\n";
400 for (unsigned j = 0, FUN = FUs.size(); j < FUN; ++j)
401 OS << " const unsigned " << FUs[j]->getName()
402 << " = 1 << " << j << ";\n";
406 std::vector<Record*> BPs = PI->ItinsDef->getValueAsListOfDefs("BP");
408 OS << "\n// Pipeline forwarding pathes for itineraries \"" << Name
409 << "\"\n" << "namespace " << Name << "Bypass {\n";
411 OS << " const unsigned NoBypass = 0;\n";
412 for (unsigned j = 0, BPN = BPs.size(); j < BPN; ++j)
413 OS << " const unsigned " << BPs[j]->getName()
414 << " = 1 << " << j << ";\n";
420 // Begin stages table
421 std::string StageTable = "\nextern const llvm::InstrStage " + Target +
423 StageTable += " { 0, 0, 0, llvm::InstrStage::Required }, // No itinerary\n";
425 // Begin operand cycle table
426 std::string OperandCycleTable = "extern const unsigned " + Target +
427 "OperandCycles[] = {\n";
428 OperandCycleTable += " 0, // No itinerary\n";
430 // Begin pipeline bypass table
431 std::string BypassTable = "extern const unsigned " + Target +
432 "ForwardingPaths[] = {\n";
433 BypassTable += " 0, // No itinerary\n";
435 // For each Itinerary across all processors, add a unique entry to the stages,
436 // operand cycles, and pipepine bypess tables. Then add the new Itinerary
437 // object with computed offsets to the ProcItinLists result.
438 unsigned StageCount = 1, OperandCycleCount = 1;
439 std::map<std::string, unsigned> ItinStageMap, ItinOperandMap;
440 for (CodeGenSchedModels::ProcIter PI = SchedModels.procModelBegin(),
441 PE = SchedModels.procModelEnd(); PI != PE; ++PI) {
442 const CodeGenProcModel &ProcModel = *PI;
444 // Add process itinerary to the list.
445 ProcItinLists.resize(ProcItinLists.size()+1);
447 // If this processor defines no itineraries, then leave the itinerary list
449 std::vector<InstrItinerary> &ItinList = ProcItinLists.back();
450 if (ProcModel.ItinDefList.empty())
453 // Reserve index==0 for NoItinerary.
454 ItinList.resize(SchedModels.numItineraryClasses()+1);
456 const std::string &Name = ProcModel.ItinsDef->getName();
458 // For each itinerary data
459 for (unsigned SchedClassIdx = 0,
460 SchedClassEnd = ProcModel.ItinDefList.size();
461 SchedClassIdx < SchedClassEnd; ++SchedClassIdx) {
463 // Next itinerary data
464 Record *ItinData = ProcModel.ItinDefList[SchedClassIdx];
466 // Get string and stage count
467 std::string ItinStageString;
468 unsigned NStages = 0;
470 FormItineraryStageString(Name, ItinData, ItinStageString, NStages);
472 // Get string and operand cycle count
473 std::string ItinOperandCycleString;
474 unsigned NOperandCycles = 0;
475 std::string ItinBypassString;
477 FormItineraryOperandCycleString(ItinData, ItinOperandCycleString,
480 FormItineraryBypassString(Name, ItinData, ItinBypassString,
484 // Check to see if stage already exists and create if it doesn't
485 unsigned FindStage = 0;
487 FindStage = ItinStageMap[ItinStageString];
488 if (FindStage == 0) {
489 // Emit as { cycles, u1 | u2 | ... | un, timeinc }, // indices
490 StageTable += ItinStageString + ", // " + itostr(StageCount);
492 StageTable += "-" + itostr(StageCount + NStages - 1);
494 // Record Itin class number.
495 ItinStageMap[ItinStageString] = FindStage = StageCount;
496 StageCount += NStages;
500 // Check to see if operand cycle already exists and create if it doesn't
501 unsigned FindOperandCycle = 0;
502 if (NOperandCycles > 0) {
503 std::string ItinOperandString = ItinOperandCycleString+ItinBypassString;
504 FindOperandCycle = ItinOperandMap[ItinOperandString];
505 if (FindOperandCycle == 0) {
506 // Emit as cycle, // index
507 OperandCycleTable += ItinOperandCycleString + ", // ";
508 std::string OperandIdxComment = itostr(OperandCycleCount);
509 if (NOperandCycles > 1)
510 OperandIdxComment += "-"
511 + itostr(OperandCycleCount + NOperandCycles - 1);
512 OperandCycleTable += OperandIdxComment + "\n";
513 // Record Itin class number.
514 ItinOperandMap[ItinOperandCycleString] =
515 FindOperandCycle = OperandCycleCount;
516 // Emit as bypass, // index
517 BypassTable += ItinBypassString + ", // " + OperandIdxComment + "\n";
518 OperandCycleCount += NOperandCycles;
522 // Set up itinerary as location and location + stage count
523 int NumUOps = ItinData ? ItinData->getValueAsInt("NumMicroOps") : 0;
524 InstrItinerary Intinerary = { NumUOps, FindStage, FindStage + NStages,
526 FindOperandCycle + NOperandCycles};
528 // Inject - empty slots will be 0, 0
529 ItinList[SchedClassIdx] = Intinerary;
534 StageTable += " { 0, 0, 0, llvm::InstrStage::Required } // End stages\n";
535 StageTable += "};\n";
537 // Closing operand cycles
538 OperandCycleTable += " 0 // End operand cycles\n";
539 OperandCycleTable += "};\n";
541 BypassTable += " 0 // End bypass tables\n";
542 BypassTable += "};\n";
546 OS << OperandCycleTable;
551 // EmitProcessorData - Generate data for processor itineraries that were
552 // computed during EmitStageAndOperandCycleData(). ProcItinLists lists all
553 // Itineraries for each processor. The Itinerary lists are indexed on
554 // CodeGenSchedClass::Index.
556 void SubtargetEmitter::
557 EmitItineraries(raw_ostream &OS,
558 std::vector<std::vector<InstrItinerary> > &ProcItinLists) {
560 // Multiple processor models may share an itinerary record. Emit it once.
561 SmallPtrSet<Record*, 8> ItinsDefSet;
563 // For each processor's machine model
564 std::vector<std::vector<InstrItinerary> >::iterator
565 ProcItinListsIter = ProcItinLists.begin();
566 for (CodeGenSchedModels::ProcIter PI = SchedModels.procModelBegin(),
567 PE = SchedModels.procModelEnd(); PI != PE; ++PI, ++ProcItinListsIter) {
569 Record *ItinsDef = PI->ItinsDef;
570 if (!ItinsDefSet.insert(ItinsDef))
573 // Get processor itinerary name
574 const std::string &Name = ItinsDef->getName();
576 // Get the itinerary list for the processor.
577 assert(ProcItinListsIter != ProcItinLists.end() && "bad iterator");
578 std::vector<InstrItinerary> &ItinList = *ProcItinListsIter;
581 OS << "static const llvm::InstrItinerary ";
582 if (ItinList.empty()) {
583 OS << '*' << Name << " = 0;\n";
587 // Begin processor itinerary table
588 OS << Name << "[] = {\n";
590 // For each itinerary class in CodeGenSchedClass::Index order.
591 for (unsigned j = 0, M = ItinList.size(); j < M; ++j) {
592 InstrItinerary &Intinerary = ItinList[j];
594 // Emit Itinerary in the form of
595 // { firstStage, lastStage, firstCycle, lastCycle } // index
597 Intinerary.NumMicroOps << ", " <<
598 Intinerary.FirstStage << ", " <<
599 Intinerary.LastStage << ", " <<
600 Intinerary.FirstOperandCycle << ", " <<
601 Intinerary.LastOperandCycle << " }" <<
602 ", // " << j << " " << SchedModels.getSchedClass(j).Name << "\n";
604 // End processor itinerary table
605 OS << " { 0, ~0U, ~0U, ~0U, ~0U } // end marker\n";
610 // Emit either the value defined in the TableGen Record, or the default
611 // value defined in the C++ header. The Record is null if the processor does not
613 void SubtargetEmitter::EmitProcessorProp(raw_ostream &OS, const Record *R,
614 const char *Name, char Separator) {
616 int V = R ? R->getValueAsInt(Name) : -1;
618 OS << V << Separator << " // " << Name;
620 OS << "MCSchedModel::Default" << Name << Separator;
624 void SubtargetEmitter::EmitProcessorResources(const CodeGenProcModel &ProcModel,
626 char Sep = ProcModel.ProcResourceDefs.empty() ? ' ' : ',';
628 OS << "\n// {Name, NumUnits, SuperIdx, IsBuffered}\n";
629 OS << "static const llvm::MCProcResourceDesc "
630 << ProcModel.ModelName << "ProcResources" << "[] = {\n"
631 << " {DBGFIELD(\"InvalidUnit\") 0, 0, 0}" << Sep << "\n";
633 for (unsigned i = 0, e = ProcModel.ProcResourceDefs.size(); i < e; ++i) {
634 Record *PRDef = ProcModel.ProcResourceDefs[i];
636 Record *SuperDef = 0;
637 unsigned SuperIdx = 0;
638 unsigned NumUnits = 0;
639 bool IsBuffered = true;
640 if (PRDef->isSubClassOf("ProcResGroup")) {
641 RecVec ResUnits = PRDef->getValueAsListOfDefs("Resources");
642 for (RecIter RUI = ResUnits.begin(), RUE = ResUnits.end();
645 IsBuffered = (*RUI)->getValueAsBit("Buffered");
646 else if(IsBuffered != (*RUI)->getValueAsBit("Buffered"))
647 PrintFatalError(PRDef->getLoc(),
648 "Mixing buffered and unbuffered resources.");
649 NumUnits += (*RUI)->getValueAsInt("NumUnits");
654 if (PRDef->getValueInit("Super")->isComplete()) {
655 SuperDef = SchedModels.findProcResUnits(
656 PRDef->getValueAsDef("Super"), ProcModel);
657 SuperIdx = ProcModel.getProcResourceIdx(SuperDef);
660 // Emit the ProcResourceDesc
663 OS << " {DBGFIELD(\"" << PRDef->getName() << "\") ";
664 if (PRDef->getName().size() < 15)
665 OS.indent(15 - PRDef->getName().size());
666 OS << NumUnits << ", " << SuperIdx << ", "
667 << IsBuffered << "}" << Sep << " // #" << i+1;
669 OS << ", Super=" << SuperDef->getName();
675 // Find the WriteRes Record that defines processor resources for this
677 Record *SubtargetEmitter::FindWriteResources(
678 const CodeGenSchedRW &SchedWrite, const CodeGenProcModel &ProcModel) {
680 // Check if the SchedWrite is already subtarget-specific and directly
681 // specifies a set of processor resources.
682 if (SchedWrite.TheDef->isSubClassOf("SchedWriteRes"))
683 return SchedWrite.TheDef;
685 Record *AliasDef = 0;
686 for (RecIter AI = SchedWrite.Aliases.begin(), AE = SchedWrite.Aliases.end();
688 const CodeGenSchedRW &AliasRW =
689 SchedModels.getSchedRW((*AI)->getValueAsDef("AliasRW"));
690 if (AliasRW.TheDef->getValueInit("SchedModel")->isComplete()) {
691 Record *ModelDef = AliasRW.TheDef->getValueAsDef("SchedModel");
692 if (&SchedModels.getProcModel(ModelDef) != &ProcModel)
696 PrintFatalError(AliasRW.TheDef->getLoc(), "Multiple aliases "
697 "defined for processor " + ProcModel.ModelName +
698 " Ensure only one SchedAlias exists per RW.");
699 AliasDef = AliasRW.TheDef;
701 if (AliasDef && AliasDef->isSubClassOf("SchedWriteRes"))
704 // Check this processor's list of write resources.
706 for (RecIter WRI = ProcModel.WriteResDefs.begin(),
707 WRE = ProcModel.WriteResDefs.end(); WRI != WRE; ++WRI) {
708 if (!(*WRI)->isSubClassOf("WriteRes"))
710 if (AliasDef == (*WRI)->getValueAsDef("WriteType")
711 || SchedWrite.TheDef == (*WRI)->getValueAsDef("WriteType")) {
713 PrintFatalError((*WRI)->getLoc(), "Resources are defined for both "
714 "SchedWrite and its alias on processor " +
715 ProcModel.ModelName);
720 // TODO: If ProcModel has a base model (previous generation processor),
721 // then call FindWriteResources recursively with that model here.
723 PrintFatalError(ProcModel.ModelDef->getLoc(),
724 std::string("Processor does not define resources for ")
725 + SchedWrite.TheDef->getName());
730 /// Find the ReadAdvance record for the given SchedRead on this processor or
732 Record *SubtargetEmitter::FindReadAdvance(const CodeGenSchedRW &SchedRead,
733 const CodeGenProcModel &ProcModel) {
734 // Check for SchedReads that directly specify a ReadAdvance.
735 if (SchedRead.TheDef->isSubClassOf("SchedReadAdvance"))
736 return SchedRead.TheDef;
738 // Check this processor's list of aliases for SchedRead.
739 Record *AliasDef = 0;
740 for (RecIter AI = SchedRead.Aliases.begin(), AE = SchedRead.Aliases.end();
742 const CodeGenSchedRW &AliasRW =
743 SchedModels.getSchedRW((*AI)->getValueAsDef("AliasRW"));
744 if (AliasRW.TheDef->getValueInit("SchedModel")->isComplete()) {
745 Record *ModelDef = AliasRW.TheDef->getValueAsDef("SchedModel");
746 if (&SchedModels.getProcModel(ModelDef) != &ProcModel)
750 PrintFatalError(AliasRW.TheDef->getLoc(), "Multiple aliases "
751 "defined for processor " + ProcModel.ModelName +
752 " Ensure only one SchedAlias exists per RW.");
753 AliasDef = AliasRW.TheDef;
755 if (AliasDef && AliasDef->isSubClassOf("SchedReadAdvance"))
758 // Check this processor's ReadAdvanceList.
760 for (RecIter RAI = ProcModel.ReadAdvanceDefs.begin(),
761 RAE = ProcModel.ReadAdvanceDefs.end(); RAI != RAE; ++RAI) {
762 if (!(*RAI)->isSubClassOf("ReadAdvance"))
764 if (AliasDef == (*RAI)->getValueAsDef("ReadType")
765 || SchedRead.TheDef == (*RAI)->getValueAsDef("ReadType")) {
767 PrintFatalError((*RAI)->getLoc(), "Resources are defined for both "
768 "SchedRead and its alias on processor " +
769 ProcModel.ModelName);
774 // TODO: If ProcModel has a base model (previous generation processor),
775 // then call FindReadAdvance recursively with that model here.
776 if (!ResDef && SchedRead.TheDef->getName() != "ReadDefault") {
777 PrintFatalError(ProcModel.ModelDef->getLoc(),
778 std::string("Processor does not define resources for ")
779 + SchedRead.TheDef->getName());
784 // Expand an explicit list of processor resources into a full list of implied
785 // resource groups that cover them.
787 // FIXME: Effectively consider a super-resource a group that include all of its
788 // subresources to allow mixing and matching super-resources and groups.
790 // FIXME: Warn if two overlapping groups don't have a common supergroup.
791 void SubtargetEmitter::ExpandProcResources(RecVec &PRVec,
792 std::vector<int64_t> &Cycles,
793 const CodeGenProcModel &ProcModel) {
794 // Default to 1 resource cycle.
795 Cycles.resize(PRVec.size(), 1);
796 for (unsigned i = 0, e = PRVec.size(); i != e; ++i) {
798 if (PRVec[i]->isSubClassOf("ProcResGroup")) {
799 SubResources = PRVec[i]->getValueAsListOfDefs("Resources");
800 std::sort(SubResources.begin(), SubResources.end(), LessRecord());
803 SubResources.push_back(PRVec[i]);
805 for (RecIter PRI = ProcModel.ProcResourceDefs.begin(),
806 PRE = ProcModel.ProcResourceDefs.end();
808 if (*PRI == PRVec[i] || !(*PRI)->isSubClassOf("ProcResGroup"))
810 RecVec SuperResources = (*PRI)->getValueAsListOfDefs("Resources");
811 std::sort(SuperResources.begin(), SuperResources.end(), LessRecord());
812 RecIter SubI = SubResources.begin(), SubE = SubResources.end();
813 RecIter SuperI = SuperResources.begin(), SuperE = SuperResources.end();
814 for ( ; SubI != SubE && SuperI != SuperE; ++SuperI) {
817 else if (*SuperI < *SubI)
822 PRVec.push_back(*PRI);
823 Cycles.push_back(Cycles[i]);
829 // Generate the SchedClass table for this processor and update global
830 // tables. Must be called for each processor in order.
831 void SubtargetEmitter::GenSchedClassTables(const CodeGenProcModel &ProcModel,
832 SchedClassTables &SchedTables) {
833 SchedTables.ProcSchedClasses.resize(SchedTables.ProcSchedClasses.size() + 1);
834 if (!ProcModel.hasInstrSchedModel())
837 std::vector<MCSchedClassDesc> &SCTab = SchedTables.ProcSchedClasses.back();
838 for (CodeGenSchedModels::SchedClassIter SCI = SchedModels.schedClassBegin(),
839 SCE = SchedModels.schedClassEnd(); SCI != SCE; ++SCI) {
840 DEBUG(SCI->dump(&SchedModels));
842 SCTab.resize(SCTab.size() + 1);
843 MCSchedClassDesc &SCDesc = SCTab.back();
844 // SCDesc.Name is guarded by NDEBUG
845 SCDesc.NumMicroOps = 0;
846 SCDesc.BeginGroup = false;
847 SCDesc.EndGroup = false;
848 SCDesc.WriteProcResIdx = 0;
849 SCDesc.WriteLatencyIdx = 0;
850 SCDesc.ReadAdvanceIdx = 0;
852 // A Variant SchedClass has no resources of its own.
853 if (!SCI->Transitions.empty()) {
854 SCDesc.NumMicroOps = MCSchedClassDesc::VariantNumMicroOps;
858 // Determine if the SchedClass is actually reachable on this processor. If
859 // not don't try to locate the processor resources, it will fail.
860 // If ProcIndices contains 0, this class applies to all processors.
861 assert(!SCI->ProcIndices.empty() && "expect at least one procidx");
862 if (SCI->ProcIndices[0] != 0) {
863 IdxIter PIPos = std::find(SCI->ProcIndices.begin(),
864 SCI->ProcIndices.end(), ProcModel.Index);
865 if (PIPos == SCI->ProcIndices.end())
868 IdxVec Writes = SCI->Writes;
869 IdxVec Reads = SCI->Reads;
870 if (SCI->ItinClassDef) {
871 assert(SCI->InstRWs.empty() && "ItinClass should not have InstRWs");
872 // Check this processor's itinerary class resources.
873 for (RecIter II = ProcModel.ItinRWDefs.begin(),
874 IE = ProcModel.ItinRWDefs.end(); II != IE; ++II) {
875 RecVec Matched = (*II)->getValueAsListOfDefs("MatchedItinClasses");
876 if (std::find(Matched.begin(), Matched.end(), SCI->ItinClassDef)
878 SchedModels.findRWs((*II)->getValueAsListOfDefs("OperandReadWrites"),
883 if (Writes.empty()) {
884 DEBUG(dbgs() << ProcModel.ItinsDef->getName()
885 << " does not have resources for itinerary class "
886 << SCI->ItinClassDef->getName() << '\n');
889 else if (!SCI->InstRWs.empty()) {
890 // This class may have a default ReadWrite list which can be overriden by
891 // InstRW definitions.
893 for (RecIter RWI = SCI->InstRWs.begin(), RWE = SCI->InstRWs.end();
895 Record *RWModelDef = (*RWI)->getValueAsDef("SchedModel");
896 if (&ProcModel == &SchedModels.getProcModel(RWModelDef)) {
904 SchedModels.findRWs(RWDef->getValueAsListOfDefs("OperandReadWrites"),
908 // Sum resources across all operand writes.
909 std::vector<MCWriteProcResEntry> WriteProcResources;
910 std::vector<MCWriteLatencyEntry> WriteLatencies;
911 std::vector<std::string> WriterNames;
912 std::vector<MCReadAdvanceEntry> ReadAdvanceEntries;
913 for (IdxIter WI = Writes.begin(), WE = Writes.end(); WI != WE; ++WI) {
915 SchedModels.expandRWSeqForProc(*WI, WriteSeq, /*IsRead=*/false,
918 // For each operand, create a latency entry.
919 MCWriteLatencyEntry WLEntry;
921 unsigned WriteID = WriteSeq.back();
922 WriterNames.push_back(SchedModels.getSchedWrite(WriteID).Name);
923 // If this Write is not referenced by a ReadAdvance, don't distinguish it
924 // from other WriteLatency entries.
925 if (!SchedModels.hasReadOfWrite(SchedModels.getSchedWrite(WriteID).TheDef)) {
928 WLEntry.WriteResourceID = WriteID;
930 for (IdxIter WSI = WriteSeq.begin(), WSE = WriteSeq.end();
934 FindWriteResources(SchedModels.getSchedWrite(*WSI), ProcModel);
936 // Mark the parent class as invalid for unsupported write types.
937 if (WriteRes->getValueAsBit("Unsupported")) {
938 SCDesc.NumMicroOps = MCSchedClassDesc::InvalidNumMicroOps;
941 WLEntry.Cycles += WriteRes->getValueAsInt("Latency");
942 SCDesc.NumMicroOps += WriteRes->getValueAsInt("NumMicroOps");
943 SCDesc.BeginGroup |= WriteRes->getValueAsBit("BeginGroup");
944 SCDesc.EndGroup |= WriteRes->getValueAsBit("EndGroup");
946 // Create an entry for each ProcResource listed in WriteRes.
947 RecVec PRVec = WriteRes->getValueAsListOfDefs("ProcResources");
948 std::vector<int64_t> Cycles =
949 WriteRes->getValueAsListOfInts("ResourceCycles");
951 ExpandProcResources(PRVec, Cycles, ProcModel);
953 for (unsigned PRIdx = 0, PREnd = PRVec.size();
954 PRIdx != PREnd; ++PRIdx) {
955 MCWriteProcResEntry WPREntry;
956 WPREntry.ProcResourceIdx = ProcModel.getProcResourceIdx(PRVec[PRIdx]);
957 assert(WPREntry.ProcResourceIdx && "Bad ProcResourceIdx");
958 WPREntry.Cycles = Cycles[PRIdx];
959 // If this resource is already used in this sequence, add the current
960 // entry's cycles so that the same resource appears to be used
961 // serially, rather than multiple parallel uses. This is important for
962 // in-order machine where the resource consumption is a hazard.
963 unsigned WPRIdx = 0, WPREnd = WriteProcResources.size();
964 for( ; WPRIdx != WPREnd; ++WPRIdx) {
965 if (WriteProcResources[WPRIdx].ProcResourceIdx
966 == WPREntry.ProcResourceIdx) {
967 WriteProcResources[WPRIdx].Cycles += WPREntry.Cycles;
971 if (WPRIdx == WPREnd)
972 WriteProcResources.push_back(WPREntry);
975 WriteLatencies.push_back(WLEntry);
977 // Create an entry for each operand Read in this SchedClass.
978 // Entries must be sorted first by UseIdx then by WriteResourceID.
979 for (unsigned UseIdx = 0, EndIdx = Reads.size();
980 UseIdx != EndIdx; ++UseIdx) {
981 Record *ReadAdvance =
982 FindReadAdvance(SchedModels.getSchedRead(Reads[UseIdx]), ProcModel);
986 // Mark the parent class as invalid for unsupported write types.
987 if (ReadAdvance->getValueAsBit("Unsupported")) {
988 SCDesc.NumMicroOps = MCSchedClassDesc::InvalidNumMicroOps;
991 RecVec ValidWrites = ReadAdvance->getValueAsListOfDefs("ValidWrites");
993 if (ValidWrites.empty())
994 WriteIDs.push_back(0);
996 for (RecIter VWI = ValidWrites.begin(), VWE = ValidWrites.end();
998 WriteIDs.push_back(SchedModels.getSchedRWIdx(*VWI, /*IsRead=*/false));
1001 std::sort(WriteIDs.begin(), WriteIDs.end());
1002 for(IdxIter WI = WriteIDs.begin(), WE = WriteIDs.end(); WI != WE; ++WI) {
1003 MCReadAdvanceEntry RAEntry;
1004 RAEntry.UseIdx = UseIdx;
1005 RAEntry.WriteResourceID = *WI;
1006 RAEntry.Cycles = ReadAdvance->getValueAsInt("Cycles");
1007 ReadAdvanceEntries.push_back(RAEntry);
1010 if (SCDesc.NumMicroOps == MCSchedClassDesc::InvalidNumMicroOps) {
1011 WriteProcResources.clear();
1012 WriteLatencies.clear();
1013 ReadAdvanceEntries.clear();
1015 // Add the information for this SchedClass to the global tables using basic
1018 // WritePrecRes entries are sorted by ProcResIdx.
1019 std::sort(WriteProcResources.begin(), WriteProcResources.end(),
1020 LessWriteProcResources());
1022 SCDesc.NumWriteProcResEntries = WriteProcResources.size();
1023 std::vector<MCWriteProcResEntry>::iterator WPRPos =
1024 std::search(SchedTables.WriteProcResources.begin(),
1025 SchedTables.WriteProcResources.end(),
1026 WriteProcResources.begin(), WriteProcResources.end());
1027 if (WPRPos != SchedTables.WriteProcResources.end())
1028 SCDesc.WriteProcResIdx = WPRPos - SchedTables.WriteProcResources.begin();
1030 SCDesc.WriteProcResIdx = SchedTables.WriteProcResources.size();
1031 SchedTables.WriteProcResources.insert(WPRPos, WriteProcResources.begin(),
1032 WriteProcResources.end());
1034 // Latency entries must remain in operand order.
1035 SCDesc.NumWriteLatencyEntries = WriteLatencies.size();
1036 std::vector<MCWriteLatencyEntry>::iterator WLPos =
1037 std::search(SchedTables.WriteLatencies.begin(),
1038 SchedTables.WriteLatencies.end(),
1039 WriteLatencies.begin(), WriteLatencies.end());
1040 if (WLPos != SchedTables.WriteLatencies.end()) {
1041 unsigned idx = WLPos - SchedTables.WriteLatencies.begin();
1042 SCDesc.WriteLatencyIdx = idx;
1043 for (unsigned i = 0, e = WriteLatencies.size(); i < e; ++i)
1044 if (SchedTables.WriterNames[idx + i].find(WriterNames[i]) ==
1045 std::string::npos) {
1046 SchedTables.WriterNames[idx + i] += std::string("_") + WriterNames[i];
1050 SCDesc.WriteLatencyIdx = SchedTables.WriteLatencies.size();
1051 SchedTables.WriteLatencies.insert(SchedTables.WriteLatencies.end(),
1052 WriteLatencies.begin(),
1053 WriteLatencies.end());
1054 SchedTables.WriterNames.insert(SchedTables.WriterNames.end(),
1055 WriterNames.begin(), WriterNames.end());
1057 // ReadAdvanceEntries must remain in operand order.
1058 SCDesc.NumReadAdvanceEntries = ReadAdvanceEntries.size();
1059 std::vector<MCReadAdvanceEntry>::iterator RAPos =
1060 std::search(SchedTables.ReadAdvanceEntries.begin(),
1061 SchedTables.ReadAdvanceEntries.end(),
1062 ReadAdvanceEntries.begin(), ReadAdvanceEntries.end());
1063 if (RAPos != SchedTables.ReadAdvanceEntries.end())
1064 SCDesc.ReadAdvanceIdx = RAPos - SchedTables.ReadAdvanceEntries.begin();
1066 SCDesc.ReadAdvanceIdx = SchedTables.ReadAdvanceEntries.size();
1067 SchedTables.ReadAdvanceEntries.insert(RAPos, ReadAdvanceEntries.begin(),
1068 ReadAdvanceEntries.end());
1073 // Emit SchedClass tables for all processors and associated global tables.
1074 void SubtargetEmitter::EmitSchedClassTables(SchedClassTables &SchedTables,
1076 // Emit global WriteProcResTable.
1077 OS << "\n// {ProcResourceIdx, Cycles}\n"
1078 << "extern const llvm::MCWriteProcResEntry "
1079 << Target << "WriteProcResTable[] = {\n"
1080 << " { 0, 0}, // Invalid\n";
1081 for (unsigned WPRIdx = 1, WPREnd = SchedTables.WriteProcResources.size();
1082 WPRIdx != WPREnd; ++WPRIdx) {
1083 MCWriteProcResEntry &WPREntry = SchedTables.WriteProcResources[WPRIdx];
1084 OS << " {" << format("%2d", WPREntry.ProcResourceIdx) << ", "
1085 << format("%2d", WPREntry.Cycles) << "}";
1086 if (WPRIdx + 1 < WPREnd)
1088 OS << " // #" << WPRIdx << '\n';
1090 OS << "}; // " << Target << "WriteProcResTable\n";
1092 // Emit global WriteLatencyTable.
1093 OS << "\n// {Cycles, WriteResourceID}\n"
1094 << "extern const llvm::MCWriteLatencyEntry "
1095 << Target << "WriteLatencyTable[] = {\n"
1096 << " { 0, 0}, // Invalid\n";
1097 for (unsigned WLIdx = 1, WLEnd = SchedTables.WriteLatencies.size();
1098 WLIdx != WLEnd; ++WLIdx) {
1099 MCWriteLatencyEntry &WLEntry = SchedTables.WriteLatencies[WLIdx];
1100 OS << " {" << format("%2d", WLEntry.Cycles) << ", "
1101 << format("%2d", WLEntry.WriteResourceID) << "}";
1102 if (WLIdx + 1 < WLEnd)
1104 OS << " // #" << WLIdx << " " << SchedTables.WriterNames[WLIdx] << '\n';
1106 OS << "}; // " << Target << "WriteLatencyTable\n";
1108 // Emit global ReadAdvanceTable.
1109 OS << "\n// {UseIdx, WriteResourceID, Cycles}\n"
1110 << "extern const llvm::MCReadAdvanceEntry "
1111 << Target << "ReadAdvanceTable[] = {\n"
1112 << " {0, 0, 0}, // Invalid\n";
1113 for (unsigned RAIdx = 1, RAEnd = SchedTables.ReadAdvanceEntries.size();
1114 RAIdx != RAEnd; ++RAIdx) {
1115 MCReadAdvanceEntry &RAEntry = SchedTables.ReadAdvanceEntries[RAIdx];
1116 OS << " {" << RAEntry.UseIdx << ", "
1117 << format("%2d", RAEntry.WriteResourceID) << ", "
1118 << format("%2d", RAEntry.Cycles) << "}";
1119 if (RAIdx + 1 < RAEnd)
1121 OS << " // #" << RAIdx << '\n';
1123 OS << "}; // " << Target << "ReadAdvanceTable\n";
1125 // Emit a SchedClass table for each processor.
1126 for (CodeGenSchedModels::ProcIter PI = SchedModels.procModelBegin(),
1127 PE = SchedModels.procModelEnd(); PI != PE; ++PI) {
1128 if (!PI->hasInstrSchedModel())
1131 std::vector<MCSchedClassDesc> &SCTab =
1132 SchedTables.ProcSchedClasses[1 + (PI - SchedModels.procModelBegin())];
1134 OS << "\n// {Name, NumMicroOps, BeginGroup, EndGroup,"
1135 << " WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#}\n";
1136 OS << "static const llvm::MCSchedClassDesc "
1137 << PI->ModelName << "SchedClasses[] = {\n";
1139 // The first class is always invalid. We no way to distinguish it except by
1140 // name and position.
1141 assert(SchedModels.getSchedClass(0).Name == "NoItinerary"
1142 && "invalid class not first");
1143 OS << " {DBGFIELD(\"InvalidSchedClass\") "
1144 << MCSchedClassDesc::InvalidNumMicroOps
1145 << ", 0, 0, 0, 0, 0, 0, 0, 0},\n";
1147 for (unsigned SCIdx = 1, SCEnd = SCTab.size(); SCIdx != SCEnd; ++SCIdx) {
1148 MCSchedClassDesc &MCDesc = SCTab[SCIdx];
1149 const CodeGenSchedClass &SchedClass = SchedModels.getSchedClass(SCIdx);
1150 OS << " {DBGFIELD(\"" << SchedClass.Name << "\") ";
1151 if (SchedClass.Name.size() < 18)
1152 OS.indent(18 - SchedClass.Name.size());
1153 OS << MCDesc.NumMicroOps
1154 << ", " << MCDesc.BeginGroup << ", " << MCDesc.EndGroup
1155 << ", " << format("%2d", MCDesc.WriteProcResIdx)
1156 << ", " << MCDesc.NumWriteProcResEntries
1157 << ", " << format("%2d", MCDesc.WriteLatencyIdx)
1158 << ", " << MCDesc.NumWriteLatencyEntries
1159 << ", " << format("%2d", MCDesc.ReadAdvanceIdx)
1160 << ", " << MCDesc.NumReadAdvanceEntries << "}";
1161 if (SCIdx + 1 < SCEnd)
1163 OS << " // #" << SCIdx << '\n';
1165 OS << "}; // " << PI->ModelName << "SchedClasses\n";
1169 void SubtargetEmitter::EmitProcessorModels(raw_ostream &OS) {
1170 // For each processor model.
1171 for (CodeGenSchedModels::ProcIter PI = SchedModels.procModelBegin(),
1172 PE = SchedModels.procModelEnd(); PI != PE; ++PI) {
1173 // Emit processor resource table.
1174 if (PI->hasInstrSchedModel())
1175 EmitProcessorResources(*PI, OS);
1176 else if(!PI->ProcResourceDefs.empty())
1177 PrintFatalError(PI->ModelDef->getLoc(), "SchedMachineModel defines "
1178 "ProcResources without defining WriteRes SchedWriteRes");
1180 // Begin processor itinerary properties
1182 OS << "static const llvm::MCSchedModel " << PI->ModelName << "(\n";
1183 EmitProcessorProp(OS, PI->ModelDef, "IssueWidth", ',');
1184 EmitProcessorProp(OS, PI->ModelDef, "MinLatency", ',');
1185 EmitProcessorProp(OS, PI->ModelDef, "LoadLatency", ',');
1186 EmitProcessorProp(OS, PI->ModelDef, "HighLatency", ',');
1187 EmitProcessorProp(OS, PI->ModelDef, "ILPWindow", ',');
1188 EmitProcessorProp(OS, PI->ModelDef, "MispredictPenalty", ',');
1189 OS << " " << PI->Index << ", // Processor ID\n";
1190 if (PI->hasInstrSchedModel())
1191 OS << " " << PI->ModelName << "ProcResources" << ",\n"
1192 << " " << PI->ModelName << "SchedClasses" << ",\n"
1193 << " " << PI->ProcResourceDefs.size()+1 << ",\n"
1194 << " " << (SchedModels.schedClassEnd()
1195 - SchedModels.schedClassBegin()) << ",\n";
1197 OS << " 0, 0, 0, 0, // No instruction-level machine model.\n";
1198 if (SchedModels.hasItineraryClasses())
1199 OS << " " << PI->ItinsDef->getName() << ");\n";
1201 OS << " 0); // No Itinerary\n";
1206 // EmitProcessorLookup - generate cpu name to itinerary lookup table.
1208 void SubtargetEmitter::EmitProcessorLookup(raw_ostream &OS) {
1209 // Gather and sort processor information
1210 std::vector<Record*> ProcessorList =
1211 Records.getAllDerivedDefinitions("Processor");
1212 std::sort(ProcessorList.begin(), ProcessorList.end(), LessRecordFieldName());
1214 // Begin processor table
1216 OS << "// Sorted (by key) array of itineraries for CPU subtype.\n"
1217 << "extern const llvm::SubtargetInfoKV "
1218 << Target << "ProcSchedKV[] = {\n";
1220 // For each processor
1221 for (unsigned i = 0, N = ProcessorList.size(); i < N;) {
1223 Record *Processor = ProcessorList[i];
1225 const std::string &Name = Processor->getValueAsString("Name");
1226 const std::string &ProcModelName =
1227 SchedModels.getModelForProc(Processor).ModelName;
1229 // Emit as { "cpu", procinit },
1230 OS << " { \"" << Name << "\", (const void *)&" << ProcModelName << " }";
1232 // Depending on ''if more in the list'' emit comma
1233 if (++i < N) OS << ",";
1238 // End processor table
1243 // EmitSchedModel - Emits all scheduling model tables, folding common patterns.
1245 void SubtargetEmitter::EmitSchedModel(raw_ostream &OS) {
1246 OS << "#ifdef DBGFIELD\n"
1247 << "#error \"<target>GenSubtargetInfo.inc requires a DBGFIELD macro\"\n"
1249 << "#ifndef NDEBUG\n"
1250 << "#define DBGFIELD(x) x,\n"
1252 << "#define DBGFIELD(x)\n"
1255 if (SchedModels.hasItineraryClasses()) {
1256 std::vector<std::vector<InstrItinerary> > ProcItinLists;
1257 // Emit the stage data
1258 EmitStageAndOperandCycleData(OS, ProcItinLists);
1259 EmitItineraries(OS, ProcItinLists);
1261 OS << "\n// ===============================================================\n"
1262 << "// Data tables for the new per-operand machine model.\n";
1264 SchedClassTables SchedTables;
1265 for (CodeGenSchedModels::ProcIter PI = SchedModels.procModelBegin(),
1266 PE = SchedModels.procModelEnd(); PI != PE; ++PI) {
1267 GenSchedClassTables(*PI, SchedTables);
1269 EmitSchedClassTables(SchedTables, OS);
1271 // Emit the processor machine model
1272 EmitProcessorModels(OS);
1273 // Emit the processor lookup data
1274 EmitProcessorLookup(OS);
1276 OS << "#undef DBGFIELD";
1279 void SubtargetEmitter::EmitSchedModelHelpers(std::string ClassName,
1281 OS << "unsigned " << ClassName
1282 << "\n::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI,"
1283 << " const TargetSchedModel *SchedModel) const {\n";
1285 std::vector<Record*> Prologs = Records.getAllDerivedDefinitions("PredicateProlog");
1286 std::sort(Prologs.begin(), Prologs.end(), LessRecord());
1287 for (std::vector<Record*>::const_iterator
1288 PI = Prologs.begin(), PE = Prologs.end(); PI != PE; ++PI) {
1289 OS << (*PI)->getValueAsString("Code") << '\n';
1291 IdxVec VariantClasses;
1292 for (CodeGenSchedModels::SchedClassIter SCI = SchedModels.schedClassBegin(),
1293 SCE = SchedModels.schedClassEnd(); SCI != SCE; ++SCI) {
1294 if (SCI->Transitions.empty())
1296 VariantClasses.push_back(SCI - SchedModels.schedClassBegin());
1298 if (!VariantClasses.empty()) {
1299 OS << " switch (SchedClass) {\n";
1300 for (IdxIter VCI = VariantClasses.begin(), VCE = VariantClasses.end();
1301 VCI != VCE; ++VCI) {
1302 const CodeGenSchedClass &SC = SchedModels.getSchedClass(*VCI);
1303 OS << " case " << *VCI << ": // " << SC.Name << '\n';
1305 for (std::vector<CodeGenSchedTransition>::const_iterator
1306 TI = SC.Transitions.begin(), TE = SC.Transitions.end();
1309 std::set_union(TI->ProcIndices.begin(), TI->ProcIndices.end(),
1310 ProcIndices.begin(), ProcIndices.end(),
1311 std::back_inserter(PI));
1312 ProcIndices.swap(PI);
1314 for (IdxIter PI = ProcIndices.begin(), PE = ProcIndices.end();
1318 OS << "if (SchedModel->getProcessorID() == " << *PI << ") ";
1319 OS << "{ // " << (SchedModels.procModelBegin() + *PI)->ModelName
1321 for (std::vector<CodeGenSchedTransition>::const_iterator
1322 TI = SC.Transitions.begin(), TE = SC.Transitions.end();
1325 if (*PI != 0 && !std::count(TI->ProcIndices.begin(),
1326 TI->ProcIndices.end(), *PI)) {
1329 for (RecIter RI = TI->PredTerm.begin(), RE = TI->PredTerm.end();
1331 if (RI != TI->PredTerm.begin())
1333 OS << "(" << (*RI)->getValueAsString("Predicate") << ")";
1336 << " return " << TI->ToClassIdx << "; // "
1337 << SchedModels.getSchedClass(TI->ToClassIdx).Name << '\n';
1344 if (SC.ItinClassDef)
1345 SCIdx = SchedModels.getSchedClassIdxForItin(SC.ItinClassDef);
1347 SCIdx = SchedModels.findSchedClassIdx(SC.Writes, SC.Reads);
1349 OS << " return " << SCIdx << ";\n";
1354 OS << " report_fatal_error(\"Expected a variant SchedClass\");\n"
1355 << "} // " << ClassName << "::resolveSchedClass\n";
1359 // ParseFeaturesFunction - Produces a subtarget specific function for parsing
1360 // the subtarget features string.
1362 void SubtargetEmitter::ParseFeaturesFunction(raw_ostream &OS,
1363 unsigned NumFeatures,
1364 unsigned NumProcs) {
1365 std::vector<Record*> Features =
1366 Records.getAllDerivedDefinitions("SubtargetFeature");
1367 std::sort(Features.begin(), Features.end(), LessRecord());
1369 OS << "// ParseSubtargetFeatures - Parses features string setting specified\n"
1370 << "// subtarget options.\n"
1373 OS << "Subtarget::ParseSubtargetFeatures(StringRef CPU, StringRef FS) {\n"
1374 << " DEBUG(dbgs() << \"\\nFeatures:\" << FS);\n"
1375 << " DEBUG(dbgs() << \"\\nCPU:\" << CPU << \"\\n\\n\");\n";
1377 if (Features.empty()) {
1382 OS << " InitMCProcessorInfo(CPU, FS);\n"
1383 << " uint64_t Bits = getFeatureBits();\n";
1385 for (unsigned i = 0; i < Features.size(); i++) {
1387 Record *R = Features[i];
1388 const std::string &Instance = R->getName();
1389 const std::string &Value = R->getValueAsString("Value");
1390 const std::string &Attribute = R->getValueAsString("Attribute");
1392 if (Value=="true" || Value=="false")
1393 OS << " if ((Bits & " << Target << "::"
1394 << Instance << ") != 0) "
1395 << Attribute << " = " << Value << ";\n";
1397 OS << " if ((Bits & " << Target << "::"
1398 << Instance << ") != 0 && "
1399 << Attribute << " < " << Value << ") "
1400 << Attribute << " = " << Value << ";\n";
1407 // SubtargetEmitter::run - Main subtarget enumeration emitter.
1409 void SubtargetEmitter::run(raw_ostream &OS) {
1410 emitSourceFileHeader("Subtarget Enumeration Source Fragment", OS);
1412 OS << "\n#ifdef GET_SUBTARGETINFO_ENUM\n";
1413 OS << "#undef GET_SUBTARGETINFO_ENUM\n";
1415 OS << "namespace llvm {\n";
1416 Enumeration(OS, "SubtargetFeature", true);
1417 OS << "} // End llvm namespace \n";
1418 OS << "#endif // GET_SUBTARGETINFO_ENUM\n\n";
1420 OS << "\n#ifdef GET_SUBTARGETINFO_MC_DESC\n";
1421 OS << "#undef GET_SUBTARGETINFO_MC_DESC\n";
1423 OS << "namespace llvm {\n";
1425 OS << "namespace {\n";
1427 unsigned NumFeatures = FeatureKeyValues(OS);
1429 unsigned NumProcs = CPUKeyValues(OS);
1437 // MCInstrInfo initialization routine.
1438 OS << "static inline void Init" << Target
1439 << "MCSubtargetInfo(MCSubtargetInfo *II, "
1440 << "StringRef TT, StringRef CPU, StringRef FS) {\n";
1441 OS << " II->InitMCSubtargetInfo(TT, CPU, FS, ";
1443 OS << Target << "FeatureKV, ";
1447 OS << Target << "SubTypeKV, ";
1450 OS << '\n'; OS.indent(22);
1451 OS << Target << "ProcSchedKV, "
1452 << Target << "WriteProcResTable, "
1453 << Target << "WriteLatencyTable, "
1454 << Target << "ReadAdvanceTable, ";
1455 if (SchedModels.hasItineraryClasses()) {
1456 OS << '\n'; OS.indent(22);
1457 OS << Target << "Stages, "
1458 << Target << "OperandCycles, "
1459 << Target << "ForwardingPaths, ";
1462 OS << NumFeatures << ", " << NumProcs << ");\n}\n\n";
1464 OS << "} // End llvm namespace \n";
1466 OS << "#endif // GET_SUBTARGETINFO_MC_DESC\n\n";
1468 OS << "\n#ifdef GET_SUBTARGETINFO_TARGET_DESC\n";
1469 OS << "#undef GET_SUBTARGETINFO_TARGET_DESC\n";
1471 OS << "#include \"llvm/Support/Debug.h\"\n";
1472 OS << "#include \"llvm/Support/raw_ostream.h\"\n";
1473 ParseFeaturesFunction(OS, NumFeatures, NumProcs);
1475 OS << "#endif // GET_SUBTARGETINFO_TARGET_DESC\n\n";
1477 // Create a TargetSubtargetInfo subclass to hide the MC layer initialization.
1478 OS << "\n#ifdef GET_SUBTARGETINFO_HEADER\n";
1479 OS << "#undef GET_SUBTARGETINFO_HEADER\n";
1481 std::string ClassName = Target + "GenSubtargetInfo";
1482 OS << "namespace llvm {\n";
1483 OS << "class DFAPacketizer;\n";
1484 OS << "struct " << ClassName << " : public TargetSubtargetInfo {\n"
1485 << " explicit " << ClassName << "(StringRef TT, StringRef CPU, "
1486 << "StringRef FS);\n"
1488 << " unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI,"
1489 << " const TargetSchedModel *SchedModel) const;\n"
1490 << " DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID)"
1493 OS << "} // End llvm namespace \n";
1495 OS << "#endif // GET_SUBTARGETINFO_HEADER\n\n";
1497 OS << "\n#ifdef GET_SUBTARGETINFO_CTOR\n";
1498 OS << "#undef GET_SUBTARGETINFO_CTOR\n";
1500 OS << "#include \"llvm/CodeGen/TargetSchedule.h\"\n";
1501 OS << "namespace llvm {\n";
1502 OS << "extern const llvm::SubtargetFeatureKV " << Target << "FeatureKV[];\n";
1503 OS << "extern const llvm::SubtargetFeatureKV " << Target << "SubTypeKV[];\n";
1504 OS << "extern const llvm::SubtargetInfoKV " << Target << "ProcSchedKV[];\n";
1505 OS << "extern const llvm::MCWriteProcResEntry "
1506 << Target << "WriteProcResTable[];\n";
1507 OS << "extern const llvm::MCWriteLatencyEntry "
1508 << Target << "WriteLatencyTable[];\n";
1509 OS << "extern const llvm::MCReadAdvanceEntry "
1510 << Target << "ReadAdvanceTable[];\n";
1512 if (SchedModels.hasItineraryClasses()) {
1513 OS << "extern const llvm::InstrStage " << Target << "Stages[];\n";
1514 OS << "extern const unsigned " << Target << "OperandCycles[];\n";
1515 OS << "extern const unsigned " << Target << "ForwardingPaths[];\n";
1518 OS << ClassName << "::" << ClassName << "(StringRef TT, StringRef CPU, "
1519 << "StringRef FS)\n"
1520 << " : TargetSubtargetInfo() {\n"
1521 << " InitMCSubtargetInfo(TT, CPU, FS, ";
1523 OS << Target << "FeatureKV, ";
1527 OS << Target << "SubTypeKV, ";
1530 OS << '\n'; OS.indent(22);
1531 OS << Target << "ProcSchedKV, "
1532 << Target << "WriteProcResTable, "
1533 << Target << "WriteLatencyTable, "
1534 << Target << "ReadAdvanceTable, ";
1535 OS << '\n'; OS.indent(22);
1536 if (SchedModels.hasItineraryClasses()) {
1537 OS << Target << "Stages, "
1538 << Target << "OperandCycles, "
1539 << Target << "ForwardingPaths, ";
1542 OS << NumFeatures << ", " << NumProcs << ");\n}\n\n";
1544 EmitSchedModelHelpers(ClassName, OS);
1546 OS << "} // End llvm namespace \n";
1548 OS << "#endif // GET_SUBTARGETINFO_CTOR\n\n";
1553 void EmitSubtarget(RecordKeeper &RK, raw_ostream &OS) {
1554 CodeGenTarget CGTarget(RK);
1555 SubtargetEmitter(RK, CGTarget).run(OS);
1558 } // End llvm namespace