1 //===- SubtargetEmitter.cpp - Generate subtarget enumerations -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend emits subtarget enumerations.
12 //===----------------------------------------------------------------------===//
14 #include "CodeGenTarget.h"
15 #include "CodeGenSchedule.h"
16 #include "llvm/ADT/StringExtras.h"
17 #include "llvm/MC/MCInstrItineraries.h"
18 #include "llvm/Support/Debug.h"
19 #include "llvm/TableGen/Record.h"
20 #include "llvm/TableGen/TableGenBackend.h"
28 class SubtargetEmitter {
30 RecordKeeper &Records;
31 CodeGenSchedModels &SchedModels;
34 void Enumeration(raw_ostream &OS, const char *ClassName, bool isBits);
35 unsigned FeatureKeyValues(raw_ostream &OS);
36 unsigned CPUKeyValues(raw_ostream &OS);
37 void FormItineraryStageString(const std::string &Names,
38 Record *ItinData, std::string &ItinString,
40 void FormItineraryOperandCycleString(Record *ItinData, std::string &ItinString,
41 unsigned &NOperandCycles);
42 void FormItineraryBypassString(const std::string &Names,
44 std::string &ItinString, unsigned NOperandCycles);
45 void EmitStageAndOperandCycleData(raw_ostream &OS,
46 std::vector<std::vector<InstrItinerary> >
48 void EmitItineraries(raw_ostream &OS,
49 std::vector<std::vector<InstrItinerary> >
51 void EmitProcessorProp(raw_ostream &OS, const Record *R, const char *Name,
53 void EmitProcessorModels(raw_ostream &OS);
54 void EmitProcessorLookup(raw_ostream &OS);
55 void EmitSchedModel(raw_ostream &OS);
56 void ParseFeaturesFunction(raw_ostream &OS, unsigned NumFeatures,
60 SubtargetEmitter(RecordKeeper &R, CodeGenTarget &TGT):
61 Records(R), SchedModels(TGT.getSchedModels()), Target(TGT.getName()) {}
63 void run(raw_ostream &o);
66 } // End anonymous namespace
69 // Enumeration - Emit the specified class as an enumeration.
71 void SubtargetEmitter::Enumeration(raw_ostream &OS,
72 const char *ClassName,
74 // Get all records of class and sort
75 std::vector<Record*> DefList = Records.getAllDerivedDefinitions(ClassName);
76 std::sort(DefList.begin(), DefList.end(), LessRecord());
78 unsigned N = DefList.size();
82 errs() << "Too many (> 64) subtarget features!\n";
86 OS << "namespace " << Target << " {\n";
88 // For bit flag enumerations with more than 32 items, emit constants.
89 // Emit an enum for everything else.
90 if (isBits && N > 32) {
92 for (unsigned i = 0; i < N; i++) {
94 Record *Def = DefList[i];
96 // Get and emit name and expression (1 << i)
97 OS << " const uint64_t " << Def->getName() << " = 1ULL << " << i << ";\n";
104 for (unsigned i = 0; i < N;) {
106 Record *Def = DefList[i];
109 OS << " " << Def->getName();
111 // If bit flags then emit expression (1 << i)
112 if (isBits) OS << " = " << " 1ULL << " << i;
114 // Depending on 'if more in the list' emit comma
115 if (++i < N) OS << ",";
128 // FeatureKeyValues - Emit data of all the subtarget features. Used by the
131 unsigned SubtargetEmitter::FeatureKeyValues(raw_ostream &OS) {
132 // Gather and sort all the features
133 std::vector<Record*> FeatureList =
134 Records.getAllDerivedDefinitions("SubtargetFeature");
136 if (FeatureList.empty())
139 std::sort(FeatureList.begin(), FeatureList.end(), LessRecordFieldName());
141 // Begin feature table
142 OS << "// Sorted (by key) array of values for CPU features.\n"
143 << "extern const llvm::SubtargetFeatureKV " << Target
144 << "FeatureKV[] = {\n";
147 unsigned NumFeatures = 0;
148 for (unsigned i = 0, N = FeatureList.size(); i < N; ++i) {
150 Record *Feature = FeatureList[i];
152 const std::string &Name = Feature->getName();
153 const std::string &CommandLineName = Feature->getValueAsString("Name");
154 const std::string &Desc = Feature->getValueAsString("Desc");
156 if (CommandLineName.empty()) continue;
158 // Emit as { "feature", "description", featureEnum, i1 | i2 | ... | in }
160 << "\"" << CommandLineName << "\", "
161 << "\"" << Desc << "\", "
162 << Target << "::" << Name << ", ";
164 const std::vector<Record*> &ImpliesList =
165 Feature->getValueAsListOfDefs("Implies");
167 if (ImpliesList.empty()) {
170 for (unsigned j = 0, M = ImpliesList.size(); j < M;) {
171 OS << Target << "::" << ImpliesList[j]->getName();
172 if (++j < M) OS << " | ";
179 // Depending on 'if more in the list' emit comma
180 if ((i + 1) < N) OS << ",";
192 // CPUKeyValues - Emit data of all the subtarget processors. Used by command
195 unsigned SubtargetEmitter::CPUKeyValues(raw_ostream &OS) {
196 // Gather and sort processor information
197 std::vector<Record*> ProcessorList =
198 Records.getAllDerivedDefinitions("Processor");
199 std::sort(ProcessorList.begin(), ProcessorList.end(), LessRecordFieldName());
201 // Begin processor table
202 OS << "// Sorted (by key) array of values for CPU subtype.\n"
203 << "extern const llvm::SubtargetFeatureKV " << Target
204 << "SubTypeKV[] = {\n";
206 // For each processor
207 for (unsigned i = 0, N = ProcessorList.size(); i < N;) {
209 Record *Processor = ProcessorList[i];
211 const std::string &Name = Processor->getValueAsString("Name");
212 const std::vector<Record*> &FeatureList =
213 Processor->getValueAsListOfDefs("Features");
215 // Emit as { "cpu", "description", f1 | f2 | ... fn },
217 << "\"" << Name << "\", "
218 << "\"Select the " << Name << " processor\", ";
220 if (FeatureList.empty()) {
223 for (unsigned j = 0, M = FeatureList.size(); j < M;) {
224 OS << Target << "::" << FeatureList[j]->getName();
225 if (++j < M) OS << " | ";
229 // The "0" is for the "implies" section of this data structure.
232 // Depending on 'if more in the list' emit comma
233 if (++i < N) OS << ",";
238 // End processor table
241 return ProcessorList.size();
245 // FormItineraryStageString - Compose a string containing the stage
246 // data initialization for the specified itinerary. N is the number
249 void SubtargetEmitter::FormItineraryStageString(const std::string &Name,
251 std::string &ItinString,
254 const std::vector<Record*> &StageList =
255 ItinData->getValueAsListOfDefs("Stages");
258 unsigned N = NStages = StageList.size();
259 for (unsigned i = 0; i < N;) {
261 const Record *Stage = StageList[i];
263 // Form string as ,{ cycles, u1 | u2 | ... | un, timeinc, kind }
264 int Cycles = Stage->getValueAsInt("Cycles");
265 ItinString += " { " + itostr(Cycles) + ", ";
268 const std::vector<Record*> &UnitList = Stage->getValueAsListOfDefs("Units");
271 for (unsigned j = 0, M = UnitList.size(); j < M;) {
272 // Add name and bitwise or
273 ItinString += Name + "FU::" + UnitList[j]->getName();
274 if (++j < M) ItinString += " | ";
277 int TimeInc = Stage->getValueAsInt("TimeInc");
278 ItinString += ", " + itostr(TimeInc);
280 int Kind = Stage->getValueAsInt("Kind");
281 ItinString += ", (llvm::InstrStage::ReservationKinds)" + itostr(Kind);
285 if (++i < N) ItinString += ", ";
290 // FormItineraryOperandCycleString - Compose a string containing the
291 // operand cycle initialization for the specified itinerary. N is the
292 // number of operands that has cycles specified.
294 void SubtargetEmitter::FormItineraryOperandCycleString(Record *ItinData,
295 std::string &ItinString, unsigned &NOperandCycles) {
296 // Get operand cycle list
297 const std::vector<int64_t> &OperandCycleList =
298 ItinData->getValueAsListOfInts("OperandCycles");
300 // For each operand cycle
301 unsigned N = NOperandCycles = OperandCycleList.size();
302 for (unsigned i = 0; i < N;) {
303 // Next operand cycle
304 const int OCycle = OperandCycleList[i];
306 ItinString += " " + itostr(OCycle);
307 if (++i < N) ItinString += ", ";
311 void SubtargetEmitter::FormItineraryBypassString(const std::string &Name,
313 std::string &ItinString,
314 unsigned NOperandCycles) {
315 const std::vector<Record*> &BypassList =
316 ItinData->getValueAsListOfDefs("Bypasses");
317 unsigned N = BypassList.size();
320 ItinString += Name + "Bypass::" + BypassList[i]->getName();
321 if (++i < NOperandCycles) ItinString += ", ";
323 for (; i < NOperandCycles;) {
325 if (++i < NOperandCycles) ItinString += ", ";
330 // EmitStageAndOperandCycleData - Generate unique itinerary stages and operand
331 // cycle tables. Create a list of InstrItinerary objects (ProcItinLists) indexed
332 // by CodeGenSchedClass::Index.
334 void SubtargetEmitter::
335 EmitStageAndOperandCycleData(raw_ostream &OS,
336 std::vector<std::vector<InstrItinerary> >
339 // Multiple processor models may share an itinerary record. Emit it once.
340 SmallPtrSet<Record*, 8> ItinsDefSet;
342 // Emit functional units for all the itineraries.
343 for (CodeGenSchedModels::ProcIter PI = SchedModels.procModelBegin(),
344 PE = SchedModels.procModelEnd(); PI != PE; ++PI) {
346 if (!ItinsDefSet.insert(PI->ItinsDef))
349 std::vector<Record*> FUs = PI->ItinsDef->getValueAsListOfDefs("FU");
353 const std::string &Name = PI->ItinsDef->getName();
354 OS << "\n// Functional units for \"" << Name << "\"\n"
355 << "namespace " << Name << "FU {\n";
357 for (unsigned j = 0, FUN = FUs.size(); j < FUN; ++j)
358 OS << " const unsigned " << FUs[j]->getName()
359 << " = 1 << " << j << ";\n";
363 std::vector<Record*> BPs = PI->ItinsDef->getValueAsListOfDefs("BP");
365 OS << "\n// Pipeline forwarding pathes for itineraries \"" << Name
366 << "\"\n" << "namespace " << Name << "Bypass {\n";
368 OS << " const unsigned NoBypass = 0;\n";
369 for (unsigned j = 0, BPN = BPs.size(); j < BPN; ++j)
370 OS << " const unsigned " << BPs[j]->getName()
371 << " = 1 << " << j << ";\n";
377 // Begin stages table
378 std::string StageTable = "\nextern const llvm::InstrStage " + Target +
380 StageTable += " { 0, 0, 0, llvm::InstrStage::Required }, // No itinerary\n";
382 // Begin operand cycle table
383 std::string OperandCycleTable = "extern const unsigned " + Target +
384 "OperandCycles[] = {\n";
385 OperandCycleTable += " 0, // No itinerary\n";
387 // Begin pipeline bypass table
388 std::string BypassTable = "extern const unsigned " + Target +
389 "ForwardingPaths[] = {\n";
390 BypassTable += " 0, // No itinerary\n";
392 // For each Itinerary across all processors, add a unique entry to the stages,
393 // operand cycles, and pipepine bypess tables. Then add the new Itinerary
394 // object with computed offsets to the ProcItinLists result.
395 unsigned StageCount = 1, OperandCycleCount = 1;
396 std::map<std::string, unsigned> ItinStageMap, ItinOperandMap;
397 for (CodeGenSchedModels::ProcIter PI = SchedModels.procModelBegin(),
398 PE = SchedModels.procModelEnd(); PI != PE; ++PI) {
399 const CodeGenProcModel &ProcModel = *PI;
401 // Add process itinerary to the list.
402 ProcItinLists.resize(ProcItinLists.size()+1);
404 // If this processor defines no itineraries, then leave the itinerary list
406 std::vector<InstrItinerary> &ItinList = ProcItinLists.back();
407 if (ProcModel.ItinDefList.empty())
410 // Reserve index==0 for NoItinerary.
411 ItinList.resize(SchedModels.numItineraryClasses()+1);
413 const std::string &Name = ProcModel.ItinsDef->getName();
415 // For each itinerary data
416 for (unsigned SchedClassIdx = 0,
417 SchedClassEnd = ProcModel.ItinDefList.size();
418 SchedClassIdx < SchedClassEnd; ++SchedClassIdx) {
420 // Next itinerary data
421 Record *ItinData = ProcModel.ItinDefList[SchedClassIdx];
423 // Get string and stage count
424 std::string ItinStageString;
425 unsigned NStages = 0;
427 FormItineraryStageString(Name, ItinData, ItinStageString, NStages);
429 // Get string and operand cycle count
430 std::string ItinOperandCycleString;
431 unsigned NOperandCycles = 0;
432 std::string ItinBypassString;
434 FormItineraryOperandCycleString(ItinData, ItinOperandCycleString,
437 FormItineraryBypassString(Name, ItinData, ItinBypassString,
441 // Check to see if stage already exists and create if it doesn't
442 unsigned FindStage = 0;
444 FindStage = ItinStageMap[ItinStageString];
445 if (FindStage == 0) {
446 // Emit as { cycles, u1 | u2 | ... | un, timeinc }, // indices
447 StageTable += ItinStageString + ", // " + itostr(StageCount);
449 StageTable += "-" + itostr(StageCount + NStages - 1);
451 // Record Itin class number.
452 ItinStageMap[ItinStageString] = FindStage = StageCount;
453 StageCount += NStages;
457 // Check to see if operand cycle already exists and create if it doesn't
458 unsigned FindOperandCycle = 0;
459 if (NOperandCycles > 0) {
460 std::string ItinOperandString = ItinOperandCycleString+ItinBypassString;
461 FindOperandCycle = ItinOperandMap[ItinOperandString];
462 if (FindOperandCycle == 0) {
463 // Emit as cycle, // index
464 OperandCycleTable += ItinOperandCycleString + ", // ";
465 std::string OperandIdxComment = itostr(OperandCycleCount);
466 if (NOperandCycles > 1)
467 OperandIdxComment += "-"
468 + itostr(OperandCycleCount + NOperandCycles - 1);
469 OperandCycleTable += OperandIdxComment + "\n";
470 // Record Itin class number.
471 ItinOperandMap[ItinOperandCycleString] =
472 FindOperandCycle = OperandCycleCount;
473 // Emit as bypass, // index
474 BypassTable += ItinBypassString + ", // " + OperandIdxComment + "\n";
475 OperandCycleCount += NOperandCycles;
479 // Set up itinerary as location and location + stage count
480 int NumUOps = ItinData ? ItinData->getValueAsInt("NumMicroOps") : 0;
481 InstrItinerary Intinerary = { NumUOps, FindStage, FindStage + NStages,
483 FindOperandCycle + NOperandCycles};
485 // Inject - empty slots will be 0, 0
486 ItinList[SchedClassIdx] = Intinerary;
491 StageTable += " { 0, 0, 0, llvm::InstrStage::Required } // End stages\n";
492 StageTable += "};\n";
494 // Closing operand cycles
495 OperandCycleTable += " 0 // End operand cycles\n";
496 OperandCycleTable += "};\n";
498 BypassTable += " 0 // End bypass tables\n";
499 BypassTable += "};\n";
503 OS << OperandCycleTable;
508 // EmitProcessorData - Generate data for processor itineraries that were
509 // computed during EmitStageAndOperandCycleData(). ProcItinLists lists all
510 // Itineraries for each processor. The Itinerary lists are indexed on
511 // CodeGenSchedClass::Index.
513 void SubtargetEmitter::
514 EmitItineraries(raw_ostream &OS,
515 std::vector<std::vector<InstrItinerary> > &ProcItinLists) {
517 // Multiple processor models may share an itinerary record. Emit it once.
518 SmallPtrSet<Record*, 8> ItinsDefSet;
520 // For each processor's machine model
521 std::vector<std::vector<InstrItinerary> >::iterator
522 ProcItinListsIter = ProcItinLists.begin();
523 for (CodeGenSchedModels::ProcIter PI = SchedModels.procModelBegin(),
524 PE = SchedModels.procModelEnd(); PI != PE; ++PI) {
526 Record *ItinsDef = PI->ItinsDef;
527 if (!ItinsDefSet.insert(ItinsDef))
530 // Get processor itinerary name
531 const std::string &Name = ItinsDef->getName();
533 // Get the itinerary list for the processor.
534 assert(ProcItinListsIter != ProcItinLists.end() && "bad iterator");
535 std::vector<InstrItinerary> &ItinList = *ProcItinListsIter++;
538 OS << "static const llvm::InstrItinerary ";
539 if (ItinList.empty()) {
540 OS << '*' << Name << " = 0;\n";
544 // Begin processor itinerary table
545 OS << Name << "[] = {\n";
547 // For each itinerary class in CodeGenSchedClass::Index order.
548 for (unsigned j = 0, M = ItinList.size(); j < M; ++j) {
549 InstrItinerary &Intinerary = ItinList[j];
551 // Emit Itinerary in the form of
552 // { firstStage, lastStage, firstCycle, lastCycle } // index
554 Intinerary.NumMicroOps << ", " <<
555 Intinerary.FirstStage << ", " <<
556 Intinerary.LastStage << ", " <<
557 Intinerary.FirstOperandCycle << ", " <<
558 Intinerary.LastOperandCycle << " }" <<
559 ", // " << j << " " << SchedModels.getSchedClass(j).Name << "\n";
561 // End processor itinerary table
562 OS << " { 0, ~0U, ~0U, ~0U, ~0U } // end marker\n";
567 // Emit either the value defined in the TableGen Record, or the default
568 // value defined in the C++ header. The Record is null if the processor does not
570 void SubtargetEmitter::EmitProcessorProp(raw_ostream &OS, const Record *R,
571 const char *Name, char Separator) {
573 int V = R ? R->getValueAsInt(Name) : -1;
575 OS << V << Separator << " // " << Name;
577 OS << "MCSchedModel::Default" << Name << Separator;
581 void SubtargetEmitter::EmitProcessorModels(raw_ostream &OS) {
582 // For each processor model.
583 for (CodeGenSchedModels::ProcIter PI = SchedModels.procModelBegin(),
584 PE = SchedModels.procModelEnd(); PI != PE; ++PI) {
586 // Begin processor itinerary properties
588 OS << "static const llvm::MCSchedModel " << PI->ModelName << "(\n";
589 EmitProcessorProp(OS, PI->ModelDef, "IssueWidth", ',');
590 EmitProcessorProp(OS, PI->ModelDef, "MinLatency", ',');
591 EmitProcessorProp(OS, PI->ModelDef, "LoadLatency", ',');
592 EmitProcessorProp(OS, PI->ModelDef, "HighLatency", ',');
593 EmitProcessorProp(OS, PI->ModelDef, "MispredictPenalty", ',');
594 if (SchedModels.hasItineraryClasses())
595 OS << " " << PI->ItinsDef->getName();
603 // EmitProcessorLookup - generate cpu name to itinerary lookup table.
605 void SubtargetEmitter::EmitProcessorLookup(raw_ostream &OS) {
606 // Gather and sort processor information
607 std::vector<Record*> ProcessorList =
608 Records.getAllDerivedDefinitions("Processor");
609 std::sort(ProcessorList.begin(), ProcessorList.end(), LessRecordFieldName());
611 // Begin processor table
613 OS << "// Sorted (by key) array of itineraries for CPU subtype.\n"
614 << "extern const llvm::SubtargetInfoKV "
615 << Target << "ProcSchedKV[] = {\n";
617 // For each processor
618 for (unsigned i = 0, N = ProcessorList.size(); i < N;) {
620 Record *Processor = ProcessorList[i];
622 const std::string &Name = Processor->getValueAsString("Name");
623 const std::string &ProcModelName =
624 SchedModels.getProcModel(Processor).ModelName;
626 // Emit as { "cpu", procinit },
628 << "\"" << Name << "\", "
629 << "(void *)&" << ProcModelName;
633 // Depending on ''if more in the list'' emit comma
634 if (++i < N) OS << ",";
639 // End processor table
644 // EmitSchedModel - Emits all scheduling model tables, folding common patterns.
646 void SubtargetEmitter::EmitSchedModel(raw_ostream &OS) {
647 if (SchedModels.hasItineraryClasses()) {
648 std::vector<std::vector<InstrItinerary> > ProcItinLists;
649 // Emit the stage data
650 EmitStageAndOperandCycleData(OS, ProcItinLists);
651 EmitItineraries(OS, ProcItinLists);
653 // Emit the processor machine model
654 EmitProcessorModels(OS);
655 // Emit the processor lookup data
656 EmitProcessorLookup(OS);
660 // ParseFeaturesFunction - Produces a subtarget specific function for parsing
661 // the subtarget features string.
663 void SubtargetEmitter::ParseFeaturesFunction(raw_ostream &OS,
664 unsigned NumFeatures,
666 std::vector<Record*> Features =
667 Records.getAllDerivedDefinitions("SubtargetFeature");
668 std::sort(Features.begin(), Features.end(), LessRecord());
670 OS << "// ParseSubtargetFeatures - Parses features string setting specified\n"
671 << "// subtarget options.\n"
674 OS << "Subtarget::ParseSubtargetFeatures(StringRef CPU, StringRef FS) {\n"
675 << " DEBUG(dbgs() << \"\\nFeatures:\" << FS);\n"
676 << " DEBUG(dbgs() << \"\\nCPU:\" << CPU << \"\\n\\n\");\n";
678 if (Features.empty()) {
683 OS << " uint64_t Bits = ReInitMCSubtargetInfo(CPU, FS);\n";
685 for (unsigned i = 0; i < Features.size(); i++) {
687 Record *R = Features[i];
688 const std::string &Instance = R->getName();
689 const std::string &Value = R->getValueAsString("Value");
690 const std::string &Attribute = R->getValueAsString("Attribute");
692 if (Value=="true" || Value=="false")
693 OS << " if ((Bits & " << Target << "::"
694 << Instance << ") != 0) "
695 << Attribute << " = " << Value << ";\n";
697 OS << " if ((Bits & " << Target << "::"
698 << Instance << ") != 0 && "
699 << Attribute << " < " << Value << ") "
700 << Attribute << " = " << Value << ";\n";
707 // SubtargetEmitter::run - Main subtarget enumeration emitter.
709 void SubtargetEmitter::run(raw_ostream &OS) {
710 emitSourceFileHeader("Subtarget Enumeration Source Fragment", OS);
712 OS << "\n#ifdef GET_SUBTARGETINFO_ENUM\n";
713 OS << "#undef GET_SUBTARGETINFO_ENUM\n";
715 OS << "namespace llvm {\n";
716 Enumeration(OS, "SubtargetFeature", true);
717 OS << "} // End llvm namespace \n";
718 OS << "#endif // GET_SUBTARGETINFO_ENUM\n\n";
720 OS << "\n#ifdef GET_SUBTARGETINFO_MC_DESC\n";
721 OS << "#undef GET_SUBTARGETINFO_MC_DESC\n";
723 OS << "namespace llvm {\n";
725 OS << "namespace {\n";
727 unsigned NumFeatures = FeatureKeyValues(OS);
729 unsigned NumProcs = CPUKeyValues(OS);
737 // MCInstrInfo initialization routine.
738 OS << "static inline void Init" << Target
739 << "MCSubtargetInfo(MCSubtargetInfo *II, "
740 << "StringRef TT, StringRef CPU, StringRef FS) {\n";
741 OS << " II->InitMCSubtargetInfo(TT, CPU, FS, ";
743 OS << Target << "FeatureKV, ";
747 OS << Target << "SubTypeKV, ";
750 if (SchedModels.hasItineraryClasses()) {
751 OS << Target << "ProcSchedKV, "
752 << Target << "Stages, "
753 << Target << "OperandCycles, "
754 << Target << "ForwardingPaths, ";
756 OS << "0, 0, 0, 0, ";
757 OS << NumFeatures << ", " << NumProcs << ");\n}\n\n";
759 OS << "} // End llvm namespace \n";
761 OS << "#endif // GET_SUBTARGETINFO_MC_DESC\n\n";
763 OS << "\n#ifdef GET_SUBTARGETINFO_TARGET_DESC\n";
764 OS << "#undef GET_SUBTARGETINFO_TARGET_DESC\n";
766 OS << "#include \"llvm/Support/Debug.h\"\n";
767 OS << "#include \"llvm/Support/raw_ostream.h\"\n";
768 ParseFeaturesFunction(OS, NumFeatures, NumProcs);
770 OS << "#endif // GET_SUBTARGETINFO_TARGET_DESC\n\n";
772 // Create a TargetSubtargetInfo subclass to hide the MC layer initialization.
773 OS << "\n#ifdef GET_SUBTARGETINFO_HEADER\n";
774 OS << "#undef GET_SUBTARGETINFO_HEADER\n";
776 std::string ClassName = Target + "GenSubtargetInfo";
777 OS << "namespace llvm {\n";
778 OS << "class DFAPacketizer;\n";
779 OS << "struct " << ClassName << " : public TargetSubtargetInfo {\n"
780 << " explicit " << ClassName << "(StringRef TT, StringRef CPU, "
781 << "StringRef FS);\n"
783 << " DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID)"
786 OS << "} // End llvm namespace \n";
788 OS << "#endif // GET_SUBTARGETINFO_HEADER\n\n";
790 OS << "\n#ifdef GET_SUBTARGETINFO_CTOR\n";
791 OS << "#undef GET_SUBTARGETINFO_CTOR\n";
793 OS << "namespace llvm {\n";
794 OS << "extern const llvm::SubtargetFeatureKV " << Target << "FeatureKV[];\n";
795 OS << "extern const llvm::SubtargetFeatureKV " << Target << "SubTypeKV[];\n";
796 if (SchedModels.hasItineraryClasses()) {
797 OS << "extern const llvm::SubtargetInfoKV " << Target << "ProcSchedKV[];\n";
798 OS << "extern const llvm::InstrStage " << Target << "Stages[];\n";
799 OS << "extern const unsigned " << Target << "OperandCycles[];\n";
800 OS << "extern const unsigned " << Target << "ForwardingPaths[];\n";
803 OS << ClassName << "::" << ClassName << "(StringRef TT, StringRef CPU, "
805 << " : TargetSubtargetInfo() {\n"
806 << " InitMCSubtargetInfo(TT, CPU, FS, ";
808 OS << Target << "FeatureKV, ";
812 OS << Target << "SubTypeKV, ";
815 if (SchedModels.hasItineraryClasses()) {
816 OS << Target << "ProcSchedKV, "
817 << Target << "Stages, "
818 << Target << "OperandCycles, "
819 << Target << "ForwardingPaths, ";
821 OS << "0, 0, 0, 0, ";
822 OS << NumFeatures << ", " << NumProcs << ");\n}\n\n";
823 OS << "} // End llvm namespace \n";
825 OS << "#endif // GET_SUBTARGETINFO_CTOR\n\n";
830 void EmitSubtarget(RecordKeeper &RK, raw_ostream &OS) {
831 CodeGenTarget CGTarget(RK);
832 SubtargetEmitter(RK, CGTarget).run(OS);
835 } // End llvm namespace