1 //===- RegisterInfoEmitter.cpp - Generate a Register File Desc. -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend is responsible for emitting a description of a target
11 // register file for a code generator. It uses instances of the Register,
12 // RegisterAliases, and RegisterClass classes to gather this information.
14 //===----------------------------------------------------------------------===//
16 #include "RegisterInfoEmitter.h"
17 #include "CodeGenTarget.h"
18 #include "CodeGenRegisters.h"
20 #include "llvm/ADT/StringExtras.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/Support/Format.h"
27 // runEnums - Print out enum values for all of the registers.
29 RegisterInfoEmitter::runEnums(raw_ostream &OS,
30 CodeGenTarget &Target, CodeGenRegBank &Bank) {
31 const std::vector<CodeGenRegister*> &Registers = Bank.getRegisters();
33 std::string Namespace = Registers[0]->TheDef->getValueAsString("Namespace");
35 EmitSourceFileHeader("Target Register Enum Values", OS);
37 OS << "\n#ifdef GET_REGINFO_ENUM\n";
38 OS << "#undef GET_REGINFO_ENUM\n";
40 OS << "namespace llvm {\n\n";
42 if (!Namespace.empty())
43 OS << "namespace " << Namespace << " {\n";
44 OS << "enum {\n NoRegister,\n";
46 for (unsigned i = 0, e = Registers.size(); i != e; ++i)
47 OS << " " << Registers[i]->getName() << " = " <<
48 Registers[i]->EnumValue << ",\n";
49 assert(Registers.size() == Registers[Registers.size()-1]->EnumValue &&
50 "Register enum value mismatch!");
51 OS << " NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n";
53 if (!Namespace.empty())
56 const std::vector<CodeGenRegisterClass> &RegisterClasses =
57 Target.getRegisterClasses();
58 if (!RegisterClasses.empty()) {
59 OS << "\n// Register classes\n";
60 if (!Namespace.empty())
61 OS << "namespace " << Namespace << " {\n";
63 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
65 OS << " " << RegisterClasses[i].getName() << "RegClassID";
69 if (!Namespace.empty())
73 const std::vector<Record*> RegAltNameIndices = Target.getRegAltNameIndices();
74 // If the only definition is the default NoRegAltName, we don't need to
76 if (RegAltNameIndices.size() > 1) {
77 OS << "\n// Register alternate name indices\n";
78 if (!Namespace.empty())
79 OS << "namespace " << Namespace << " {\n";
81 for (unsigned i = 0, e = RegAltNameIndices.size(); i != e; ++i)
82 OS << " " << RegAltNameIndices[i]->getName() << ",\t// " << i << "\n";
83 OS << " NUM_TARGET_REG_ALT_NAMES = " << RegAltNameIndices.size() << "\n";
85 if (!Namespace.empty())
90 OS << "} // End llvm namespace \n";
91 OS << "#endif // GET_REGINFO_ENUM\n\n";
95 // runMCDesc - Print out MC register descriptions.
98 RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target,
99 CodeGenRegBank &RegBank) {
100 EmitSourceFileHeader("MC Register Information", OS);
102 OS << "\n#ifdef GET_REGINFO_MC_DESC\n";
103 OS << "#undef GET_REGINFO_MC_DESC\n";
105 std::map<const CodeGenRegister*, CodeGenRegister::Set> Overlaps;
106 RegBank.computeOverlaps(Overlaps);
108 OS << "namespace llvm {\n\n";
110 const std::string &TargetName = Target.getName();
111 std::string ClassName = TargetName + "GenMCRegisterInfo";
112 OS << "struct " << ClassName << " : public MCRegisterInfo {\n"
113 << " explicit " << ClassName << "(const MCRegisterDesc *D);\n";
116 OS << "\nnamespace {\n";
118 const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters();
120 // Emit an overlap list for all registers.
121 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
122 const CodeGenRegister *Reg = Regs[i];
123 const CodeGenRegister::Set &O = Overlaps[Reg];
124 // Move Reg to the front so TRI::getAliasSet can share the list.
125 OS << " const unsigned " << Reg->getName() << "_Overlaps[] = { "
126 << getQualifiedName(Reg->TheDef) << ", ";
127 for (CodeGenRegister::Set::const_iterator I = O.begin(), E = O.end();
130 OS << getQualifiedName((*I)->TheDef) << ", ";
134 // Emit the empty sub-registers list
135 OS << " const unsigned Empty_SubRegsSet[] = { 0 };\n";
136 // Loop over all of the registers which have sub-registers, emitting the
137 // sub-registers list to memory.
138 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
139 const CodeGenRegister &Reg = *Regs[i];
140 if (Reg.getSubRegs().empty())
142 // getSubRegs() orders by SubRegIndex. We want a topological order.
143 SetVector<CodeGenRegister*> SR;
144 Reg.addSubRegsPreOrder(SR);
145 OS << " const unsigned " << Reg.getName() << "_SubRegsSet[] = { ";
146 for (unsigned j = 0, je = SR.size(); j != je; ++j)
147 OS << getQualifiedName(SR[j]->TheDef) << ", ";
151 // Emit the empty super-registers list
152 OS << " const unsigned Empty_SuperRegsSet[] = { 0 };\n";
153 // Loop over all of the registers which have super-registers, emitting the
154 // super-registers list to memory.
155 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
156 const CodeGenRegister &Reg = *Regs[i];
157 const CodeGenRegister::SuperRegList &SR = Reg.getSuperRegs();
160 OS << " const unsigned " << Reg.getName() << "_SuperRegsSet[] = { ";
161 for (unsigned j = 0, je = SR.size(); j != je; ++j)
162 OS << getQualifiedName(SR[j]->TheDef) << ", ";
166 OS << "\n const MCRegisterDesc " << TargetName
167 << "RegDesc[] = { // Descriptors\n";
168 OS << " { \"NOREG\",\t0,\t0,\t0 },\n";
170 // Now that register alias and sub-registers sets have been emitted, emit the
171 // register descriptors now.
172 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
173 const CodeGenRegister &Reg = *Regs[i];
175 OS << Reg.getName() << "\",\t" << Reg.getName() << "_Overlaps,\t";
176 if (!Reg.getSubRegs().empty())
177 OS << Reg.getName() << "_SubRegsSet,\t";
179 OS << "Empty_SubRegsSet,\t";
180 if (!Reg.getSuperRegs().empty())
181 OS << Reg.getName() << "_SuperRegsSet";
183 OS << "Empty_SuperRegsSet";
186 OS << " };\n"; // End of register descriptors...
188 OS << "}\n\n"; // End of anonymous namespace...
190 // MCRegisterInfo initialization routine.
191 OS << "static inline void Init" << TargetName
192 << "MCRegisterInfo(MCRegisterInfo *RI) {\n";
193 OS << " RI->InitMCRegisterInfo(" << TargetName << "RegDesc, "
194 << Regs.size()+1 << ");\n}\n\n";
196 OS << "} // End llvm namespace \n";
197 OS << "#endif // GET_REGINFO_MC_DESC\n\n";
201 RegisterInfoEmitter::runTargetHeader(raw_ostream &OS, CodeGenTarget &Target,
202 CodeGenRegBank &RegBank) {
203 EmitSourceFileHeader("Register Information Header Fragment", OS);
205 OS << "\n#ifdef GET_REGINFO_HEADER\n";
206 OS << "#undef GET_REGINFO_HEADER\n";
208 const std::string &TargetName = Target.getName();
209 std::string ClassName = TargetName + "GenRegisterInfo";
211 OS << "#include \"llvm/Target/TargetRegisterInfo.h\"\n";
212 OS << "#include <string>\n\n";
214 OS << "namespace llvm {\n\n";
216 OS << "struct " << ClassName << " : public TargetRegisterInfo {\n"
217 << " explicit " << ClassName << "();\n"
218 << " virtual int getDwarfRegNumFull(unsigned RegNum, "
219 << "unsigned Flavour) const;\n"
220 << " virtual int getLLVMRegNumFull(unsigned DwarfRegNum, "
221 << "unsigned Flavour) const;\n"
222 << " virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0;\n"
223 << " virtual bool needsStackRealignment(const MachineFunction &) const\n"
224 << " { return false; }\n"
225 << " unsigned getSubReg(unsigned RegNo, unsigned Index) const;\n"
226 << " unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const;\n"
227 << " unsigned composeSubRegIndices(unsigned, unsigned) const;\n"
230 const std::vector<Record*> &SubRegIndices = RegBank.getSubRegIndices();
231 if (!SubRegIndices.empty()) {
232 OS << "\n// Subregister indices\n";
233 std::string Namespace = SubRegIndices[0]->getValueAsString("Namespace");
234 if (!Namespace.empty())
235 OS << "namespace " << Namespace << " {\n";
236 OS << "enum {\n NoSubRegister,\n";
237 for (unsigned i = 0, e = RegBank.getNumNamedIndices(); i != e; ++i)
238 OS << " " << SubRegIndices[i]->getName() << ",\t// " << i+1 << "\n";
239 OS << " NUM_TARGET_NAMED_SUBREGS = " << SubRegIndices.size()+1 << "\n";
241 if (!Namespace.empty())
245 const std::vector<CodeGenRegisterClass> &RegisterClasses =
246 Target.getRegisterClasses();
248 if (!RegisterClasses.empty()) {
249 OS << "namespace " << RegisterClasses[0].Namespace
250 << " { // Register classes\n";
252 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
253 const CodeGenRegisterClass &RC = RegisterClasses[i];
254 const std::string &Name = RC.getName();
256 // Output the register class definition.
257 OS << " struct " << Name << "Class : public TargetRegisterClass {\n"
258 << " " << Name << "Class();\n";
259 if (!RC.AltOrderSelect.empty())
260 OS << " ArrayRef<unsigned> "
261 "getRawAllocationOrder(const MachineFunction&) const;\n";
264 // Output the extern for the instance.
265 OS << " extern " << Name << "Class\t" << Name << "RegClass;\n";
266 // Output the extern for the pointer to the instance (should remove).
267 OS << " static TargetRegisterClass * const "<< Name <<"RegisterClass = &"
268 << Name << "RegClass;\n";
270 OS << "} // end of namespace " << TargetName << "\n\n";
272 OS << "} // End llvm namespace \n";
273 OS << "#endif // GET_REGINFO_HEADER\n\n";
277 // runTargetDesc - Output the target register and register file descriptions.
280 RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
281 CodeGenRegBank &RegBank){
282 EmitSourceFileHeader("Target Register and Register Classes Information", OS);
284 OS << "\n#ifdef GET_REGINFO_TARGET_DESC\n";
285 OS << "#undef GET_REGINFO_TARGET_DESC\n";
287 OS << "namespace llvm {\n\n";
289 // Start out by emitting each of the register classes.
290 const std::vector<CodeGenRegisterClass> &RegisterClasses =
291 Target.getRegisterClasses();
293 // Collect all registers belonging to any allocatable class.
294 std::set<Record*> AllocatableRegs;
296 // Loop over all of the register classes... emitting each one.
297 OS << "namespace { // Register classes...\n";
299 // Emit the register enum value arrays for each RegisterClass
300 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
301 const CodeGenRegisterClass &RC = RegisterClasses[rc];
302 ArrayRef<Record*> Order = RC.getOrder();
304 // Collect allocatable registers.
306 AllocatableRegs.insert(Order.begin(), Order.end());
308 // Give the register class a legal C name if it's anonymous.
309 std::string Name = RC.getName();
311 // Emit the register list now.
312 OS << " // " << Name << " Register Class...\n"
313 << " static const unsigned " << Name
315 for (unsigned i = 0, e = Order.size(); i != e; ++i) {
316 Record *Reg = Order[i];
317 OS << getQualifiedName(Reg) << ", ";
322 // Emit the ValueType arrays for each RegisterClass
323 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
324 const CodeGenRegisterClass &RC = RegisterClasses[rc];
326 // Give the register class a legal C name if it's anonymous.
327 std::string Name = RC.getName() + "VTs";
329 // Emit the register list now.
331 << " Register Class Value Types...\n"
332 << " static const EVT " << Name
334 for (unsigned i = 0, e = RC.VTs.size(); i != e; ++i)
335 OS << getEnumName(RC.VTs[i]) << ", ";
336 OS << "MVT::Other\n };\n\n";
338 OS << "} // end anonymous namespace\n\n";
340 // Now that all of the structs have been emitted, emit the instances.
341 if (!RegisterClasses.empty()) {
342 OS << "namespace " << RegisterClasses[0].Namespace
343 << " { // Register class instances\n";
344 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i)
345 OS << " " << RegisterClasses[i].getName() << "Class\t"
346 << RegisterClasses[i].getName() << "RegClass;\n";
348 std::map<unsigned, std::set<unsigned> > SuperClassMap;
349 std::map<unsigned, std::set<unsigned> > SuperRegClassMap;
352 unsigned NumSubRegIndices = RegBank.getSubRegIndices().size();
354 if (NumSubRegIndices) {
355 // Emit the sub-register classes for each RegisterClass
356 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
357 const CodeGenRegisterClass &RC = RegisterClasses[rc];
358 std::vector<Record*> SRC(NumSubRegIndices);
359 for (DenseMap<Record*,Record*>::const_iterator
360 i = RC.SubRegClasses.begin(),
361 e = RC.SubRegClasses.end(); i != e; ++i) {
363 unsigned idx = RegBank.getSubRegIndexNo(i->first);
364 SRC.at(idx-1) = i->second;
366 // Find the register class number of i->second for SuperRegClassMap.
367 for (unsigned rc2 = 0, e2 = RegisterClasses.size(); rc2 != e2; ++rc2) {
368 const CodeGenRegisterClass &RC2 = RegisterClasses[rc2];
369 if (RC2.TheDef == i->second) {
370 SuperRegClassMap[rc2].insert(rc);
376 // Give the register class a legal C name if it's anonymous.
377 std::string Name = RC.TheDef->getName();
380 << " Sub-register Classes...\n"
381 << " static const TargetRegisterClass* const "
382 << Name << "SubRegClasses[] = {\n ";
384 for (unsigned idx = 0; idx != NumSubRegIndices; ++idx) {
388 OS << "&" << getQualifiedName(SRC[idx]) << "RegClass";
395 // Emit the super-register classes for each RegisterClass
396 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
397 const CodeGenRegisterClass &RC = RegisterClasses[rc];
399 // Give the register class a legal C name if it's anonymous.
400 std::string Name = RC.TheDef->getName();
403 << " Super-register Classes...\n"
404 << " static const TargetRegisterClass* const "
405 << Name << "SuperRegClasses[] = {\n ";
408 std::map<unsigned, std::set<unsigned> >::iterator I =
409 SuperRegClassMap.find(rc);
410 if (I != SuperRegClassMap.end()) {
411 for (std::set<unsigned>::iterator II = I->second.begin(),
412 EE = I->second.end(); II != EE; ++II) {
413 const CodeGenRegisterClass &RC2 = RegisterClasses[*II];
416 OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
421 OS << (!Empty ? ", " : "") << "NULL";
425 // No subregindices in this target
426 OS << " static const TargetRegisterClass* const "
427 << "NullRegClasses[] = { NULL };\n\n";
430 // Emit the sub-classes array for each RegisterClass
431 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
432 const CodeGenRegisterClass &RC = RegisterClasses[rc];
434 // Give the register class a legal C name if it's anonymous.
435 std::string Name = RC.TheDef->getName();
438 << " Register Class sub-classes...\n"
439 << " static const TargetRegisterClass* const "
440 << Name << "Subclasses[] = {\n ";
443 for (unsigned rc2 = 0, e2 = RegisterClasses.size(); rc2 != e2; ++rc2) {
444 const CodeGenRegisterClass &RC2 = RegisterClasses[rc2];
446 // Sub-classes are used to determine if a virtual register can be used
447 // as an instruction operand, or if it must be copied first.
448 if (rc == rc2 || !RC.hasSubClass(&RC2)) continue;
450 if (!Empty) OS << ", ";
451 OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
454 std::map<unsigned, std::set<unsigned> >::iterator SCMI =
455 SuperClassMap.find(rc2);
456 if (SCMI == SuperClassMap.end()) {
457 SuperClassMap.insert(std::make_pair(rc2, std::set<unsigned>()));
458 SCMI = SuperClassMap.find(rc2);
460 SCMI->second.insert(rc);
463 OS << (!Empty ? ", " : "") << "NULL";
467 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
468 const CodeGenRegisterClass &RC = RegisterClasses[rc];
470 // Give the register class a legal C name if it's anonymous.
471 std::string Name = RC.TheDef->getName();
474 << " Register Class super-classes...\n"
475 << " static const TargetRegisterClass* const "
476 << Name << "Superclasses[] = {\n ";
479 std::map<unsigned, std::set<unsigned> >::iterator I =
480 SuperClassMap.find(rc);
481 if (I != SuperClassMap.end()) {
482 for (std::set<unsigned>::iterator II = I->second.begin(),
483 EE = I->second.end(); II != EE; ++II) {
484 const CodeGenRegisterClass &RC2 = RegisterClasses[*II];
485 if (!Empty) OS << ", ";
486 OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
491 OS << (!Empty ? ", " : "") << "NULL";
496 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
497 const CodeGenRegisterClass &RC = RegisterClasses[i];
498 OS << RC.getName() << "Class::" << RC.getName()
499 << "Class() : TargetRegisterClass("
500 << RC.getName() + "RegClassID" << ", "
501 << '\"' << RC.getName() << "\", "
502 << RC.getName() + "VTs" << ", "
503 << RC.getName() + "Subclasses" << ", "
504 << RC.getName() + "Superclasses" << ", "
505 << (NumSubRegIndices ? RC.getName() + "Sub" : std::string("Null"))
507 << (NumSubRegIndices ? RC.getName() + "Super" : std::string("Null"))
509 << RC.SpillSize/8 << ", "
510 << RC.SpillAlignment/8 << ", "
511 << RC.CopyCost << ", "
512 << RC.Allocatable << ", "
513 << RC.getName() << ", " << RC.getName() << " + "
514 << RC.getOrder().size()
516 if (!RC.AltOrderSelect.empty()) {
517 OS << "\nstatic inline unsigned " << RC.getName()
518 << "AltOrderSelect(const MachineFunction &MF) {"
519 << RC.AltOrderSelect << "}\n\nArrayRef<unsigned> "
520 << RC.getName() << "Class::"
521 << "getRawAllocationOrder(const MachineFunction &MF) const {\n";
522 for (unsigned oi = 1 , oe = RC.getNumOrders(); oi != oe; ++oi) {
523 ArrayRef<Record*> Elems = RC.getOrder(oi);
524 OS << " static const unsigned AltOrder" << oi << "[] = {";
525 for (unsigned elem = 0; elem != Elems.size(); ++elem)
526 OS << (elem ? ", " : " ") << getQualifiedName(Elems[elem]);
529 OS << " static const ArrayRef<unsigned> Order[] = {\n"
530 << " ArrayRef<unsigned>(" << RC.getName();
531 for (unsigned oi = 1, oe = RC.getNumOrders(); oi != oe; ++oi)
532 OS << "),\n ArrayRef<unsigned>(AltOrder" << oi;
533 OS << ")\n };\n const unsigned Select = " << RC.getName()
534 << "AltOrderSelect(MF);\n assert(Select < " << RC.getNumOrders()
535 << ");\n return Order[Select];\n}\n";
542 OS << "\nnamespace {\n";
543 OS << " const TargetRegisterClass* const RegisterClasses[] = {\n";
544 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i)
545 OS << " &" << getQualifiedName(RegisterClasses[i].TheDef)
549 // Emit extra information about registers.
550 const std::string &TargetName = Target.getName();
551 OS << "\n static const TargetRegisterInfoDesc "
552 << TargetName << "RegInfoDesc[] = "
553 << "{ // Extra Descriptors\n";
554 OS << " { 0, 0 },\n";
556 const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters();
557 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
558 const CodeGenRegister &Reg = *Regs[i];
560 OS << Reg.CostPerUse << ", "
561 << int(AllocatableRegs.count(Reg.TheDef)) << " },\n";
563 OS << " };\n"; // End of register descriptors...
566 // Calculate the mapping of subregister+index pairs to physical registers.
567 // This will also create further anonymous indexes.
568 unsigned NamedIndices = RegBank.getNumNamedIndices();
570 // Emit SubRegIndex names, skipping 0
571 const std::vector<Record*> &SubRegIndices = RegBank.getSubRegIndices();
572 OS << "\n const char *const SubRegIndexTable[] = { \"";
573 for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) {
574 OS << SubRegIndices[i]->getName();
580 // Emit names of the anonymus subreg indexes.
581 if (SubRegIndices.size() > NamedIndices) {
583 for (unsigned i = NamedIndices, e = SubRegIndices.size(); i != e; ++i) {
584 OS << "\n " << SubRegIndices[i]->getName() << " = " << i+1;
590 OS << "}\n\n"; // End of anonymous namespace...
592 std::string ClassName = Target.getName() + "GenRegisterInfo";
594 // Emit the subregister + index mapping function based on the information
596 OS << "unsigned " << ClassName
597 << "::getSubReg(unsigned RegNo, unsigned Index) const {\n"
598 << " switch (RegNo) {\n"
599 << " default:\n return 0;\n";
600 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
601 const CodeGenRegister::SubRegMap &SRM = Regs[i]->getSubRegs();
604 OS << " case " << getQualifiedName(Regs[i]->TheDef) << ":\n";
605 OS << " switch (Index) {\n";
606 OS << " default: return 0;\n";
607 for (CodeGenRegister::SubRegMap::const_iterator ii = SRM.begin(),
608 ie = SRM.end(); ii != ie; ++ii)
609 OS << " case " << getQualifiedName(ii->first)
610 << ": return " << getQualifiedName(ii->second->TheDef) << ";\n";
611 OS << " };\n" << " break;\n";
614 OS << " return 0;\n";
617 OS << "unsigned " << ClassName
618 << "::getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const {\n"
619 << " switch (RegNo) {\n"
620 << " default:\n return 0;\n";
621 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
622 const CodeGenRegister::SubRegMap &SRM = Regs[i]->getSubRegs();
625 OS << " case " << getQualifiedName(Regs[i]->TheDef) << ":\n";
626 for (CodeGenRegister::SubRegMap::const_iterator ii = SRM.begin(),
627 ie = SRM.end(); ii != ie; ++ii)
628 OS << " if (SubRegNo == " << getQualifiedName(ii->second->TheDef)
629 << ") return " << getQualifiedName(ii->first) << ";\n";
630 OS << " return 0;\n";
633 OS << " return 0;\n";
636 // Emit composeSubRegIndices
637 OS << "unsigned " << ClassName
638 << "::composeSubRegIndices(unsigned IdxA, unsigned IdxB) const {\n"
639 << " switch (IdxA) {\n"
640 << " default:\n return IdxB;\n";
641 for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) {
643 for (unsigned j = 0; j != e; ++j) {
644 if (Record *Comp = RegBank.getCompositeSubRegIndex(SubRegIndices[i],
647 OS << " case " << getQualifiedName(SubRegIndices[i])
648 << ": switch(IdxB) {\n default: return IdxB;\n";
651 OS << " case " << getQualifiedName(SubRegIndices[j])
652 << ": return " << getQualifiedName(Comp) << ";\n";
660 // Emit the constructor of the class...
661 OS << ClassName << "::" << ClassName
663 << " : TargetRegisterInfo(" << TargetName << "RegInfoDesc"
664 << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n"
665 << " SubRegIndexTable) {\n"
666 << " InitMCRegisterInfo(" << TargetName << "RegDesc, "
667 << Regs.size()+1 << ");\n"
670 // Collect all information about dwarf register numbers
671 typedef std::map<Record*, std::vector<int64_t>, LessRecord> DwarfRegNumsMapTy;
672 DwarfRegNumsMapTy DwarfRegNums;
674 // First, just pull all provided information to the map
675 unsigned maxLength = 0;
676 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
677 Record *Reg = Regs[i]->TheDef;
678 std::vector<int64_t> RegNums = Reg->getValueAsListOfInts("DwarfNumbers");
679 maxLength = std::max((size_t)maxLength, RegNums.size());
680 if (DwarfRegNums.count(Reg))
681 errs() << "Warning: DWARF numbers for register " << getQualifiedName(Reg)
682 << "specified multiple times\n";
683 DwarfRegNums[Reg] = RegNums;
686 // Now we know maximal length of number list. Append -1's, where needed
687 for (DwarfRegNumsMapTy::iterator
688 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I)
689 for (unsigned i = I->second.size(), e = maxLength; i != e; ++i)
690 I->second.push_back(-1);
692 // Emit reverse information about the dwarf register numbers.
693 OS << "int " << ClassName << "::getLLVMRegNumFull(unsigned DwarfRegNum, "
694 << "unsigned Flavour) const {\n"
695 << " switch (Flavour) {\n"
697 << " assert(0 && \"Unknown DWARF flavour\");\n"
700 for (unsigned i = 0, e = maxLength; i != e; ++i) {
701 OS << " case " << i << ":\n"
702 << " switch (DwarfRegNum) {\n"
704 << " assert(0 && \"Invalid DwarfRegNum\");\n"
707 for (DwarfRegNumsMapTy::iterator
708 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
709 int DwarfRegNo = I->second[i];
711 OS << " case " << DwarfRegNo << ":\n"
712 << " return " << getQualifiedName(I->first) << ";\n";
719 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
720 Record *Reg = Regs[i]->TheDef;
721 const RecordVal *V = Reg->getValue("DwarfAlias");
722 if (!V || !V->getValue())
725 DefInit *DI = dynamic_cast<DefInit*>(V->getValue());
726 Record *Alias = DI->getDef();
727 DwarfRegNums[Reg] = DwarfRegNums[Alias];
730 // Emit information about the dwarf register numbers.
731 OS << "int " << ClassName << "::getDwarfRegNumFull(unsigned RegNum, "
732 << "unsigned Flavour) const {\n"
733 << " switch (Flavour) {\n"
735 << " assert(0 && \"Unknown DWARF flavour\");\n"
738 for (unsigned i = 0, e = maxLength; i != e; ++i) {
739 OS << " case " << i << ":\n"
740 << " switch (RegNum) {\n"
742 << " assert(0 && \"Invalid RegNum\");\n"
745 // Sort by name to get a stable order.
748 for (DwarfRegNumsMapTy::iterator
749 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
750 int RegNo = I->second[i];
751 OS << " case " << getQualifiedName(I->first) << ":\n"
752 << " return " << RegNo << ";\n";
759 OS << "} // End llvm namespace \n";
760 OS << "#endif // GET_REGINFO_TARGET_DESC\n\n";
763 void RegisterInfoEmitter::run(raw_ostream &OS) {
764 CodeGenTarget Target(Records);
765 CodeGenRegBank &RegBank = Target.getRegBank();
766 RegBank.computeDerivedInfo();
768 runEnums(OS, Target, RegBank);
769 runMCDesc(OS, Target, RegBank);
770 runTargetHeader(OS, Target, RegBank);
771 runTargetDesc(OS, Target, RegBank);