1 //===- RegisterInfoEmitter.cpp - Generate a Register File Desc. -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend is responsible for emitting a description of a target
11 // register file for a code generator. It uses instances of the Register,
12 // RegisterAliases, and RegisterClass classes to gather this information.
14 //===----------------------------------------------------------------------===//
16 #include "RegisterInfoEmitter.h"
17 #include "CodeGenTarget.h"
18 #include "CodeGenRegisters.h"
20 #include "llvm/ADT/StringExtras.h"
21 #include "llvm/ADT/STLExtras.h"
26 // runEnums - Print out enum values for all of the registers.
27 void RegisterInfoEmitter::runEnums(raw_ostream &OS) {
29 const std::vector<CodeGenRegister> &Registers = Target.getRegisters();
31 std::string Namespace = Registers[0].TheDef->getValueAsString("Namespace");
33 EmitSourceFileHeader("Target Register Enum Values", OS);
34 OS << "namespace llvm {\n\n";
36 if (!Namespace.empty())
37 OS << "namespace " << Namespace << " {\n";
38 OS << "enum {\n NoRegister,\n";
40 for (unsigned i = 0, e = Registers.size(); i != e; ++i)
41 OS << " " << Registers[i].getName() << ", \t// " << i+1 << "\n";
42 OS << " NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n";
44 if (!Namespace.empty())
47 const std::vector<Record*> SubRegIndices =
48 Records.getAllDerivedDefinitions("SubRegIndex");
49 if (!SubRegIndices.empty()) {
50 OS << "\n// Subregister indices\n";
51 Namespace = SubRegIndices[0]->getValueAsString("Namespace");
52 if (!Namespace.empty())
53 OS << "namespace " << Namespace << " {\n";
54 OS << "enum {\n NoSubRegister,\n";
55 for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i)
56 OS << " " << SubRegIndices[i]->getName() << " = "
57 << SubRegIndices[i]->getValueAsInt("NumberHack") << ",\n";
58 OS << " NUM_TARGET_SUBREGS = " << SubRegIndices.size()+1 << "\n";
60 if (!Namespace.empty())
63 OS << "} // End llvm namespace \n";
66 void RegisterInfoEmitter::runHeader(raw_ostream &OS) {
67 EmitSourceFileHeader("Register Information Header Fragment", OS);
69 const std::string &TargetName = Target.getName();
70 std::string ClassName = TargetName + "GenRegisterInfo";
72 OS << "#include \"llvm/Target/TargetRegisterInfo.h\"\n";
73 OS << "#include <string>\n\n";
75 OS << "namespace llvm {\n\n";
77 OS << "struct " << ClassName << " : public TargetRegisterInfo {\n"
78 << " explicit " << ClassName
79 << "(int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);\n"
80 << " virtual int getDwarfRegNumFull(unsigned RegNum, "
81 << "unsigned Flavour) const;\n"
82 << " virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0;\n"
83 << " virtual bool needsStackRealignment(const MachineFunction &) const\n"
84 << " { return false; }\n"
85 << " unsigned getSubReg(unsigned RegNo, unsigned Index) const;\n"
86 << " unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const;\n"
89 const std::vector<CodeGenRegisterClass> &RegisterClasses =
90 Target.getRegisterClasses();
92 if (!RegisterClasses.empty()) {
93 OS << "namespace " << RegisterClasses[0].Namespace
94 << " { // Register classes\n";
97 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
99 OS << " " << RegisterClasses[i].getName() << "RegClassID";
100 OS << " = " << (i+1);
104 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
105 const std::string &Name = RegisterClasses[i].getName();
107 // Output the register class definition.
108 OS << " struct " << Name << "Class : public TargetRegisterClass {\n"
109 << " " << Name << "Class();\n"
110 << RegisterClasses[i].MethodProtos << " };\n";
112 // Output the extern for the instance.
113 OS << " extern " << Name << "Class\t" << Name << "RegClass;\n";
114 // Output the extern for the pointer to the instance (should remove).
115 OS << " static TargetRegisterClass * const "<< Name <<"RegisterClass = &"
116 << Name << "RegClass;\n";
118 OS << "} // end of namespace " << TargetName << "\n\n";
120 OS << "} // End llvm namespace \n";
123 bool isSubRegisterClass(const CodeGenRegisterClass &RC,
124 std::set<Record*> &RegSet) {
125 for (unsigned i = 0, e = RC.Elements.size(); i != e; ++i) {
126 Record *Reg = RC.Elements[i];
127 if (!RegSet.count(Reg))
133 static void addSuperReg(Record *R, Record *S,
134 std::map<Record*, std::set<Record*>, LessRecord> &SubRegs,
135 std::map<Record*, std::set<Record*>, LessRecord> &SuperRegs,
136 std::map<Record*, std::set<Record*>, LessRecord> &Aliases) {
138 errs() << "Error: recursive sub-register relationship between"
139 << " register " << getQualifiedName(R)
140 << " and its sub-registers?\n";
143 if (!SuperRegs[R].insert(S).second)
145 SubRegs[S].insert(R);
146 Aliases[R].insert(S);
147 Aliases[S].insert(R);
148 if (SuperRegs.count(S))
149 for (std::set<Record*>::iterator I = SuperRegs[S].begin(),
150 E = SuperRegs[S].end(); I != E; ++I)
151 addSuperReg(R, *I, SubRegs, SuperRegs, Aliases);
154 static void addSubSuperReg(Record *R, Record *S,
155 std::map<Record*, std::set<Record*>, LessRecord> &SubRegs,
156 std::map<Record*, std::set<Record*>, LessRecord> &SuperRegs,
157 std::map<Record*, std::set<Record*>, LessRecord> &Aliases) {
159 errs() << "Error: recursive sub-register relationship between"
160 << " register " << getQualifiedName(R)
161 << " and its sub-registers?\n";
165 if (!SubRegs[R].insert(S).second)
167 addSuperReg(S, R, SubRegs, SuperRegs, Aliases);
168 Aliases[R].insert(S);
169 Aliases[S].insert(R);
170 if (SubRegs.count(S))
171 for (std::set<Record*>::iterator I = SubRegs[S].begin(),
172 E = SubRegs[S].end(); I != E; ++I)
173 addSubSuperReg(R, *I, SubRegs, SuperRegs, Aliases);
176 class RegisterSorter {
178 std::map<Record*, std::set<Record*>, LessRecord> &RegisterSubRegs;
181 RegisterSorter(std::map<Record*, std::set<Record*>, LessRecord> &RS)
182 : RegisterSubRegs(RS) {}
184 bool operator()(Record *RegA, Record *RegB) {
185 // B is sub-register of A.
186 return RegisterSubRegs.count(RegA) && RegisterSubRegs[RegA].count(RegB);
190 // RegisterInfoEmitter::run - Main register file description emitter.
192 void RegisterInfoEmitter::run(raw_ostream &OS) {
193 CodeGenTarget Target;
194 EmitSourceFileHeader("Register Information Source Fragment", OS);
196 OS << "namespace llvm {\n\n";
198 // Start out by emitting each of the register classes... to do this, we build
199 // a set of registers which belong to a register class, this is to ensure that
200 // each register is only in a single register class.
202 const std::vector<CodeGenRegisterClass> &RegisterClasses =
203 Target.getRegisterClasses();
205 // Loop over all of the register classes... emitting each one.
206 OS << "namespace { // Register classes...\n";
208 // RegClassesBelongedTo - Keep track of which register classes each reg
210 std::multimap<Record*, const CodeGenRegisterClass*> RegClassesBelongedTo;
212 // Emit the register enum value arrays for each RegisterClass
213 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
214 const CodeGenRegisterClass &RC = RegisterClasses[rc];
216 // Give the register class a legal C name if it's anonymous.
217 std::string Name = RC.TheDef->getName();
219 // Emit the register list now.
220 OS << " // " << Name << " Register Class...\n"
221 << " static const unsigned " << Name
223 for (unsigned i = 0, e = RC.Elements.size(); i != e; ++i) {
224 Record *Reg = RC.Elements[i];
225 OS << getQualifiedName(Reg) << ", ";
227 // Keep track of which regclasses this register is in.
228 RegClassesBelongedTo.insert(std::make_pair(Reg, &RC));
233 // Emit the ValueType arrays for each RegisterClass
234 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
235 const CodeGenRegisterClass &RC = RegisterClasses[rc];
237 // Give the register class a legal C name if it's anonymous.
238 std::string Name = RC.TheDef->getName() + "VTs";
240 // Emit the register list now.
242 << " Register Class Value Types...\n"
243 << " static const EVT " << Name
245 for (unsigned i = 0, e = RC.VTs.size(); i != e; ++i)
246 OS << getEnumName(RC.VTs[i]) << ", ";
247 OS << "MVT::Other\n };\n\n";
249 OS << "} // end anonymous namespace\n\n";
251 // Now that all of the structs have been emitted, emit the instances.
252 if (!RegisterClasses.empty()) {
253 OS << "namespace " << RegisterClasses[0].Namespace
254 << " { // Register class instances\n";
255 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i)
256 OS << " " << RegisterClasses[i].getName() << "Class\t"
257 << RegisterClasses[i].getName() << "RegClass;\n";
259 std::map<unsigned, std::set<unsigned> > SuperClassMap;
260 std::map<unsigned, std::set<unsigned> > SuperRegClassMap;
263 // Emit the sub-register classes for each RegisterClass
264 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
265 const CodeGenRegisterClass &RC = RegisterClasses[rc];
267 // Give the register class a legal C name if it's anonymous.
268 std::string Name = RC.TheDef->getName();
271 << " Sub-register Classes...\n"
272 << " static const TargetRegisterClass* const "
273 << Name << "SubRegClasses[] = {\n ";
277 for (unsigned subrc = 0, subrcMax = RC.SubRegClasses.size();
278 subrc != subrcMax; ++subrc) {
279 unsigned rc2 = 0, e2 = RegisterClasses.size();
280 for (; rc2 != e2; ++rc2) {
281 const CodeGenRegisterClass &RC2 = RegisterClasses[rc2];
282 if (RC.SubRegClasses[subrc]->getName() == RC2.getName()) {
285 OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
288 std::map<unsigned, std::set<unsigned> >::iterator SCMI =
289 SuperRegClassMap.find(rc2);
290 if (SCMI == SuperRegClassMap.end()) {
291 SuperRegClassMap.insert(std::make_pair(rc2,
292 std::set<unsigned>()));
293 SCMI = SuperRegClassMap.find(rc2);
295 SCMI->second.insert(rc);
300 throw "Register Class member '" +
301 RC.SubRegClasses[subrc]->getName() +
302 "' is not a valid RegisterClass!";
305 OS << (!Empty ? ", " : "") << "NULL";
309 // Emit the super-register classes for each RegisterClass
310 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
311 const CodeGenRegisterClass &RC = RegisterClasses[rc];
313 // Give the register class a legal C name if it's anonymous.
314 std::string Name = RC.TheDef->getName();
317 << " Super-register Classes...\n"
318 << " static const TargetRegisterClass* const "
319 << Name << "SuperRegClasses[] = {\n ";
322 std::map<unsigned, std::set<unsigned> >::iterator I =
323 SuperRegClassMap.find(rc);
324 if (I != SuperRegClassMap.end()) {
325 for (std::set<unsigned>::iterator II = I->second.begin(),
326 EE = I->second.end(); II != EE; ++II) {
327 const CodeGenRegisterClass &RC2 = RegisterClasses[*II];
330 OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
335 OS << (!Empty ? ", " : "") << "NULL";
339 // Emit the sub-classes array for each RegisterClass
340 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
341 const CodeGenRegisterClass &RC = RegisterClasses[rc];
343 // Give the register class a legal C name if it's anonymous.
344 std::string Name = RC.TheDef->getName();
346 std::set<Record*> RegSet;
347 for (unsigned i = 0, e = RC.Elements.size(); i != e; ++i) {
348 Record *Reg = RC.Elements[i];
353 << " Register Class sub-classes...\n"
354 << " static const TargetRegisterClass* const "
355 << Name << "Subclasses[] = {\n ";
358 for (unsigned rc2 = 0, e2 = RegisterClasses.size(); rc2 != e2; ++rc2) {
359 const CodeGenRegisterClass &RC2 = RegisterClasses[rc2];
361 // RC2 is a sub-class of RC if it is a valid replacement for any
362 // instruction operand where an RC register is required. It must satisfy
365 // 1. All RC2 registers are also in RC.
366 // 2. The RC2 spill size must not be smaller that the RC spill size.
367 // 3. RC2 spill alignment must be compatible with RC.
369 // Sub-classes are used to determine if a virtual register can be used
370 // as an instruction operand, or if it must be copied first.
372 if (rc == rc2 || RC2.Elements.size() > RC.Elements.size() ||
373 (RC.SpillAlignment && RC2.SpillAlignment % RC.SpillAlignment) ||
374 RC.SpillSize > RC2.SpillSize || !isSubRegisterClass(RC2, RegSet))
377 if (!Empty) OS << ", ";
378 OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
381 std::map<unsigned, std::set<unsigned> >::iterator SCMI =
382 SuperClassMap.find(rc2);
383 if (SCMI == SuperClassMap.end()) {
384 SuperClassMap.insert(std::make_pair(rc2, std::set<unsigned>()));
385 SCMI = SuperClassMap.find(rc2);
387 SCMI->second.insert(rc);
390 OS << (!Empty ? ", " : "") << "NULL";
394 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
395 const CodeGenRegisterClass &RC = RegisterClasses[rc];
397 // Give the register class a legal C name if it's anonymous.
398 std::string Name = RC.TheDef->getName();
401 << " Register Class super-classes...\n"
402 << " static const TargetRegisterClass* const "
403 << Name << "Superclasses[] = {\n ";
406 std::map<unsigned, std::set<unsigned> >::iterator I =
407 SuperClassMap.find(rc);
408 if (I != SuperClassMap.end()) {
409 for (std::set<unsigned>::iterator II = I->second.begin(),
410 EE = I->second.end(); II != EE; ++II) {
411 const CodeGenRegisterClass &RC2 = RegisterClasses[*II];
412 if (!Empty) OS << ", ";
413 OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
418 OS << (!Empty ? ", " : "") << "NULL";
423 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
424 const CodeGenRegisterClass &RC = RegisterClasses[i];
425 OS << RC.MethodBodies << "\n";
426 OS << RC.getName() << "Class::" << RC.getName()
427 << "Class() : TargetRegisterClass("
428 << RC.getName() + "RegClassID" << ", "
429 << '\"' << RC.getName() << "\", "
430 << RC.getName() + "VTs" << ", "
431 << RC.getName() + "Subclasses" << ", "
432 << RC.getName() + "Superclasses" << ", "
433 << RC.getName() + "SubRegClasses" << ", "
434 << RC.getName() + "SuperRegClasses" << ", "
435 << RC.SpillSize/8 << ", "
436 << RC.SpillAlignment/8 << ", "
437 << RC.CopyCost << ", "
438 << RC.getName() << ", " << RC.getName() << " + " << RC.Elements.size()
445 OS << "\nnamespace {\n";
446 OS << " const TargetRegisterClass* const RegisterClasses[] = {\n";
447 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i)
448 OS << " &" << getQualifiedName(RegisterClasses[i].TheDef)
452 // Emit register sub-registers / super-registers, aliases...
453 std::map<Record*, std::set<Record*>, LessRecord> RegisterSubRegs;
454 std::map<Record*, std::set<Record*>, LessRecord> RegisterSuperRegs;
455 std::map<Record*, std::set<Record*>, LessRecord> RegisterAliases;
456 std::map<Record*, std::vector<std::pair<int, Record*> > > SubRegVectors;
457 typedef std::map<Record*, std::vector<int64_t>, LessRecord> DwarfRegNumsMapTy;
458 DwarfRegNumsMapTy DwarfRegNums;
460 const std::vector<CodeGenRegister> &Regs = Target.getRegisters();
462 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
463 Record *R = Regs[i].TheDef;
464 std::vector<Record*> LI = Regs[i].TheDef->getValueAsListOfDefs("Aliases");
465 // Add information that R aliases all of the elements in the list... and
466 // that everything in the list aliases R.
467 for (unsigned j = 0, e = LI.size(); j != e; ++j) {
469 if (RegisterAliases[R].count(Reg))
470 errs() << "Warning: register alias between " << getQualifiedName(R)
471 << " and " << getQualifiedName(Reg)
472 << " specified multiple times!\n";
473 RegisterAliases[R].insert(Reg);
475 if (RegisterAliases[Reg].count(R))
476 errs() << "Warning: register alias between " << getQualifiedName(R)
477 << " and " << getQualifiedName(Reg)
478 << " specified multiple times!\n";
479 RegisterAliases[Reg].insert(R);
483 // Process sub-register sets.
484 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
485 Record *R = Regs[i].TheDef;
486 std::vector<Record*> LI = Regs[i].TheDef->getValueAsListOfDefs("SubRegs");
487 // Process sub-register set and add aliases information.
488 for (unsigned j = 0, e = LI.size(); j != e; ++j) {
489 Record *SubReg = LI[j];
490 if (RegisterSubRegs[R].count(SubReg))
491 errs() << "Warning: register " << getQualifiedName(SubReg)
492 << " specified as a sub-register of " << getQualifiedName(R)
493 << " multiple times!\n";
494 addSubSuperReg(R, SubReg, RegisterSubRegs, RegisterSuperRegs,
499 // Print the SubregHashTable, a simple quadratically probed
500 // hash table for determining if a register is a subregister
501 // of another register.
502 unsigned NumSubRegs = 0;
503 std::map<Record*, unsigned> RegNo;
504 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
505 RegNo[Regs[i].TheDef] = i;
506 NumSubRegs += RegisterSubRegs[Regs[i].TheDef].size();
509 unsigned SubregHashTableSize = 2 * NextPowerOf2(2 * NumSubRegs);
510 unsigned* SubregHashTable = new unsigned[2 * SubregHashTableSize];
511 std::fill(SubregHashTable, SubregHashTable + 2 * SubregHashTableSize, ~0U);
513 unsigned hashMisses = 0;
515 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
516 Record* R = Regs[i].TheDef;
517 for (std::set<Record*>::iterator I = RegisterSubRegs[R].begin(),
518 E = RegisterSubRegs[R].end(); I != E; ++I) {
520 // We have to increase the indices of both registers by one when
521 // computing the hash because, in the generated code, there
522 // will be an extra empty slot at register 0.
523 size_t index = ((i+1) + (RegNo[RJ]+1) * 37) & (SubregHashTableSize-1);
524 unsigned ProbeAmt = 2;
525 while (SubregHashTable[index*2] != ~0U &&
526 SubregHashTable[index*2+1] != ~0U) {
527 index = (index + ProbeAmt) & (SubregHashTableSize-1);
533 SubregHashTable[index*2] = i;
534 SubregHashTable[index*2+1] = RegNo[RJ];
538 OS << "\n\n // Number of hash collisions: " << hashMisses << "\n";
540 if (SubregHashTableSize) {
541 std::string Namespace = Regs[0].TheDef->getValueAsString("Namespace");
543 OS << " const unsigned SubregHashTable[] = { ";
544 for (unsigned i = 0; i < SubregHashTableSize - 1; ++i) {
546 // Insert spaces for nice formatting.
549 if (SubregHashTable[2*i] != ~0U) {
550 OS << getQualifiedName(Regs[SubregHashTable[2*i]].TheDef) << ", "
551 << getQualifiedName(Regs[SubregHashTable[2*i+1]].TheDef) << ", \n";
553 OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister, \n";
557 unsigned Idx = SubregHashTableSize*2-2;
558 if (SubregHashTable[Idx] != ~0U) {
560 << getQualifiedName(Regs[SubregHashTable[Idx]].TheDef) << ", "
561 << getQualifiedName(Regs[SubregHashTable[Idx+1]].TheDef) << " };\n";
563 OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister };\n";
566 OS << " const unsigned SubregHashTableSize = "
567 << SubregHashTableSize << ";\n";
569 OS << " const unsigned SubregHashTable[] = { ~0U, ~0U };\n"
570 << " const unsigned SubregHashTableSize = 1;\n";
573 delete [] SubregHashTable;
576 // Print the SuperregHashTable, a simple quadratically probed
577 // hash table for determining if a register is a super-register
578 // of another register.
579 unsigned NumSupRegs = 0;
581 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
582 RegNo[Regs[i].TheDef] = i;
583 NumSupRegs += RegisterSuperRegs[Regs[i].TheDef].size();
586 unsigned SuperregHashTableSize = 2 * NextPowerOf2(2 * NumSupRegs);
587 unsigned* SuperregHashTable = new unsigned[2 * SuperregHashTableSize];
588 std::fill(SuperregHashTable, SuperregHashTable + 2 * SuperregHashTableSize, ~0U);
592 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
593 Record* R = Regs[i].TheDef;
594 for (std::set<Record*>::iterator I = RegisterSuperRegs[R].begin(),
595 E = RegisterSuperRegs[R].end(); I != E; ++I) {
597 // We have to increase the indices of both registers by one when
598 // computing the hash because, in the generated code, there
599 // will be an extra empty slot at register 0.
600 size_t index = ((i+1) + (RegNo[RJ]+1) * 37) & (SuperregHashTableSize-1);
601 unsigned ProbeAmt = 2;
602 while (SuperregHashTable[index*2] != ~0U &&
603 SuperregHashTable[index*2+1] != ~0U) {
604 index = (index + ProbeAmt) & (SuperregHashTableSize-1);
610 SuperregHashTable[index*2] = i;
611 SuperregHashTable[index*2+1] = RegNo[RJ];
615 OS << "\n\n // Number of hash collisions: " << hashMisses << "\n";
617 if (SuperregHashTableSize) {
618 std::string Namespace = Regs[0].TheDef->getValueAsString("Namespace");
620 OS << " const unsigned SuperregHashTable[] = { ";
621 for (unsigned i = 0; i < SuperregHashTableSize - 1; ++i) {
623 // Insert spaces for nice formatting.
626 if (SuperregHashTable[2*i] != ~0U) {
627 OS << getQualifiedName(Regs[SuperregHashTable[2*i]].TheDef) << ", "
628 << getQualifiedName(Regs[SuperregHashTable[2*i+1]].TheDef) << ", \n";
630 OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister, \n";
634 unsigned Idx = SuperregHashTableSize*2-2;
635 if (SuperregHashTable[Idx] != ~0U) {
637 << getQualifiedName(Regs[SuperregHashTable[Idx]].TheDef) << ", "
638 << getQualifiedName(Regs[SuperregHashTable[Idx+1]].TheDef) << " };\n";
640 OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister };\n";
643 OS << " const unsigned SuperregHashTableSize = "
644 << SuperregHashTableSize << ";\n";
646 OS << " const unsigned SuperregHashTable[] = { ~0U, ~0U };\n"
647 << " const unsigned SuperregHashTableSize = 1;\n";
650 delete [] SuperregHashTable;
653 // Print the AliasHashTable, a simple quadratically probed
654 // hash table for determining if a register aliases another register.
655 unsigned NumAliases = 0;
657 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
658 RegNo[Regs[i].TheDef] = i;
659 NumAliases += RegisterAliases[Regs[i].TheDef].size();
662 unsigned AliasesHashTableSize = 2 * NextPowerOf2(2 * NumAliases);
663 unsigned* AliasesHashTable = new unsigned[2 * AliasesHashTableSize];
664 std::fill(AliasesHashTable, AliasesHashTable + 2 * AliasesHashTableSize, ~0U);
668 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
669 Record* R = Regs[i].TheDef;
670 for (std::set<Record*>::iterator I = RegisterAliases[R].begin(),
671 E = RegisterAliases[R].end(); I != E; ++I) {
673 // We have to increase the indices of both registers by one when
674 // computing the hash because, in the generated code, there
675 // will be an extra empty slot at register 0.
676 size_t index = ((i+1) + (RegNo[RJ]+1) * 37) & (AliasesHashTableSize-1);
677 unsigned ProbeAmt = 2;
678 while (AliasesHashTable[index*2] != ~0U &&
679 AliasesHashTable[index*2+1] != ~0U) {
680 index = (index + ProbeAmt) & (AliasesHashTableSize-1);
686 AliasesHashTable[index*2] = i;
687 AliasesHashTable[index*2+1] = RegNo[RJ];
691 OS << "\n\n // Number of hash collisions: " << hashMisses << "\n";
693 if (AliasesHashTableSize) {
694 std::string Namespace = Regs[0].TheDef->getValueAsString("Namespace");
696 OS << " const unsigned AliasesHashTable[] = { ";
697 for (unsigned i = 0; i < AliasesHashTableSize - 1; ++i) {
699 // Insert spaces for nice formatting.
702 if (AliasesHashTable[2*i] != ~0U) {
703 OS << getQualifiedName(Regs[AliasesHashTable[2*i]].TheDef) << ", "
704 << getQualifiedName(Regs[AliasesHashTable[2*i+1]].TheDef) << ", \n";
706 OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister, \n";
710 unsigned Idx = AliasesHashTableSize*2-2;
711 if (AliasesHashTable[Idx] != ~0U) {
713 << getQualifiedName(Regs[AliasesHashTable[Idx]].TheDef) << ", "
714 << getQualifiedName(Regs[AliasesHashTable[Idx+1]].TheDef) << " };\n";
716 OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister };\n";
719 OS << " const unsigned AliasesHashTableSize = "
720 << AliasesHashTableSize << ";\n";
722 OS << " const unsigned AliasesHashTable[] = { ~0U, ~0U };\n"
723 << " const unsigned AliasesHashTableSize = 1;\n";
726 delete [] AliasesHashTable;
728 if (!RegisterAliases.empty())
729 OS << "\n\n // Register Alias Sets...\n";
731 // Emit the empty alias list
732 OS << " const unsigned Empty_AliasSet[] = { 0 };\n";
733 // Loop over all of the registers which have aliases, emitting the alias list
735 for (std::map<Record*, std::set<Record*>, LessRecord >::iterator
736 I = RegisterAliases.begin(), E = RegisterAliases.end(); I != E; ++I) {
737 OS << " const unsigned " << I->first->getName() << "_AliasSet[] = { ";
738 for (std::set<Record*>::iterator ASI = I->second.begin(),
739 E = I->second.end(); ASI != E; ++ASI)
740 OS << getQualifiedName(*ASI) << ", ";
744 if (!RegisterSubRegs.empty())
745 OS << "\n\n // Register Sub-registers Sets...\n";
747 // Emit the empty sub-registers list
748 OS << " const unsigned Empty_SubRegsSet[] = { 0 };\n";
749 // Loop over all of the registers which have sub-registers, emitting the
750 // sub-registers list to memory.
751 for (std::map<Record*, std::set<Record*>, LessRecord>::iterator
752 I = RegisterSubRegs.begin(), E = RegisterSubRegs.end(); I != E; ++I) {
753 OS << " const unsigned " << I->first->getName() << "_SubRegsSet[] = { ";
754 std::vector<Record*> SubRegsVector;
755 for (std::set<Record*>::iterator ASI = I->second.begin(),
756 E = I->second.end(); ASI != E; ++ASI)
757 SubRegsVector.push_back(*ASI);
758 RegisterSorter RS(RegisterSubRegs);
759 std::stable_sort(SubRegsVector.begin(), SubRegsVector.end(), RS);
760 for (unsigned i = 0, e = SubRegsVector.size(); i != e; ++i)
761 OS << getQualifiedName(SubRegsVector[i]) << ", ";
765 if (!RegisterSuperRegs.empty())
766 OS << "\n\n // Register Super-registers Sets...\n";
768 // Emit the empty super-registers list
769 OS << " const unsigned Empty_SuperRegsSet[] = { 0 };\n";
770 // Loop over all of the registers which have super-registers, emitting the
771 // super-registers list to memory.
772 for (std::map<Record*, std::set<Record*>, LessRecord >::iterator
773 I = RegisterSuperRegs.begin(), E = RegisterSuperRegs.end(); I != E; ++I) {
774 OS << " const unsigned " << I->first->getName() << "_SuperRegsSet[] = { ";
776 std::vector<Record*> SuperRegsVector;
777 for (std::set<Record*>::iterator ASI = I->second.begin(),
778 E = I->second.end(); ASI != E; ++ASI)
779 SuperRegsVector.push_back(*ASI);
780 RegisterSorter RS(RegisterSubRegs);
781 std::stable_sort(SuperRegsVector.begin(), SuperRegsVector.end(), RS);
782 for (unsigned i = 0, e = SuperRegsVector.size(); i != e; ++i)
783 OS << getQualifiedName(SuperRegsVector[i]) << ", ";
787 OS<<"\n const TargetRegisterDesc RegisterDescriptors[] = { // Descriptors\n";
788 OS << " { \"NOREG\",\t0,\t0,\t0 },\n";
790 // Now that register alias and sub-registers sets have been emitted, emit the
791 // register descriptors now.
792 const std::vector<CodeGenRegister> &Registers = Target.getRegisters();
793 for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
794 const CodeGenRegister &Reg = Registers[i];
796 OS << Reg.getName() << "\",\t";
797 if (RegisterAliases.count(Reg.TheDef))
798 OS << Reg.getName() << "_AliasSet,\t";
800 OS << "Empty_AliasSet,\t";
801 if (RegisterSubRegs.count(Reg.TheDef))
802 OS << Reg.getName() << "_SubRegsSet,\t";
804 OS << "Empty_SubRegsSet,\t";
805 if (RegisterSuperRegs.count(Reg.TheDef))
806 OS << Reg.getName() << "_SuperRegsSet },\n";
808 OS << "Empty_SuperRegsSet },\n";
810 OS << " };\n"; // End of register descriptors...
811 OS << "}\n\n"; // End of anonymous namespace...
813 std::string ClassName = Target.getName() + "GenRegisterInfo";
815 // Calculate the mapping of subregister+index pairs to physical registers.
816 std::vector<Record*> SubRegs = Records.getAllDerivedDefinitions("SubRegSet");
817 for (unsigned i = 0, e = SubRegs.size(); i != e; ++i) {
818 int subRegIndex = SubRegs[i]->getValueAsInt("index");
819 std::vector<Record*> From = SubRegs[i]->getValueAsListOfDefs("From");
820 std::vector<Record*> To = SubRegs[i]->getValueAsListOfDefs("To");
822 if (From.size() != To.size()) {
823 errs() << "Error: register list and sub-register list not of equal length"
824 << " in SubRegSet\n";
828 // For each entry in from/to vectors, insert the to register at index
829 for (unsigned ii = 0, ee = From.size(); ii != ee; ++ii)
830 SubRegVectors[From[ii]].push_back(std::make_pair(subRegIndex, To[ii]));
833 // Emit the subregister + index mapping function based on the information
835 OS << "unsigned " << ClassName
836 << "::getSubReg(unsigned RegNo, unsigned Index) const {\n"
837 << " switch (RegNo) {\n"
838 << " default:\n return 0;\n";
839 for (std::map<Record*, std::vector<std::pair<int, Record*> > >::iterator
840 I = SubRegVectors.begin(), E = SubRegVectors.end(); I != E; ++I) {
841 OS << " case " << getQualifiedName(I->first) << ":\n";
842 OS << " switch (Index) {\n";
843 OS << " default: return 0;\n";
844 for (unsigned i = 0, e = I->second.size(); i != e; ++i)
845 OS << " case " << (I->second)[i].first << ": return "
846 << getQualifiedName((I->second)[i].second) << ";\n";
847 OS << " };\n" << " break;\n";
850 OS << " return 0;\n";
853 OS << "unsigned " << ClassName
854 << "::getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const {\n"
855 << " switch (RegNo) {\n"
856 << " default:\n return 0;\n";
857 for (std::map<Record*, std::vector<std::pair<int, Record*> > >::iterator
858 I = SubRegVectors.begin(), E = SubRegVectors.end(); I != E; ++I) {
859 OS << " case " << getQualifiedName(I->first) << ":\n";
860 for (unsigned i = 0, e = I->second.size(); i != e; ++i)
861 OS << " if (SubRegNo == "
862 << getQualifiedName((I->second)[i].second)
863 << ") return " << (I->second)[i].first << ";\n";
864 OS << " return 0;\n";
867 OS << " return 0;\n";
870 // Emit the constructor of the class...
871 OS << ClassName << "::" << ClassName
872 << "(int CallFrameSetupOpcode, int CallFrameDestroyOpcode)\n"
873 << " : TargetRegisterInfo(RegisterDescriptors, " << Registers.size()+1
874 << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n "
875 << " CallFrameSetupOpcode, CallFrameDestroyOpcode,\n"
876 << " SubregHashTable, SubregHashTableSize,\n"
877 << " SuperregHashTable, SuperregHashTableSize,\n"
878 << " AliasesHashTable, AliasesHashTableSize) {\n"
881 // Collect all information about dwarf register numbers
883 // First, just pull all provided information to the map
884 unsigned maxLength = 0;
885 for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
886 Record *Reg = Registers[i].TheDef;
887 std::vector<int64_t> RegNums = Reg->getValueAsListOfInts("DwarfNumbers");
888 maxLength = std::max((size_t)maxLength, RegNums.size());
889 if (DwarfRegNums.count(Reg))
890 errs() << "Warning: DWARF numbers for register " << getQualifiedName(Reg)
891 << "specified multiple times\n";
892 DwarfRegNums[Reg] = RegNums;
895 // Now we know maximal length of number list. Append -1's, where needed
896 for (DwarfRegNumsMapTy::iterator
897 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I)
898 for (unsigned i = I->second.size(), e = maxLength; i != e; ++i)
899 I->second.push_back(-1);
901 // Emit information about the dwarf register numbers.
902 OS << "int " << ClassName << "::getDwarfRegNumFull(unsigned RegNum, "
903 << "unsigned Flavour) const {\n"
904 << " switch (Flavour) {\n"
906 << " assert(0 && \"Unknown DWARF flavour\");\n"
909 for (unsigned i = 0, e = maxLength; i != e; ++i) {
910 OS << " case " << i << ":\n"
911 << " switch (RegNum) {\n"
913 << " assert(0 && \"Invalid RegNum\");\n"
916 // Sort by name to get a stable order.
919 for (DwarfRegNumsMapTy::iterator
920 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
921 int RegNo = I->second[i];
923 OS << " case " << getQualifiedName(I->first) << ":\n"
924 << " return " << RegNo << ";\n";
926 OS << " case " << getQualifiedName(I->first) << ":\n"
927 << " assert(0 && \"Invalid register for this mode\");\n"
935 OS << "} // End llvm namespace \n";