1 //===- RegisterInfoEmitter.cpp - Generate a Register File Desc. -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend is responsible for emitting a description of a target
11 // register file for a code generator. It uses instances of the Register,
12 // RegisterAliases, and RegisterClass classes to gather this information.
14 //===----------------------------------------------------------------------===//
16 #include "CodeGenRegisters.h"
17 #include "CodeGenTarget.h"
18 #include "SequenceToOffsetTable.h"
19 #include "llvm/ADT/BitVector.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/StringExtras.h"
22 #include "llvm/ADT/Twine.h"
23 #include "llvm/Support/Format.h"
24 #include "llvm/TableGen/Error.h"
25 #include "llvm/TableGen/Record.h"
26 #include "llvm/TableGen/TableGenBackend.h"
33 class RegisterInfoEmitter {
34 RecordKeeper &Records;
36 RegisterInfoEmitter(RecordKeeper &R) : Records(R) {}
38 // runEnums - Print out enum values for all of the registers.
39 void runEnums(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank);
41 // runMCDesc - Print out MC register descriptions.
42 void runMCDesc(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank);
44 // runTargetHeader - Emit a header fragment for the register info emitter.
45 void runTargetHeader(raw_ostream &o, CodeGenTarget &Target,
46 CodeGenRegBank &Bank);
48 // runTargetDesc - Output the target register and register file descriptions.
49 void runTargetDesc(raw_ostream &o, CodeGenTarget &Target,
50 CodeGenRegBank &Bank);
52 // run - Output the register file description.
53 void run(raw_ostream &o);
56 void EmitRegMapping(raw_ostream &o,
57 const std::vector<CodeGenRegister*> &Regs, bool isCtor);
58 void EmitRegMappingTables(raw_ostream &o,
59 const std::vector<CodeGenRegister*> &Regs,
61 void EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank,
62 const std::string &ClassName);
63 void emitComposeSubRegIndices(raw_ostream &OS, CodeGenRegBank &RegBank,
64 const std::string &ClassName);
66 } // End anonymous namespace
68 // runEnums - Print out enum values for all of the registers.
69 void RegisterInfoEmitter::runEnums(raw_ostream &OS,
70 CodeGenTarget &Target, CodeGenRegBank &Bank) {
71 const std::vector<CodeGenRegister*> &Registers = Bank.getRegisters();
73 // Register enums are stored as uint16_t in the tables. Make sure we'll fit.
74 assert(Registers.size() <= 0xffff && "Too many regs to fit in tables");
76 std::string Namespace = Registers[0]->TheDef->getValueAsString("Namespace");
78 emitSourceFileHeader("Target Register Enum Values", OS);
80 OS << "\n#ifdef GET_REGINFO_ENUM\n";
81 OS << "#undef GET_REGINFO_ENUM\n";
83 OS << "namespace llvm {\n\n";
85 OS << "class MCRegisterClass;\n"
86 << "extern const MCRegisterClass " << Namespace
87 << "MCRegisterClasses[];\n\n";
89 if (!Namespace.empty())
90 OS << "namespace " << Namespace << " {\n";
91 OS << "enum {\n NoRegister,\n";
93 for (unsigned i = 0, e = Registers.size(); i != e; ++i)
94 OS << " " << Registers[i]->getName() << " = " <<
95 Registers[i]->EnumValue << ",\n";
96 assert(Registers.size() == Registers[Registers.size()-1]->EnumValue &&
97 "Register enum value mismatch!");
98 OS << " NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n";
100 if (!Namespace.empty())
103 ArrayRef<CodeGenRegisterClass*> RegisterClasses = Bank.getRegClasses();
104 if (!RegisterClasses.empty()) {
106 // RegisterClass enums are stored as uint16_t in the tables.
107 assert(RegisterClasses.size() <= 0xffff &&
108 "Too many register classes to fit in tables");
110 OS << "\n// Register classes\n";
111 if (!Namespace.empty())
112 OS << "namespace " << Namespace << " {\n";
114 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
116 OS << " " << RegisterClasses[i]->getName() << "RegClassID";
120 if (!Namespace.empty())
124 const std::vector<Record*> &RegAltNameIndices = Target.getRegAltNameIndices();
125 // If the only definition is the default NoRegAltName, we don't need to
127 if (RegAltNameIndices.size() > 1) {
128 OS << "\n// Register alternate name indices\n";
129 if (!Namespace.empty())
130 OS << "namespace " << Namespace << " {\n";
132 for (unsigned i = 0, e = RegAltNameIndices.size(); i != e; ++i)
133 OS << " " << RegAltNameIndices[i]->getName() << ",\t// " << i << "\n";
134 OS << " NUM_TARGET_REG_ALT_NAMES = " << RegAltNameIndices.size() << "\n";
136 if (!Namespace.empty())
140 ArrayRef<CodeGenSubRegIndex*> SubRegIndices = Bank.getSubRegIndices();
141 if (!SubRegIndices.empty()) {
142 OS << "\n// Subregister indices\n";
143 std::string Namespace =
144 SubRegIndices[0]->getNamespace();
145 if (!Namespace.empty())
146 OS << "namespace " << Namespace << " {\n";
147 OS << "enum {\n NoSubRegister,\n";
148 for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i)
149 OS << " " << SubRegIndices[i]->getName() << ",\t// " << i+1 << "\n";
150 OS << " NUM_TARGET_SUBREGS\n};\n";
151 if (!Namespace.empty())
155 OS << "} // End llvm namespace\n";
156 OS << "#endif // GET_REGINFO_ENUM\n\n";
159 static void printInt(raw_ostream &OS, int Val) {
163 static const char *getMinimalTypeForRange(uint64_t Range) {
164 assert(Range < 0xFFFFFFFFULL && "Enum too large");
172 void RegisterInfoEmitter::
173 EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank,
174 const std::string &ClassName) {
175 unsigned NumRCs = RegBank.getRegClasses().size();
176 unsigned NumSets = RegBank.getNumRegPressureSets();
178 OS << "/// Get the weight in units of pressure for this register class.\n"
179 << "const RegClassWeight &" << ClassName << "::\n"
180 << "getRegClassWeight(const TargetRegisterClass *RC) const {\n"
181 << " static const RegClassWeight RCWeightTable[] = {\n";
182 for (unsigned i = 0, e = NumRCs; i != e; ++i) {
183 const CodeGenRegisterClass &RC = *RegBank.getRegClasses()[i];
184 const CodeGenRegister::Set &Regs = RC.getMembers();
188 std::vector<unsigned> RegUnits;
189 RC.buildRegUnitSet(RegUnits);
190 OS << " {" << (*Regs.begin())->getWeight(RegBank)
191 << ", " << RegBank.getRegUnitSetWeight(RegUnits);
193 OS << "}, \t// " << RC.getName() << "\n";
196 << " return RCWeightTable[RC->getID()];\n"
199 // Reasonable targets (not ARMv7) have unit weight for all units, so don't
200 // bother generating a table.
201 bool RegUnitsHaveUnitWeight = true;
202 for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits();
203 UnitIdx < UnitEnd; ++UnitIdx) {
204 if (RegBank.getRegUnit(UnitIdx).Weight > 1)
205 RegUnitsHaveUnitWeight = false;
207 OS << "/// Get the weight in units of pressure for this register unit.\n"
208 << "unsigned " << ClassName << "::\n"
209 << "getRegUnitWeight(unsigned RegUnit) const {\n"
210 << " assert(RegUnit < " << RegBank.getNumNativeRegUnits()
211 << " && \"invalid register unit\");\n";
212 if (!RegUnitsHaveUnitWeight) {
213 OS << " static const uint8_t RUWeightTable[] = {\n ";
214 for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits();
215 UnitIdx < UnitEnd; ++UnitIdx) {
216 const RegUnit &RU = RegBank.getRegUnit(UnitIdx);
217 assert(RU.Weight < 256 && "RegUnit too heavy");
218 OS << RU.Weight << ", ";
221 << " return RUWeightTable[RegUnit];\n";
224 OS << " // All register units have unit weight.\n"
230 << "// Get the number of dimensions of register pressure.\n"
231 << "unsigned " << ClassName << "::getNumRegPressureSets() const {\n"
232 << " return " << NumSets << ";\n}\n\n";
234 OS << "// Get the name of this register unit pressure set.\n"
235 << "const char *" << ClassName << "::\n"
236 << "getRegPressureSetName(unsigned Idx) const {\n"
237 << " static const char *PressureNameTable[] = {\n";
238 unsigned MaxRegUnitWeight = 0;
239 for (unsigned i = 0; i < NumSets; ++i ) {
240 const RegUnitSet &RegUnits = RegBank.getRegSetAt(i);
241 MaxRegUnitWeight = std::max(MaxRegUnitWeight, RegUnits.Weight);
242 OS << " \"" << RegUnits.Name << "\",\n";
244 OS << " nullptr };\n"
245 << " return PressureNameTable[Idx];\n"
248 OS << "// Get the register unit pressure limit for this dimension.\n"
249 << "// This limit must be adjusted dynamically for reserved registers.\n"
250 << "unsigned " << ClassName << "::\n"
251 << "getRegPressureSetLimit(unsigned Idx) const {\n"
252 << " static const " << getMinimalTypeForRange(MaxRegUnitWeight)
253 << " PressureLimitTable[] = {\n";
254 for (unsigned i = 0; i < NumSets; ++i ) {
255 const RegUnitSet &RegUnits = RegBank.getRegSetAt(i);
256 OS << " " << RegUnits.Weight << ", \t// " << i << ": "
257 << RegUnits.Name << "\n";
260 << " return PressureLimitTable[Idx];\n"
263 SequenceToOffsetTable<std::vector<int>> PSetsSeqs;
265 // This table may be larger than NumRCs if some register units needed a list
266 // of unit sets that did not correspond to a register class.
267 unsigned NumRCUnitSets = RegBank.getNumRegClassPressureSetLists();
268 std::vector<std::vector<int>> PSets(NumRCUnitSets);
270 for (unsigned i = 0, e = NumRCUnitSets; i != e; ++i) {
271 ArrayRef<unsigned> PSetIDs = RegBank.getRCPressureSetIDs(i);
272 PSets[i].reserve(PSetIDs.size());
273 for (ArrayRef<unsigned>::iterator PSetI = PSetIDs.begin(),
274 PSetE = PSetIDs.end(); PSetI != PSetE; ++PSetI) {
275 PSets[i].push_back(RegBank.getRegPressureSet(*PSetI).Order);
277 std::sort(PSets[i].begin(), PSets[i].end());
278 PSetsSeqs.add(PSets[i]);
283 OS << "/// Table of pressure sets per register class or unit.\n"
284 << "static const int RCSetsTable[] = {\n";
285 PSetsSeqs.emit(OS, printInt, "-1");
288 OS << "/// Get the dimensions of register pressure impacted by this "
289 << "register class.\n"
290 << "/// Returns a -1 terminated array of pressure set IDs\n"
291 << "const int* " << ClassName << "::\n"
292 << "getRegClassPressureSets(const TargetRegisterClass *RC) const {\n";
293 OS << " static const " << getMinimalTypeForRange(PSetsSeqs.size()-1)
294 << " RCSetStartTable[] = {\n ";
295 for (unsigned i = 0, e = NumRCs; i != e; ++i) {
296 OS << PSetsSeqs.get(PSets[i]) << ",";
299 << " return &RCSetsTable[RCSetStartTable[RC->getID()]];\n"
302 OS << "/// Get the dimensions of register pressure impacted by this "
303 << "register unit.\n"
304 << "/// Returns a -1 terminated array of pressure set IDs\n"
305 << "const int* " << ClassName << "::\n"
306 << "getRegUnitPressureSets(unsigned RegUnit) const {\n"
307 << " assert(RegUnit < " << RegBank.getNumNativeRegUnits()
308 << " && \"invalid register unit\");\n";
309 OS << " static const " << getMinimalTypeForRange(PSetsSeqs.size()-1)
310 << " RUSetStartTable[] = {\n ";
311 for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits();
312 UnitIdx < UnitEnd; ++UnitIdx) {
313 OS << PSetsSeqs.get(PSets[RegBank.getRegUnit(UnitIdx).RegClassUnitSetsIdx])
317 << " return &RCSetsTable[RUSetStartTable[RegUnit]];\n"
322 RegisterInfoEmitter::EmitRegMappingTables(raw_ostream &OS,
323 const std::vector<CodeGenRegister*> &Regs,
325 // Collect all information about dwarf register numbers
326 typedef std::map<Record*, std::vector<int64_t>, LessRecordRegister> DwarfRegNumsMapTy;
327 DwarfRegNumsMapTy DwarfRegNums;
329 // First, just pull all provided information to the map
330 unsigned maxLength = 0;
331 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
332 Record *Reg = Regs[i]->TheDef;
333 std::vector<int64_t> RegNums = Reg->getValueAsListOfInts("DwarfNumbers");
334 maxLength = std::max((size_t)maxLength, RegNums.size());
335 if (DwarfRegNums.count(Reg))
336 PrintWarning(Reg->getLoc(), Twine("DWARF numbers for register ") +
337 getQualifiedName(Reg) + "specified multiple times");
338 DwarfRegNums[Reg] = RegNums;
344 // Now we know maximal length of number list. Append -1's, where needed
345 for (DwarfRegNumsMapTy::iterator
346 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I)
347 for (unsigned i = I->second.size(), e = maxLength; i != e; ++i)
348 I->second.push_back(-1);
350 std::string Namespace = Regs[0]->TheDef->getValueAsString("Namespace");
352 OS << "// " << Namespace << " Dwarf<->LLVM register mappings.\n";
354 // Emit reverse information about the dwarf register numbers.
355 for (unsigned j = 0; j < 2; ++j) {
356 for (unsigned i = 0, e = maxLength; i != e; ++i) {
357 OS << "extern const MCRegisterInfo::DwarfLLVMRegPair " << Namespace;
358 OS << (j == 0 ? "DwarfFlavour" : "EHFlavour");
359 OS << i << "Dwarf2L[]";
364 // Store the mapping sorted by the LLVM reg num so lookup can be done
365 // with a binary search.
366 std::map<uint64_t, Record*> Dwarf2LMap;
367 for (DwarfRegNumsMapTy::iterator
368 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
369 int DwarfRegNo = I->second[i];
372 Dwarf2LMap[DwarfRegNo] = I->first;
375 for (std::map<uint64_t, Record*>::iterator
376 I = Dwarf2LMap.begin(), E = Dwarf2LMap.end(); I != E; ++I)
377 OS << " { " << I->first << "U, " << getQualifiedName(I->second)
385 // We have to store the size in a const global, it's used in multiple
387 OS << "extern const unsigned " << Namespace
388 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i << "Dwarf2LSize";
390 OS << " = array_lengthof(" << Namespace
391 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i
398 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
399 Record *Reg = Regs[i]->TheDef;
400 const RecordVal *V = Reg->getValue("DwarfAlias");
401 if (!V || !V->getValue())
404 DefInit *DI = cast<DefInit>(V->getValue());
405 Record *Alias = DI->getDef();
406 DwarfRegNums[Reg] = DwarfRegNums[Alias];
409 // Emit information about the dwarf register numbers.
410 for (unsigned j = 0; j < 2; ++j) {
411 for (unsigned i = 0, e = maxLength; i != e; ++i) {
412 OS << "extern const MCRegisterInfo::DwarfLLVMRegPair " << Namespace;
413 OS << (j == 0 ? "DwarfFlavour" : "EHFlavour");
414 OS << i << "L2Dwarf[]";
417 // Store the mapping sorted by the Dwarf reg num so lookup can be done
418 // with a binary search.
419 for (DwarfRegNumsMapTy::iterator
420 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
421 int RegNo = I->second[i];
422 if (RegNo == -1) // -1 is the default value, don't emit a mapping.
425 OS << " { " << getQualifiedName(I->first) << ", " << RegNo
433 // We have to store the size in a const global, it's used in multiple
435 OS << "extern const unsigned " << Namespace
436 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i << "L2DwarfSize";
438 OS << " = array_lengthof(" << Namespace
439 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i << "L2Dwarf);\n\n";
447 RegisterInfoEmitter::EmitRegMapping(raw_ostream &OS,
448 const std::vector<CodeGenRegister*> &Regs,
450 // Emit the initializer so the tables from EmitRegMappingTables get wired up
451 // to the MCRegisterInfo object.
452 unsigned maxLength = 0;
453 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
454 Record *Reg = Regs[i]->TheDef;
455 maxLength = std::max((size_t)maxLength,
456 Reg->getValueAsListOfInts("DwarfNumbers").size());
462 std::string Namespace = Regs[0]->TheDef->getValueAsString("Namespace");
464 // Emit reverse information about the dwarf register numbers.
465 for (unsigned j = 0; j < 2; ++j) {
468 OS << "DwarfFlavour";
473 << " llvm_unreachable(\"Unknown DWARF flavour\");\n";
475 for (unsigned i = 0, e = maxLength; i != e; ++i) {
476 OS << " case " << i << ":\n";
481 raw_string_ostream(Tmp) << Namespace
482 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i
484 OS << "mapDwarfRegsToLLVMRegs(" << Tmp << ", " << Tmp << "Size, ";
495 // Emit information about the dwarf register numbers.
496 for (unsigned j = 0; j < 2; ++j) {
499 OS << "DwarfFlavour";
504 << " llvm_unreachable(\"Unknown DWARF flavour\");\n";
506 for (unsigned i = 0, e = maxLength; i != e; ++i) {
507 OS << " case " << i << ":\n";
512 raw_string_ostream(Tmp) << Namespace
513 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i
515 OS << "mapLLVMRegsToDwarfRegs(" << Tmp << ", " << Tmp << "Size, ";
527 // Print a BitVector as a sequence of hex numbers using a little-endian mapping.
528 // Width is the number of bits per hex number.
529 static void printBitVectorAsHex(raw_ostream &OS,
530 const BitVector &Bits,
532 assert(Width <= 32 && "Width too large");
533 unsigned Digits = (Width + 3) / 4;
534 for (unsigned i = 0, e = Bits.size(); i < e; i += Width) {
536 for (unsigned j = 0; j != Width && i + j != e; ++j)
537 Value |= Bits.test(i + j) << j;
538 OS << format("0x%0*x, ", Digits, Value);
542 // Helper to emit a set of bits into a constant byte array.
543 class BitVectorEmitter {
546 void add(unsigned v) {
547 if (v >= Values.size())
548 Values.resize(((v/8)+1)*8); // Round up to the next byte.
552 void print(raw_ostream &OS) {
553 printBitVectorAsHex(OS, Values, 8);
557 static void printSimpleValueType(raw_ostream &OS, MVT::SimpleValueType VT) {
558 OS << getEnumName(VT);
561 static void printSubRegIndex(raw_ostream &OS, const CodeGenSubRegIndex *Idx) {
562 OS << Idx->EnumValue;
565 // Differentially encoded register and regunit lists allow for better
566 // compression on regular register banks. The sequence is computed from the
567 // differential list as:
570 // out[n+1] = out[n] + diff[n]; // n = 0, 1, ...
572 // The initial value depends on the specific list. The list is terminated by a
573 // 0 differential which means we can't encode repeated elements.
575 typedef SmallVector<uint16_t, 4> DiffVec;
577 // Differentially encode a sequence of numbers into V. The starting value and
578 // terminating 0 are not added to V, so it will have the same size as List.
580 DiffVec &diffEncode(DiffVec &V, unsigned InitVal, ArrayRef<unsigned> List) {
581 assert(V.empty() && "Clear DiffVec before diffEncode.");
582 uint16_t Val = uint16_t(InitVal);
583 for (unsigned i = 0; i != List.size(); ++i) {
584 uint16_t Cur = List[i];
585 V.push_back(Cur - Val);
591 template<typename Iter>
593 DiffVec &diffEncode(DiffVec &V, unsigned InitVal, Iter Begin, Iter End) {
594 assert(V.empty() && "Clear DiffVec before diffEncode.");
595 uint16_t Val = uint16_t(InitVal);
596 for (Iter I = Begin; I != End; ++I) {
597 uint16_t Cur = (*I)->EnumValue;
598 V.push_back(Cur - Val);
604 static void printDiff16(raw_ostream &OS, uint16_t Val) {
608 // Try to combine Idx's compose map into Vec if it is compatible.
609 // Return false if it's not possible.
610 static bool combine(const CodeGenSubRegIndex *Idx,
611 SmallVectorImpl<CodeGenSubRegIndex*> &Vec) {
612 const CodeGenSubRegIndex::CompMap &Map = Idx->getComposites();
613 for (CodeGenSubRegIndex::CompMap::const_iterator
614 I = Map.begin(), E = Map.end(); I != E; ++I) {
615 CodeGenSubRegIndex *&Entry = Vec[I->first->EnumValue - 1];
616 if (Entry && Entry != I->second)
620 // All entries are compatible. Make it so.
621 for (CodeGenSubRegIndex::CompMap::const_iterator
622 I = Map.begin(), E = Map.end(); I != E; ++I)
623 Vec[I->first->EnumValue - 1] = I->second;
628 RegisterInfoEmitter::emitComposeSubRegIndices(raw_ostream &OS,
629 CodeGenRegBank &RegBank,
630 const std::string &ClName) {
631 ArrayRef<CodeGenSubRegIndex*> SubRegIndices = RegBank.getSubRegIndices();
632 OS << "unsigned " << ClName
633 << "::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {\n";
635 // Many sub-register indexes are composition-compatible, meaning that
637 // compose(IdxA, IdxB) == compose(IdxA', IdxB)
639 // for many IdxA, IdxA' pairs. Not all sub-register indexes can be composed.
640 // The illegal entries can be use as wildcards to compress the table further.
642 // Map each Sub-register index to a compatible table row.
643 SmallVector<unsigned, 4> RowMap;
644 SmallVector<SmallVector<CodeGenSubRegIndex*, 4>, 4> Rows;
646 for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) {
647 unsigned Found = ~0u;
648 for (unsigned r = 0, re = Rows.size(); r != re; ++r) {
649 if (combine(SubRegIndices[i], Rows[r])) {
656 Rows.resize(Found + 1);
657 Rows.back().resize(SubRegIndices.size());
658 combine(SubRegIndices[i], Rows.back());
660 RowMap.push_back(Found);
663 // Output the row map if there is multiple rows.
664 if (Rows.size() > 1) {
665 OS << " static const " << getMinimalTypeForRange(Rows.size())
666 << " RowMap[" << SubRegIndices.size() << "] = {\n ";
667 for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i)
668 OS << RowMap[i] << ", ";
673 OS << " static const " << getMinimalTypeForRange(SubRegIndices.size()+1)
674 << " Rows[" << Rows.size() << "][" << SubRegIndices.size() << "] = {\n";
675 for (unsigned r = 0, re = Rows.size(); r != re; ++r) {
677 for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i)
679 OS << Rows[r][i]->EnumValue << ", ";
686 OS << " --IdxA; assert(IdxA < " << SubRegIndices.size() << ");\n"
687 << " --IdxB; assert(IdxB < " << SubRegIndices.size() << ");\n";
689 OS << " return Rows[RowMap[IdxA]][IdxB];\n";
691 OS << " return Rows[0][IdxB];\n";
696 // runMCDesc - Print out MC register descriptions.
699 RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target,
700 CodeGenRegBank &RegBank) {
701 emitSourceFileHeader("MC Register Information", OS);
703 OS << "\n#ifdef GET_REGINFO_MC_DESC\n";
704 OS << "#undef GET_REGINFO_MC_DESC\n";
706 const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters();
708 ArrayRef<CodeGenSubRegIndex*> SubRegIndices = RegBank.getSubRegIndices();
709 // The lists of sub-registers and super-registers go in the same array. That
710 // allows us to share suffixes.
711 typedef std::vector<const CodeGenRegister*> RegVec;
713 // Differentially encoded lists.
714 SequenceToOffsetTable<DiffVec> DiffSeqs;
715 SmallVector<DiffVec, 4> SubRegLists(Regs.size());
716 SmallVector<DiffVec, 4> SuperRegLists(Regs.size());
717 SmallVector<DiffVec, 4> RegUnitLists(Regs.size());
718 SmallVector<unsigned, 4> RegUnitInitScale(Regs.size());
720 // Keep track of sub-register names as well. These are not differentially
722 typedef SmallVector<const CodeGenSubRegIndex*, 4> SubRegIdxVec;
723 SequenceToOffsetTable<SubRegIdxVec, CodeGenSubRegIndex::Less> SubRegIdxSeqs;
724 SmallVector<SubRegIdxVec, 4> SubRegIdxLists(Regs.size());
726 SequenceToOffsetTable<std::string> RegStrings;
728 // Precompute register lists for the SequenceToOffsetTable.
729 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
730 const CodeGenRegister *Reg = Regs[i];
732 RegStrings.add(Reg->getName());
734 // Compute the ordered sub-register list.
735 SetVector<const CodeGenRegister*> SR;
736 Reg->addSubRegsPreOrder(SR, RegBank);
737 diffEncode(SubRegLists[i], Reg->EnumValue, SR.begin(), SR.end());
738 DiffSeqs.add(SubRegLists[i]);
740 // Compute the corresponding sub-register indexes.
741 SubRegIdxVec &SRIs = SubRegIdxLists[i];
742 for (unsigned j = 0, je = SR.size(); j != je; ++j)
743 SRIs.push_back(Reg->getSubRegIndex(SR[j]));
744 SubRegIdxSeqs.add(SRIs);
746 // Super-registers are already computed.
747 const RegVec &SuperRegList = Reg->getSuperRegs();
748 diffEncode(SuperRegLists[i], Reg->EnumValue,
749 SuperRegList.begin(), SuperRegList.end());
750 DiffSeqs.add(SuperRegLists[i]);
752 // Differentially encode the register unit list, seeded by register number.
753 // First compute a scale factor that allows more diff-lists to be reused:
758 // A scale factor of 2 allows D0 and D1 to share a diff-list. The initial
759 // value for the differential decoder is the register number multiplied by
762 // Check the neighboring registers for arithmetic progressions.
763 unsigned ScaleA = ~0u, ScaleB = ~0u;
764 ArrayRef<unsigned> RUs = Reg->getNativeRegUnits();
765 if (i > 0 && Regs[i-1]->getNativeRegUnits().size() == RUs.size())
766 ScaleB = RUs.front() - Regs[i-1]->getNativeRegUnits().front();
767 if (i+1 != Regs.size() &&
768 Regs[i+1]->getNativeRegUnits().size() == RUs.size())
769 ScaleA = Regs[i+1]->getNativeRegUnits().front() - RUs.front();
770 unsigned Scale = std::min(ScaleB, ScaleA);
771 // Default the scale to 0 if it can't be encoded in 4 bits.
774 RegUnitInitScale[i] = Scale;
775 DiffSeqs.add(diffEncode(RegUnitLists[i], Scale * Reg->EnumValue, RUs));
778 // Compute the final layout of the sequence table.
780 SubRegIdxSeqs.layout();
782 OS << "namespace llvm {\n\n";
784 const std::string &TargetName = Target.getName();
786 // Emit the shared table of differential lists.
787 OS << "extern const MCPhysReg " << TargetName << "RegDiffLists[] = {\n";
788 DiffSeqs.emit(OS, printDiff16);
791 // Emit the table of sub-register indexes.
792 OS << "extern const uint16_t " << TargetName << "SubRegIdxLists[] = {\n";
793 SubRegIdxSeqs.emit(OS, printSubRegIndex);
796 // Emit the table of sub-register index sizes.
797 OS << "extern const MCRegisterInfo::SubRegCoveredBits "
798 << TargetName << "SubRegIdxRanges[] = {\n";
799 OS << " { " << (uint16_t)-1 << ", " << (uint16_t)-1 << " },\n";
800 for (ArrayRef<CodeGenSubRegIndex*>::const_iterator
801 SRI = SubRegIndices.begin(), SRE = SubRegIndices.end();
803 OS << " { " << (*SRI)->Offset << ", "
805 << " },\t// " << (*SRI)->getName() << "\n";
809 // Emit the string table.
811 OS << "extern const char " << TargetName << "RegStrings[] = {\n";
812 RegStrings.emit(OS, printChar);
815 OS << "extern const MCRegisterDesc " << TargetName
816 << "RegDesc[] = { // Descriptors\n";
817 OS << " { " << RegStrings.get("") << ", 0, 0, 0, 0 },\n";
819 // Emit the register descriptors now.
820 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
821 const CodeGenRegister *Reg = Regs[i];
822 OS << " { " << RegStrings.get(Reg->getName()) << ", "
823 << DiffSeqs.get(SubRegLists[i]) << ", "
824 << DiffSeqs.get(SuperRegLists[i]) << ", "
825 << SubRegIdxSeqs.get(SubRegIdxLists[i]) << ", "
826 << (DiffSeqs.get(RegUnitLists[i])*16 + RegUnitInitScale[i]) << " },\n";
828 OS << "};\n\n"; // End of register descriptors...
830 // Emit the table of register unit roots. Each regunit has one or two root
832 OS << "extern const MCPhysReg " << TargetName << "RegUnitRoots[][2] = {\n";
833 for (unsigned i = 0, e = RegBank.getNumNativeRegUnits(); i != e; ++i) {
834 ArrayRef<const CodeGenRegister*> Roots = RegBank.getRegUnit(i).getRoots();
835 assert(!Roots.empty() && "All regunits must have a root register.");
836 assert(Roots.size() <= 2 && "More than two roots not supported yet.");
837 OS << " { " << getQualifiedName(Roots.front()->TheDef);
838 for (unsigned r = 1; r != Roots.size(); ++r)
839 OS << ", " << getQualifiedName(Roots[r]->TheDef);
844 ArrayRef<CodeGenRegisterClass*> RegisterClasses = RegBank.getRegClasses();
846 // Loop over all of the register classes... emitting each one.
847 OS << "namespace { // Register classes...\n";
849 SequenceToOffsetTable<std::string> RegClassStrings;
851 // Emit the register enum value arrays for each RegisterClass
852 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
853 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
854 ArrayRef<Record*> Order = RC.getOrder();
856 // Give the register class a legal C name if it's anonymous.
857 std::string Name = RC.getName();
859 RegClassStrings.add(Name);
861 // Emit the register list now.
862 OS << " // " << Name << " Register Class...\n"
863 << " const MCPhysReg " << Name
865 for (unsigned i = 0, e = Order.size(); i != e; ++i) {
866 Record *Reg = Order[i];
867 OS << getQualifiedName(Reg) << ", ";
871 OS << " // " << Name << " Bit set.\n"
872 << " const uint8_t " << Name
874 BitVectorEmitter BVE;
875 for (unsigned i = 0, e = Order.size(); i != e; ++i) {
876 Record *Reg = Order[i];
877 BVE.add(Target.getRegBank().getReg(Reg)->EnumValue);
885 RegClassStrings.layout();
886 OS << "extern const char " << TargetName << "RegClassStrings[] = {\n";
887 RegClassStrings.emit(OS, printChar);
890 OS << "extern const MCRegisterClass " << TargetName
891 << "MCRegisterClasses[] = {\n";
893 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
894 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
896 // Asserts to make sure values will fit in table assuming types from
898 assert((RC.SpillSize/8) <= 0xffff && "SpillSize too large.");
899 assert((RC.SpillAlignment/8) <= 0xffff && "SpillAlignment too large.");
900 assert(RC.CopyCost >= -128 && RC.CopyCost <= 127 && "Copy cost too large.");
902 OS << " { " << RC.getName() << ", " << RC.getName() << "Bits, "
903 << RegClassStrings.get(RC.getName()) << ", "
904 << RC.getOrder().size() << ", sizeof(" << RC.getName() << "Bits), "
905 << RC.getQualifiedName() + "RegClassID" << ", "
906 << RC.SpillSize/8 << ", "
907 << RC.SpillAlignment/8 << ", "
908 << RC.CopyCost << ", "
909 << RC.Allocatable << " },\n";
914 EmitRegMappingTables(OS, Regs, false);
916 // Emit Reg encoding table
917 OS << "extern const uint16_t " << TargetName;
918 OS << "RegEncodingTable[] = {\n";
919 // Add entry for NoRegister
921 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
922 Record *Reg = Regs[i]->TheDef;
923 BitsInit *BI = Reg->getValueAsBitsInit("HWEncoding");
925 for (unsigned b = 0, be = BI->getNumBits(); b != be; ++b) {
926 if (BitInit *B = dyn_cast<BitInit>(BI->getBit(b)))
927 Value |= (uint64_t)B->getValue() << b;
929 OS << " " << Value << ",\n";
931 OS << "};\n"; // End of HW encoding table
933 // MCRegisterInfo initialization routine.
934 OS << "static inline void Init" << TargetName
935 << "MCRegisterInfo(MCRegisterInfo *RI, unsigned RA, "
936 << "unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {\n"
937 << " RI->InitMCRegisterInfo(" << TargetName << "RegDesc, "
938 << Regs.size()+1 << ", RA, PC, " << TargetName << "MCRegisterClasses, "
939 << RegisterClasses.size() << ", "
940 << TargetName << "RegUnitRoots, "
941 << RegBank.getNumNativeRegUnits() << ", "
942 << TargetName << "RegDiffLists, "
943 << TargetName << "RegStrings, "
944 << TargetName << "RegClassStrings, "
945 << TargetName << "SubRegIdxLists, "
946 << (SubRegIndices.size() + 1) << ",\n"
947 << TargetName << "SubRegIdxRanges, "
948 << TargetName << "RegEncodingTable);\n\n";
950 EmitRegMapping(OS, Regs, false);
954 OS << "} // End llvm namespace\n";
955 OS << "#endif // GET_REGINFO_MC_DESC\n\n";
959 RegisterInfoEmitter::runTargetHeader(raw_ostream &OS, CodeGenTarget &Target,
960 CodeGenRegBank &RegBank) {
961 emitSourceFileHeader("Register Information Header Fragment", OS);
963 OS << "\n#ifdef GET_REGINFO_HEADER\n";
964 OS << "#undef GET_REGINFO_HEADER\n";
966 const std::string &TargetName = Target.getName();
967 std::string ClassName = TargetName + "GenRegisterInfo";
969 OS << "#include \"llvm/Target/TargetRegisterInfo.h\"\n\n";
971 OS << "namespace llvm {\n\n";
973 OS << "struct " << ClassName << " : public TargetRegisterInfo {\n"
974 << " explicit " << ClassName
975 << "(unsigned RA, unsigned D = 0, unsigned E = 0, unsigned PC = 0);\n"
976 << " bool needsStackRealignment(const MachineFunction &) const override\n"
977 << " { return false; }\n";
978 if (!RegBank.getSubRegIndices().empty()) {
979 OS << " unsigned composeSubRegIndicesImpl"
980 << "(unsigned, unsigned) const override;\n"
981 << " const TargetRegisterClass *getSubClassWithSubReg"
982 << "(const TargetRegisterClass*, unsigned) const override;\n";
984 OS << " const RegClassWeight &getRegClassWeight("
985 << "const TargetRegisterClass *RC) const override;\n"
986 << " unsigned getRegUnitWeight(unsigned RegUnit) const override;\n"
987 << " unsigned getNumRegPressureSets() const override;\n"
988 << " const char *getRegPressureSetName(unsigned Idx) const override;\n"
989 << " unsigned getRegPressureSetLimit(unsigned Idx) const override;\n"
990 << " const int *getRegClassPressureSets("
991 << "const TargetRegisterClass *RC) const override;\n"
992 << " const int *getRegUnitPressureSets("
993 << "unsigned RegUnit) const override;\n"
996 ArrayRef<CodeGenRegisterClass*> RegisterClasses = RegBank.getRegClasses();
998 if (!RegisterClasses.empty()) {
999 OS << "namespace " << RegisterClasses[0]->Namespace
1000 << " { // Register classes\n";
1002 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
1003 const CodeGenRegisterClass &RC = *RegisterClasses[i];
1004 const std::string &Name = RC.getName();
1006 // Output the extern for the instance.
1007 OS << " extern const TargetRegisterClass " << Name << "RegClass;\n";
1009 OS << "} // end of namespace " << TargetName << "\n\n";
1011 OS << "} // End llvm namespace\n";
1012 OS << "#endif // GET_REGINFO_HEADER\n\n";
1016 // runTargetDesc - Output the target register and register file descriptions.
1019 RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
1020 CodeGenRegBank &RegBank){
1021 emitSourceFileHeader("Target Register and Register Classes Information", OS);
1023 OS << "\n#ifdef GET_REGINFO_TARGET_DESC\n";
1024 OS << "#undef GET_REGINFO_TARGET_DESC\n";
1026 OS << "namespace llvm {\n\n";
1028 // Get access to MCRegisterClass data.
1029 OS << "extern const MCRegisterClass " << Target.getName()
1030 << "MCRegisterClasses[];\n";
1032 // Start out by emitting each of the register classes.
1033 ArrayRef<CodeGenRegisterClass*> RegisterClasses = RegBank.getRegClasses();
1034 ArrayRef<CodeGenSubRegIndex*> SubRegIndices = RegBank.getSubRegIndices();
1036 // Collect all registers belonging to any allocatable class.
1037 std::set<Record*> AllocatableRegs;
1039 // Collect allocatable registers.
1040 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
1041 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
1042 ArrayRef<Record*> Order = RC.getOrder();
1045 AllocatableRegs.insert(Order.begin(), Order.end());
1048 // Build a shared array of value types.
1049 SequenceToOffsetTable<SmallVector<MVT::SimpleValueType, 4> > VTSeqs;
1050 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc)
1051 VTSeqs.add(RegisterClasses[rc]->VTs);
1053 OS << "\nstatic const MVT::SimpleValueType VTLists[] = {\n";
1054 VTSeqs.emit(OS, printSimpleValueType, "MVT::Other");
1057 // Emit SubRegIndex names, skipping 0.
1058 OS << "\nstatic const char *const SubRegIndexNameTable[] = { \"";
1059 for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) {
1060 OS << SubRegIndices[i]->getName();
1066 // Emit SubRegIndex lane masks, including 0.
1067 OS << "\nstatic const unsigned SubRegIndexLaneMaskTable[] = {\n ~0u,\n";
1068 for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) {
1069 OS << format(" 0x%08x, // ", SubRegIndices[i]->LaneMask)
1070 << SubRegIndices[i]->getName() << '\n';
1076 // Now that all of the structs have been emitted, emit the instances.
1077 if (!RegisterClasses.empty()) {
1078 OS << "\nstatic const TargetRegisterClass *const "
1079 << "NullRegClasses[] = { nullptr };\n\n";
1081 // Emit register class bit mask tables. The first bit mask emitted for a
1082 // register class, RC, is the set of sub-classes, including RC itself.
1084 // If RC has super-registers, also create a list of subreg indices and bit
1085 // masks, (Idx, Mask). The bit mask has a bit for every superreg regclass,
1086 // SuperRC, that satisfies:
1088 // For all SuperReg in SuperRC: SuperReg:Idx in RC
1090 // The 0-terminated list of subreg indices starts at:
1092 // RC->getSuperRegIndices() = SuperRegIdxSeqs + ...
1094 // The corresponding bitmasks follow the sub-class mask in memory. Each
1095 // mask has RCMaskWords uint32_t entries.
1097 // Every bit mask present in the list has at least one bit set.
1099 // Compress the sub-reg index lists.
1100 typedef std::vector<const CodeGenSubRegIndex*> IdxList;
1101 SmallVector<IdxList, 8> SuperRegIdxLists(RegisterClasses.size());
1102 SequenceToOffsetTable<IdxList, CodeGenSubRegIndex::Less> SuperRegIdxSeqs;
1103 BitVector MaskBV(RegisterClasses.size());
1105 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
1106 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
1107 OS << "static const uint32_t " << RC.getName() << "SubClassMask[] = {\n ";
1108 printBitVectorAsHex(OS, RC.getSubClasses(), 32);
1110 // Emit super-reg class masks for any relevant SubRegIndices that can
1112 IdxList &SRIList = SuperRegIdxLists[rc];
1113 for (unsigned sri = 0, sre = SubRegIndices.size(); sri != sre; ++sri) {
1114 CodeGenSubRegIndex *Idx = SubRegIndices[sri];
1116 RC.getSuperRegClasses(Idx, MaskBV);
1119 SRIList.push_back(Idx);
1121 printBitVectorAsHex(OS, MaskBV, 32);
1122 OS << "// " << Idx->getName();
1124 SuperRegIdxSeqs.add(SRIList);
1128 OS << "static const uint16_t SuperRegIdxSeqs[] = {\n";
1129 SuperRegIdxSeqs.layout();
1130 SuperRegIdxSeqs.emit(OS, printSubRegIndex);
1133 // Emit NULL terminated super-class lists.
1134 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
1135 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
1136 ArrayRef<CodeGenRegisterClass*> Supers = RC.getSuperClasses();
1138 // Skip classes without supers. We can reuse NullRegClasses.
1142 OS << "static const TargetRegisterClass *const "
1143 << RC.getName() << "Superclasses[] = {\n";
1144 for (unsigned i = 0; i != Supers.size(); ++i)
1145 OS << " &" << Supers[i]->getQualifiedName() << "RegClass,\n";
1146 OS << " nullptr\n};\n\n";
1150 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
1151 const CodeGenRegisterClass &RC = *RegisterClasses[i];
1152 if (!RC.AltOrderSelect.empty()) {
1153 OS << "\nstatic inline unsigned " << RC.getName()
1154 << "AltOrderSelect(const MachineFunction &MF) {"
1155 << RC.AltOrderSelect << "}\n\n"
1156 << "static ArrayRef<MCPhysReg> " << RC.getName()
1157 << "GetRawAllocationOrder(const MachineFunction &MF) {\n";
1158 for (unsigned oi = 1 , oe = RC.getNumOrders(); oi != oe; ++oi) {
1159 ArrayRef<Record*> Elems = RC.getOrder(oi);
1160 if (!Elems.empty()) {
1161 OS << " static const MCPhysReg AltOrder" << oi << "[] = {";
1162 for (unsigned elem = 0; elem != Elems.size(); ++elem)
1163 OS << (elem ? ", " : " ") << getQualifiedName(Elems[elem]);
1167 OS << " const MCRegisterClass &MCR = " << Target.getName()
1168 << "MCRegisterClasses[" << RC.getQualifiedName() + "RegClassID];\n"
1169 << " const ArrayRef<MCPhysReg> Order[] = {\n"
1170 << " makeArrayRef(MCR.begin(), MCR.getNumRegs()";
1171 for (unsigned oi = 1, oe = RC.getNumOrders(); oi != oe; ++oi)
1172 if (RC.getOrder(oi).empty())
1173 OS << "),\n ArrayRef<MCPhysReg>(";
1175 OS << "),\n makeArrayRef(AltOrder" << oi;
1176 OS << ")\n };\n const unsigned Select = " << RC.getName()
1177 << "AltOrderSelect(MF);\n assert(Select < " << RC.getNumOrders()
1178 << ");\n return Order[Select];\n}\n";
1182 // Now emit the actual value-initialized register class instances.
1183 OS << "\nnamespace " << RegisterClasses[0]->Namespace
1184 << " { // Register class instances\n";
1186 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
1187 const CodeGenRegisterClass &RC = *RegisterClasses[i];
1188 OS << " extern const TargetRegisterClass "
1189 << RegisterClasses[i]->getName() << "RegClass = {\n "
1190 << '&' << Target.getName() << "MCRegisterClasses[" << RC.getName()
1191 << "RegClassID],\n "
1192 << "VTLists + " << VTSeqs.get(RC.VTs) << ",\n "
1193 << RC.getName() << "SubClassMask,\n SuperRegIdxSeqs + "
1194 << SuperRegIdxSeqs.get(SuperRegIdxLists[i]) << ",\n ";
1195 if (RC.getSuperClasses().empty())
1196 OS << "NullRegClasses,\n ";
1198 OS << RC.getName() << "Superclasses,\n ";
1199 if (RC.AltOrderSelect.empty())
1202 OS << RC.getName() << "GetRawAllocationOrder\n";
1209 OS << "\nnamespace {\n";
1210 OS << " const TargetRegisterClass* const RegisterClasses[] = {\n";
1211 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i)
1212 OS << " &" << RegisterClasses[i]->getQualifiedName()
1215 OS << "}\n"; // End of anonymous namespace...
1217 // Emit extra information about registers.
1218 const std::string &TargetName = Target.getName();
1219 OS << "\nstatic const TargetRegisterInfoDesc "
1220 << TargetName << "RegInfoDesc[] = { // Extra Descriptors\n";
1221 OS << " { 0, 0 },\n";
1223 const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters();
1224 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
1225 const CodeGenRegister &Reg = *Regs[i];
1227 OS << Reg.CostPerUse << ", "
1228 << int(AllocatableRegs.count(Reg.TheDef)) << " },\n";
1230 OS << "};\n"; // End of register descriptors...
1233 std::string ClassName = Target.getName() + "GenRegisterInfo";
1235 if (!SubRegIndices.empty())
1236 emitComposeSubRegIndices(OS, RegBank, ClassName);
1238 // Emit getSubClassWithSubReg.
1239 if (!SubRegIndices.empty()) {
1240 OS << "const TargetRegisterClass *" << ClassName
1241 << "::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx)"
1243 // Use the smallest type that can hold a regclass ID with room for a
1245 if (RegisterClasses.size() < UINT8_MAX)
1246 OS << " static const uint8_t Table[";
1247 else if (RegisterClasses.size() < UINT16_MAX)
1248 OS << " static const uint16_t Table[";
1250 PrintFatalError("Too many register classes.");
1251 OS << RegisterClasses.size() << "][" << SubRegIndices.size() << "] = {\n";
1252 for (unsigned rci = 0, rce = RegisterClasses.size(); rci != rce; ++rci) {
1253 const CodeGenRegisterClass &RC = *RegisterClasses[rci];
1254 OS << " {\t// " << RC.getName() << "\n";
1255 for (unsigned sri = 0, sre = SubRegIndices.size(); sri != sre; ++sri) {
1256 CodeGenSubRegIndex *Idx = SubRegIndices[sri];
1257 if (CodeGenRegisterClass *SRC = RC.getSubClassWithSubReg(Idx))
1258 OS << " " << SRC->EnumValue + 1 << ",\t// " << Idx->getName()
1259 << " -> " << SRC->getName() << "\n";
1261 OS << " 0,\t// " << Idx->getName() << "\n";
1265 OS << " };\n assert(RC && \"Missing regclass\");\n"
1266 << " if (!Idx) return RC;\n --Idx;\n"
1267 << " assert(Idx < " << SubRegIndices.size() << " && \"Bad subreg\");\n"
1268 << " unsigned TV = Table[RC->getID()][Idx];\n"
1269 << " return TV ? getRegClass(TV - 1) : nullptr;\n}\n\n";
1272 EmitRegUnitPressure(OS, RegBank, ClassName);
1274 // Emit the constructor of the class...
1275 OS << "extern const MCRegisterDesc " << TargetName << "RegDesc[];\n";
1276 OS << "extern const MCPhysReg " << TargetName << "RegDiffLists[];\n";
1277 OS << "extern const char " << TargetName << "RegStrings[];\n";
1278 OS << "extern const char " << TargetName << "RegClassStrings[];\n";
1279 OS << "extern const MCPhysReg " << TargetName << "RegUnitRoots[][2];\n";
1280 OS << "extern const uint16_t " << TargetName << "SubRegIdxLists[];\n";
1281 OS << "extern const MCRegisterInfo::SubRegCoveredBits "
1282 << TargetName << "SubRegIdxRanges[];\n";
1283 OS << "extern const uint16_t " << TargetName << "RegEncodingTable[];\n";
1285 EmitRegMappingTables(OS, Regs, true);
1287 OS << ClassName << "::\n" << ClassName
1288 << "(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour, unsigned PC)\n"
1289 << " : TargetRegisterInfo(" << TargetName << "RegInfoDesc"
1290 << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n"
1291 << " SubRegIndexNameTable, SubRegIndexLaneMaskTable, 0x";
1292 OS.write_hex(RegBank.CoveringLanes);
1294 << " InitMCRegisterInfo(" << TargetName << "RegDesc, "
1295 << Regs.size()+1 << ", RA, PC,\n " << TargetName
1296 << "MCRegisterClasses, " << RegisterClasses.size() << ",\n"
1297 << " " << TargetName << "RegUnitRoots,\n"
1298 << " " << RegBank.getNumNativeRegUnits() << ",\n"
1299 << " " << TargetName << "RegDiffLists,\n"
1300 << " " << TargetName << "RegStrings,\n"
1301 << " " << TargetName << "RegClassStrings,\n"
1302 << " " << TargetName << "SubRegIdxLists,\n"
1303 << " " << SubRegIndices.size() + 1 << ",\n"
1304 << " " << TargetName << "SubRegIdxRanges,\n"
1305 << " " << TargetName << "RegEncodingTable);\n\n";
1307 EmitRegMapping(OS, Regs, true);
1312 // Emit CalleeSavedRegs information.
1313 std::vector<Record*> CSRSets =
1314 Records.getAllDerivedDefinitions("CalleeSavedRegs");
1315 for (unsigned i = 0, e = CSRSets.size(); i != e; ++i) {
1316 Record *CSRSet = CSRSets[i];
1317 const SetTheory::RecVec *Regs = RegBank.getSets().expand(CSRSet);
1318 assert(Regs && "Cannot expand CalleeSavedRegs instance");
1320 // Emit the *_SaveList list of callee-saved registers.
1321 OS << "static const MCPhysReg " << CSRSet->getName()
1322 << "_SaveList[] = { ";
1323 for (unsigned r = 0, re = Regs->size(); r != re; ++r)
1324 OS << getQualifiedName((*Regs)[r]) << ", ";
1327 // Emit the *_RegMask bit mask of call-preserved registers.
1328 BitVector Covered = RegBank.computeCoveredRegisters(*Regs);
1330 // Check for an optional OtherPreserved set.
1331 // Add those registers to RegMask, but not to SaveList.
1332 if (DagInit *OPDag =
1333 dyn_cast<DagInit>(CSRSet->getValueInit("OtherPreserved"))) {
1334 SetTheory::RecSet OPSet;
1335 RegBank.getSets().evaluate(OPDag, OPSet, CSRSet->getLoc());
1336 Covered |= RegBank.computeCoveredRegisters(
1337 ArrayRef<Record*>(OPSet.begin(), OPSet.end()));
1340 OS << "static const uint32_t " << CSRSet->getName()
1341 << "_RegMask[] = { ";
1342 printBitVectorAsHex(OS, Covered, 32);
1347 OS << "} // End llvm namespace\n";
1348 OS << "#endif // GET_REGINFO_TARGET_DESC\n\n";
1351 void RegisterInfoEmitter::run(raw_ostream &OS) {
1352 CodeGenTarget Target(Records);
1353 CodeGenRegBank &RegBank = Target.getRegBank();
1354 RegBank.computeDerivedInfo();
1356 runEnums(OS, Target, RegBank);
1357 runMCDesc(OS, Target, RegBank);
1358 runTargetHeader(OS, Target, RegBank);
1359 runTargetDesc(OS, Target, RegBank);
1364 void EmitRegisterInfo(RecordKeeper &RK, raw_ostream &OS) {
1365 RegisterInfoEmitter(RK).run(OS);
1368 } // End llvm namespace