1 //===- RegisterInfoEmitter.cpp - Generate a Register File Desc. -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend is responsible for emitting a description of a target
11 // register file for a code generator. It uses instances of the Register,
12 // RegisterAliases, and RegisterClass classes to gather this information.
14 //===----------------------------------------------------------------------===//
16 #include "RegisterInfoEmitter.h"
17 #include "CodeGenTarget.h"
18 #include "CodeGenRegisters.h"
20 #include "llvm/ADT/StringExtras.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/Support/Streams.h"
26 // runEnums - Print out enum values for all of the registers.
27 void RegisterInfoEmitter::runEnums(std::ostream &OS) {
29 const std::vector<CodeGenRegister> &Registers = Target.getRegisters();
31 std::string Namespace = Registers[0].TheDef->getValueAsString("Namespace");
33 EmitSourceFileHeader("Target Register Enum Values", OS);
34 OS << "namespace llvm {\n\n";
36 if (!Namespace.empty())
37 OS << "namespace " << Namespace << " {\n";
38 OS << " enum {\n NoRegister,\n";
40 for (unsigned i = 0, e = Registers.size(); i != e; ++i)
41 OS << " " << Registers[i].getName() << ", \t// " << i+1 << "\n";
42 OS << " NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n";
44 if (!Namespace.empty())
46 OS << "} // End llvm namespace \n";
49 void RegisterInfoEmitter::runHeader(std::ostream &OS) {
50 EmitSourceFileHeader("Register Information Header Fragment", OS);
52 const std::string &TargetName = Target.getName();
53 std::string ClassName = TargetName + "GenRegisterInfo";
55 OS << "#include \"llvm/Target/MRegisterInfo.h\"\n";
56 OS << "#include <string>\n\n";
58 OS << "namespace llvm {\n\n";
60 OS << "struct " << ClassName << " : public MRegisterInfo {\n"
62 << "(int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);\n"
63 << " int getDwarfRegNum(unsigned RegNum) const;\n"
66 const std::vector<CodeGenRegisterClass> &RegisterClasses =
67 Target.getRegisterClasses();
69 if (!RegisterClasses.empty()) {
70 OS << "namespace " << RegisterClasses[0].Namespace
71 << " { // Register classes\n";
74 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
76 OS << " " << RegisterClasses[i].getName() << "RegClassID";
81 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
82 const std::string &Name = RegisterClasses[i].getName();
84 // Output the register class definition.
85 OS << " struct " << Name << "Class : public TargetRegisterClass {\n"
86 << " " << Name << "Class();\n"
87 << RegisterClasses[i].MethodProtos << " };\n";
89 // Output the extern for the instance.
90 OS << " extern " << Name << "Class\t" << Name << "RegClass;\n";
91 // Output the extern for the pointer to the instance (should remove).
92 OS << " static TargetRegisterClass * const "<< Name <<"RegisterClass = &"
93 << Name << "RegClass;\n";
95 OS << "} // end of namespace " << TargetName << "\n\n";
97 OS << "} // End llvm namespace \n";
100 bool isSubRegisterClass(const CodeGenRegisterClass &RC,
101 std::set<Record*> &RegSet) {
102 for (unsigned i = 0, e = RC.Elements.size(); i != e; ++i) {
103 Record *Reg = RC.Elements[i];
104 if (!RegSet.count(Reg))
110 static void addSuperReg(Record *R, Record *S,
111 std::map<Record*, std::set<Record*> > &SubRegs,
112 std::map<Record*, std::set<Record*> > &SuperRegs,
113 std::map<Record*, std::set<Record*> > &Aliases,
114 RegisterInfoEmitter &RIE) {
116 cerr << "Error: recursive sub-register relationship between"
117 << " register " << RIE.getQualifiedName(R)
118 << " and its sub-registers?\n";
121 if (!SuperRegs[R].insert(S).second)
123 SubRegs[S].insert(R);
124 Aliases[R].insert(S);
125 Aliases[S].insert(R);
126 if (SuperRegs.count(S))
127 for (std::set<Record*>::iterator I = SuperRegs[S].begin(),
128 E = SuperRegs[S].end(); I != E; ++I)
129 addSuperReg(R, *I, SubRegs, SuperRegs, Aliases, RIE);
132 static void addSubSuperReg(Record *R, Record *S,
133 std::map<Record*, std::set<Record*> > &SubRegs,
134 std::map<Record*, std::set<Record*> > &SuperRegs,
135 std::map<Record*, std::set<Record*> > &Aliases,
136 RegisterInfoEmitter &RIE) {
138 cerr << "Error: recursive sub-register relationship between"
139 << " register " << RIE.getQualifiedName(R)
140 << " and its sub-registers?\n";
144 if (!SubRegs[R].insert(S).second)
146 addSuperReg(S, R, SubRegs, SuperRegs, Aliases, RIE);
147 Aliases[R].insert(S);
148 Aliases[S].insert(R);
149 if (SubRegs.count(S))
150 for (std::set<Record*>::iterator I = SubRegs[S].begin(),
151 E = SubRegs[S].end(); I != E; ++I)
152 addSubSuperReg(R, *I, SubRegs, SuperRegs, Aliases, RIE);
155 // RegisterInfoEmitter::run - Main register file description emitter.
157 void RegisterInfoEmitter::run(std::ostream &OS) {
158 CodeGenTarget Target;
159 EmitSourceFileHeader("Register Information Source Fragment", OS);
161 OS << "namespace llvm {\n\n";
163 // Start out by emitting each of the register classes... to do this, we build
164 // a set of registers which belong to a register class, this is to ensure that
165 // each register is only in a single register class.
167 const std::vector<CodeGenRegisterClass> &RegisterClasses =
168 Target.getRegisterClasses();
170 // Loop over all of the register classes... emitting each one.
171 OS << "namespace { // Register classes...\n";
173 // RegClassesBelongedTo - Keep track of which register classes each reg
175 std::multimap<Record*, const CodeGenRegisterClass*> RegClassesBelongedTo;
177 // Emit the register enum value arrays for each RegisterClass
178 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
179 const CodeGenRegisterClass &RC = RegisterClasses[rc];
181 // Give the register class a legal C name if it's anonymous.
182 std::string Name = RC.TheDef->getName();
184 // Emit the register list now.
185 OS << " // " << Name << " Register Class...\n"
186 << " static const unsigned " << Name
188 for (unsigned i = 0, e = RC.Elements.size(); i != e; ++i) {
189 Record *Reg = RC.Elements[i];
190 OS << getQualifiedName(Reg) << ", ";
192 // Keep track of which regclasses this register is in.
193 RegClassesBelongedTo.insert(std::make_pair(Reg, &RC));
198 // Emit the ValueType arrays for each RegisterClass
199 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
200 const CodeGenRegisterClass &RC = RegisterClasses[rc];
202 // Give the register class a legal C name if it's anonymous.
203 std::string Name = RC.TheDef->getName() + "VTs";
205 // Emit the register list now.
207 << " Register Class Value Types...\n"
208 << " static const MVT::ValueType " << Name
210 for (unsigned i = 0, e = RC.VTs.size(); i != e; ++i)
211 OS << RC.VTs[i] << ", ";
212 OS << "MVT::Other\n };\n\n";
214 OS << "} // end anonymous namespace\n\n";
216 // Now that all of the structs have been emitted, emit the instances.
217 if (!RegisterClasses.empty()) {
218 OS << "namespace " << RegisterClasses[0].Namespace
219 << " { // Register class instances\n";
220 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i)
221 OS << " " << RegisterClasses[i].getName() << "Class\t"
222 << RegisterClasses[i].getName() << "RegClass;\n";
224 std::map<unsigned, std::set<unsigned> > SuperClassMap;
226 // Emit the sub-classes array for each RegisterClass
227 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
228 const CodeGenRegisterClass &RC = RegisterClasses[rc];
230 // Give the register class a legal C name if it's anonymous.
231 std::string Name = RC.TheDef->getName();
233 std::set<Record*> RegSet;
234 for (unsigned i = 0, e = RC.Elements.size(); i != e; ++i) {
235 Record *Reg = RC.Elements[i];
240 << " Register Class sub-classes...\n"
241 << " static const TargetRegisterClass* const "
242 << Name << "Subclasses [] = {\n ";
245 for (unsigned rc2 = 0, e2 = RegisterClasses.size(); rc2 != e2; ++rc2) {
246 const CodeGenRegisterClass &RC2 = RegisterClasses[rc2];
247 if (rc == rc2 || RC2.Elements.size() > RC.Elements.size() ||
248 RC.SpillSize != RC2.SpillSize || !isSubRegisterClass(RC2, RegSet))
251 if (!Empty) OS << ", ";
252 OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
255 std::map<unsigned, std::set<unsigned> >::iterator SCMI =
256 SuperClassMap.find(rc2);
257 if (SCMI == SuperClassMap.end()) {
258 SuperClassMap.insert(std::make_pair(rc2, std::set<unsigned>()));
259 SCMI = SuperClassMap.find(rc2);
261 SCMI->second.insert(rc);
264 OS << (!Empty ? ", " : "") << "NULL";
268 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
269 const CodeGenRegisterClass &RC = RegisterClasses[rc];
271 // Give the register class a legal C name if it's anonymous.
272 std::string Name = RC.TheDef->getName();
275 << " Register Class super-classes...\n"
276 << " static const TargetRegisterClass* const "
277 << Name << "Superclasses [] = {\n ";
280 std::map<unsigned, std::set<unsigned> >::iterator I =
281 SuperClassMap.find(rc);
282 if (I != SuperClassMap.end()) {
283 for (std::set<unsigned>::iterator II = I->second.begin(),
284 EE = I->second.end(); II != EE; ++II) {
285 const CodeGenRegisterClass &RC2 = RegisterClasses[*II];
286 if (!Empty) OS << ", ";
287 OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
292 OS << (!Empty ? ", " : "") << "NULL";
297 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
298 const CodeGenRegisterClass &RC = RegisterClasses[i];
299 OS << RC.MethodBodies << "\n";
300 OS << RC.getName() << "Class::" << RC.getName()
301 << "Class() : TargetRegisterClass("
302 << RC.getName() + "RegClassID" << ", "
303 << RC.getName() + "VTs" << ", "
304 << RC.getName() + "Subclasses" << ", "
305 << RC.getName() + "Superclasses" << ", "
306 << RC.SpillSize/8 << ", "
307 << RC.SpillAlignment/8 << ", " << RC.getName() << ", "
308 << RC.getName() << " + " << RC.Elements.size() << ") {}\n";
314 OS << "\nnamespace {\n";
315 OS << " const TargetRegisterClass* const RegisterClasses[] = {\n";
316 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i)
317 OS << " &" << getQualifiedName(RegisterClasses[i].TheDef)
321 // Emit register sub-registers / super-registers, aliases...
322 std::map<Record*, std::set<Record*> > RegisterSubRegs;
323 std::map<Record*, std::set<Record*> > RegisterSuperRegs;
324 std::map<Record*, std::set<Record*> > RegisterAliases;
325 const std::vector<CodeGenRegister> &Regs = Target.getRegisters();
327 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
328 Record *R = Regs[i].TheDef;
329 std::vector<Record*> LI = Regs[i].TheDef->getValueAsListOfDefs("Aliases");
330 // Add information that R aliases all of the elements in the list... and
331 // that everything in the list aliases R.
332 for (unsigned j = 0, e = LI.size(); j != e; ++j) {
334 if (RegisterAliases[R].count(Reg))
335 cerr << "Warning: register alias between " << getQualifiedName(R)
336 << " and " << getQualifiedName(Reg)
337 << " specified multiple times!\n";
338 RegisterAliases[R].insert(Reg);
340 if (RegisterAliases[Reg].count(R))
341 cerr << "Warning: register alias between " << getQualifiedName(R)
342 << " and " << getQualifiedName(Reg)
343 << " specified multiple times!\n";
344 RegisterAliases[Reg].insert(R);
348 // Process sub-register sets.
349 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
350 Record *R = Regs[i].TheDef;
351 std::vector<Record*> LI = Regs[i].TheDef->getValueAsListOfDefs("SubRegs");
352 // Process sub-register set and add aliases information.
353 for (unsigned j = 0, e = LI.size(); j != e; ++j) {
354 Record *SubReg = LI[j];
355 if (RegisterSubRegs[R].count(SubReg))
356 cerr << "Warning: register " << getQualifiedName(SubReg)
357 << " specified as a sub-register of " << getQualifiedName(R)
358 << " multiple times!\n";
359 addSubSuperReg(R, SubReg, RegisterSubRegs, RegisterSuperRegs,
360 RegisterAliases, *this);
364 if (!RegisterAliases.empty())
365 OS << "\n\n // Register Alias Sets...\n";
367 // Emit the empty alias list
368 OS << " const unsigned Empty_AliasSet[] = { 0 };\n";
369 // Loop over all of the registers which have aliases, emitting the alias list
371 for (std::map<Record*, std::set<Record*> >::iterator
372 I = RegisterAliases.begin(), E = RegisterAliases.end(); I != E; ++I) {
373 OS << " const unsigned " << I->first->getName() << "_AliasSet[] = { ";
374 for (std::set<Record*>::iterator ASI = I->second.begin(),
375 E = I->second.end(); ASI != E; ++ASI)
376 OS << getQualifiedName(*ASI) << ", ";
380 if (!RegisterSubRegs.empty())
381 OS << "\n\n // Register Sub-registers Sets...\n";
383 // Emit the empty sub-registers list
384 OS << " const unsigned Empty_SubRegsSet[] = { 0 };\n";
385 // Loop over all of the registers which have sub-registers, emitting the
386 // sub-registers list to memory.
387 for (std::map<Record*, std::set<Record*> >::iterator
388 I = RegisterSubRegs.begin(), E = RegisterSubRegs.end(); I != E; ++I) {
389 OS << " const unsigned " << I->first->getName() << "_SubRegsSet[] = { ";
390 for (std::set<Record*>::iterator ASI = I->second.begin(),
391 E = I->second.end(); ASI != E; ++ASI)
392 OS << getQualifiedName(*ASI) << ", ";
396 if (!RegisterSuperRegs.empty())
397 OS << "\n\n // Register Super-registers Sets...\n";
399 // Emit the empty super-registers list
400 OS << " const unsigned Empty_SuperRegsSet[] = { 0 };\n";
401 // Loop over all of the registers which have super-registers, emitting the
402 // super-registers list to memory.
403 for (std::map<Record*, std::set<Record*> >::iterator
404 I = RegisterSuperRegs.begin(), E = RegisterSuperRegs.end(); I != E; ++I) {
405 OS << " const unsigned " << I->first->getName() << "_SuperRegsSet[] = { ";
406 for (std::set<Record*>::iterator ASI = I->second.begin(),
407 E = I->second.end(); ASI != E; ++ASI)
408 OS << getQualifiedName(*ASI) << ", ";
412 OS<<"\n const TargetRegisterDesc RegisterDescriptors[] = { // Descriptors\n";
413 OS << " { \"NOREG\",\t0,\t0,\t0 },\n";
415 // Now that register alias and sub-registers sets have been emitted, emit the
416 // register descriptors now.
417 const std::vector<CodeGenRegister> &Registers = Target.getRegisters();
418 for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
419 const CodeGenRegister &Reg = Registers[i];
421 if (!Reg.TheDef->getValueAsString("Name").empty())
422 OS << Reg.TheDef->getValueAsString("Name");
426 if (RegisterAliases.count(Reg.TheDef))
427 OS << Reg.getName() << "_AliasSet,\t";
429 OS << "Empty_AliasSet,\t";
430 if (RegisterSubRegs.count(Reg.TheDef))
431 OS << Reg.getName() << "_SubRegsSet,\t";
433 OS << "Empty_SubRegsSet,\t";
434 if (RegisterSuperRegs.count(Reg.TheDef))
435 OS << Reg.getName() << "_SuperRegsSet },\n";
437 OS << "Empty_SuperRegsSet },\n";
439 OS << " };\n"; // End of register descriptors...
440 OS << "}\n\n"; // End of anonymous namespace...
442 std::string ClassName = Target.getName() + "GenRegisterInfo";
444 // Emit the constructor of the class...
445 OS << ClassName << "::" << ClassName
446 << "(int CallFrameSetupOpcode, int CallFrameDestroyOpcode)\n"
447 << " : MRegisterInfo(RegisterDescriptors, " << Registers.size()+1
448 << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n "
449 << " CallFrameSetupOpcode, CallFrameDestroyOpcode) {}\n\n";
451 // Emit information about the dwarf register numbers.
452 OS << "int " << ClassName << "::getDwarfRegNum(unsigned RegNum) const {\n";
453 OS << " static const int DwarfRegNums[] = { -1, // NoRegister";
454 for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
455 if (!(i % 16)) OS << "\n ";
456 const CodeGenRegister &Reg = Registers[i];
457 int DwarfRegNum = Reg.TheDef->getValueAsInt("DwarfNumber");
459 if ((i + 1) != e) OS << ", ";
462 OS << " assert(RegNum < (sizeof(DwarfRegNums)/sizeof(int)) &&\n";
463 OS << " \"RegNum exceeds number of registers\");\n";
464 OS << " return DwarfRegNums[RegNum];\n";
467 OS << "} // End llvm namespace \n";