1 //===- RegisterInfoEmitter.cpp - Generate a Register File Desc. -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend is responsible for emitting a description of a target
11 // register file for a code generator. It uses instances of the Register,
12 // RegisterAliases, and RegisterClass classes to gather this information.
14 //===----------------------------------------------------------------------===//
16 #include "CodeGenRegisters.h"
17 #include "CodeGenTarget.h"
18 #include "SequenceToOffsetTable.h"
19 #include "llvm/ADT/BitVector.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/StringExtras.h"
22 #include "llvm/ADT/Twine.h"
23 #include "llvm/Support/Format.h"
24 #include "llvm/TableGen/Error.h"
25 #include "llvm/TableGen/Record.h"
26 #include "llvm/TableGen/TableGenBackend.h"
33 class RegisterInfoEmitter {
34 RecordKeeper &Records;
36 RegisterInfoEmitter(RecordKeeper &R) : Records(R) {}
38 // runEnums - Print out enum values for all of the registers.
39 void runEnums(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank);
41 // runMCDesc - Print out MC register descriptions.
42 void runMCDesc(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank);
44 // runTargetHeader - Emit a header fragment for the register info emitter.
45 void runTargetHeader(raw_ostream &o, CodeGenTarget &Target,
46 CodeGenRegBank &Bank);
48 // runTargetDesc - Output the target register and register file descriptions.
49 void runTargetDesc(raw_ostream &o, CodeGenTarget &Target,
50 CodeGenRegBank &Bank);
52 // run - Output the register file description.
53 void run(raw_ostream &o);
56 void EmitRegMapping(raw_ostream &o,
57 const std::vector<CodeGenRegister*> &Regs, bool isCtor);
58 void EmitRegMappingTables(raw_ostream &o,
59 const std::vector<CodeGenRegister*> &Regs,
61 void EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank,
62 const std::string &ClassName);
63 void emitComposeSubRegIndices(raw_ostream &OS, CodeGenRegBank &RegBank,
64 const std::string &ClassName);
66 } // End anonymous namespace
68 // runEnums - Print out enum values for all of the registers.
69 void RegisterInfoEmitter::runEnums(raw_ostream &OS,
70 CodeGenTarget &Target, CodeGenRegBank &Bank) {
71 const std::vector<CodeGenRegister*> &Registers = Bank.getRegisters();
73 // Register enums are stored as uint16_t in the tables. Make sure we'll fit.
74 assert(Registers.size() <= 0xffff && "Too many regs to fit in tables");
76 std::string Namespace = Registers[0]->TheDef->getValueAsString("Namespace");
78 emitSourceFileHeader("Target Register Enum Values", OS);
80 OS << "\n#ifdef GET_REGINFO_ENUM\n";
81 OS << "#undef GET_REGINFO_ENUM\n";
83 OS << "namespace llvm {\n\n";
85 OS << "class MCRegisterClass;\n"
86 << "extern const MCRegisterClass " << Namespace
87 << "MCRegisterClasses[];\n\n";
89 if (!Namespace.empty())
90 OS << "namespace " << Namespace << " {\n";
91 OS << "enum {\n NoRegister,\n";
93 for (unsigned i = 0, e = Registers.size(); i != e; ++i)
94 OS << " " << Registers[i]->getName() << " = " <<
95 Registers[i]->EnumValue << ",\n";
96 assert(Registers.size() == Registers[Registers.size()-1]->EnumValue &&
97 "Register enum value mismatch!");
98 OS << " NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n";
100 if (!Namespace.empty())
103 ArrayRef<CodeGenRegisterClass*> RegisterClasses = Bank.getRegClasses();
104 if (!RegisterClasses.empty()) {
106 // RegisterClass enums are stored as uint16_t in the tables.
107 assert(RegisterClasses.size() <= 0xffff &&
108 "Too many register classes to fit in tables");
110 OS << "\n// Register classes\n";
111 if (!Namespace.empty())
112 OS << "namespace " << Namespace << " {\n";
114 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
116 OS << " " << RegisterClasses[i]->getName() << "RegClassID";
120 if (!Namespace.empty())
124 const std::vector<Record*> &RegAltNameIndices = Target.getRegAltNameIndices();
125 // If the only definition is the default NoRegAltName, we don't need to
127 if (RegAltNameIndices.size() > 1) {
128 OS << "\n// Register alternate name indices\n";
129 if (!Namespace.empty())
130 OS << "namespace " << Namespace << " {\n";
132 for (unsigned i = 0, e = RegAltNameIndices.size(); i != e; ++i)
133 OS << " " << RegAltNameIndices[i]->getName() << ",\t// " << i << "\n";
134 OS << " NUM_TARGET_REG_ALT_NAMES = " << RegAltNameIndices.size() << "\n";
136 if (!Namespace.empty())
140 ArrayRef<CodeGenSubRegIndex*> SubRegIndices = Bank.getSubRegIndices();
141 if (!SubRegIndices.empty()) {
142 OS << "\n// Subregister indices\n";
143 std::string Namespace =
144 SubRegIndices[0]->getNamespace();
145 if (!Namespace.empty())
146 OS << "namespace " << Namespace << " {\n";
147 OS << "enum {\n NoSubRegister,\n";
148 for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i)
149 OS << " " << SubRegIndices[i]->getName() << ",\t// " << i+1 << "\n";
150 OS << " NUM_TARGET_SUBREGS\n};\n";
151 if (!Namespace.empty())
155 OS << "} // End llvm namespace\n";
156 OS << "#endif // GET_REGINFO_ENUM\n\n";
159 void RegisterInfoEmitter::
160 EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank,
161 const std::string &ClassName) {
162 unsigned NumRCs = RegBank.getRegClasses().size();
163 unsigned NumSets = RegBank.getNumRegPressureSets();
165 OS << "/// Get the weight in units of pressure for this register class.\n"
166 << "const RegClassWeight &" << ClassName << "::\n"
167 << "getRegClassWeight(const TargetRegisterClass *RC) const {\n"
168 << " static const RegClassWeight RCWeightTable[] = {\n";
169 for (unsigned i = 0, e = NumRCs; i != e; ++i) {
170 const CodeGenRegisterClass &RC = *RegBank.getRegClasses()[i];
171 const CodeGenRegister::Set &Regs = RC.getMembers();
175 std::vector<unsigned> RegUnits;
176 RC.buildRegUnitSet(RegUnits);
177 OS << " {" << (*Regs.begin())->getWeight(RegBank)
178 << ", " << RegBank.getRegUnitSetWeight(RegUnits);
180 OS << "}, \t// " << RC.getName() << "\n";
183 << " return RCWeightTable[RC->getID()];\n"
186 // Reasonable targets (not ARMv7) have unit weight for all units, so don't
187 // bother generating a table.
188 bool RegUnitsHaveUnitWeight = true;
189 for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits();
190 UnitIdx < UnitEnd; ++UnitIdx) {
191 if (RegBank.getRegUnit(UnitIdx).Weight > 1)
192 RegUnitsHaveUnitWeight = false;
194 OS << "/// Get the weight in units of pressure for this register unit.\n"
195 << "unsigned " << ClassName << "::\n"
196 << "getRegUnitWeight(unsigned RegUnit) const {\n"
197 << " assert(RegUnit < " << RegBank.getNumNativeRegUnits()
198 << " && \"invalid register unit\");\n";
199 if (!RegUnitsHaveUnitWeight) {
200 OS << " static const uint8_t RUWeightTable[] = {\n ";
201 for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits();
202 UnitIdx < UnitEnd; ++UnitIdx) {
203 const RegUnit &RU = RegBank.getRegUnit(UnitIdx);
204 assert(RU.Weight < 256 && "RegUnit too heavy");
205 OS << RU.Weight << ", ";
208 << " return RUWeightTable[RegUnit];\n";
211 OS << " // All register units have unit weight.\n"
217 << "// Get the number of dimensions of register pressure.\n"
218 << "unsigned " << ClassName << "::getNumRegPressureSets() const {\n"
219 << " return " << NumSets << ";\n}\n\n";
221 OS << "// Get the name of this register unit pressure set.\n"
222 << "const char *" << ClassName << "::\n"
223 << "getRegPressureSetName(unsigned Idx) const {\n"
224 << " static const char *PressureNameTable[] = {\n";
225 for (unsigned i = 0; i < NumSets; ++i ) {
226 OS << " \"" << RegBank.getRegSetAt(i).Name << "\",\n";
228 OS << " nullptr };\n"
229 << " return PressureNameTable[Idx];\n"
232 OS << "// Get the register unit pressure limit for this dimension.\n"
233 << "// This limit must be adjusted dynamically for reserved registers.\n"
234 << "unsigned " << ClassName << "::\n"
235 << "getRegPressureSetLimit(unsigned Idx) const {\n"
236 << " static const unsigned PressureLimitTable[] = {\n";
237 for (unsigned i = 0; i < NumSets; ++i ) {
238 const RegUnitSet &RegUnits = RegBank.getRegSetAt(i);
239 OS << " " << RegUnits.Weight << ", \t// " << i << ": "
240 << RegUnits.Name << "\n";
243 << " return PressureLimitTable[Idx];\n"
246 // This table may be larger than NumRCs if some register units needed a list
247 // of unit sets that did not correspond to a register class.
248 unsigned NumRCUnitSets = RegBank.getNumRegClassPressureSetLists();
249 OS << "/// Table of pressure sets per register class or unit.\n"
250 << "static const int RCSetsTable[] = {\n ";
251 std::vector<unsigned> RCSetStarts(NumRCUnitSets);
252 for (unsigned i = 0, StartIdx = 0, e = NumRCUnitSets; i != e; ++i) {
253 RCSetStarts[i] = StartIdx;
254 ArrayRef<unsigned> PSetIDs = RegBank.getRCPressureSetIDs(i);
255 std::vector<unsigned> PSets;
256 PSets.reserve(PSetIDs.size());
257 for (ArrayRef<unsigned>::iterator PSetI = PSetIDs.begin(),
258 PSetE = PSetIDs.end(); PSetI != PSetE; ++PSetI) {
259 PSets.push_back(RegBank.getRegPressureSet(*PSetI).Order);
261 std::sort(PSets.begin(), PSets.end());
262 for (unsigned j = 0, e = PSets.size(); j < e; ++j) {
263 OS << PSets[j] << ", ";
266 OS << "-1, \t// #" << RCSetStarts[i] << " ";
268 OS << RegBank.getRegClasses()[i]->getName();
271 for (ArrayRef<unsigned>::iterator PSetI = PSetIDs.begin(),
272 PSetE = PSetIDs.end(); PSetI != PSetE; ++PSetI) {
273 OS << "~" << RegBank.getRegSetAt(*PSetI).Name;
281 OS << "/// Get the dimensions of register pressure impacted by this "
282 << "register class.\n"
283 << "/// Returns a -1 terminated array of pressure set IDs\n"
284 << "const int* " << ClassName << "::\n"
285 << "getRegClassPressureSets(const TargetRegisterClass *RC) const {\n";
286 OS << " static const unsigned RCSetStartTable[] = {\n ";
287 for (unsigned i = 0, e = NumRCs; i != e; ++i) {
288 OS << RCSetStarts[i] << ",";
291 << " unsigned SetListStart = RCSetStartTable[RC->getID()];\n"
292 << " return &RCSetsTable[SetListStart];\n"
295 OS << "/// Get the dimensions of register pressure impacted by this "
296 << "register unit.\n"
297 << "/// Returns a -1 terminated array of pressure set IDs\n"
298 << "const int* " << ClassName << "::\n"
299 << "getRegUnitPressureSets(unsigned RegUnit) const {\n"
300 << " assert(RegUnit < " << RegBank.getNumNativeRegUnits()
301 << " && \"invalid register unit\");\n";
302 OS << " static const unsigned RUSetStartTable[] = {\n ";
303 for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits();
304 UnitIdx < UnitEnd; ++UnitIdx) {
305 OS << RCSetStarts[RegBank.getRegUnit(UnitIdx).RegClassUnitSetsIdx] << ",";
308 << " unsigned SetListStart = RUSetStartTable[RegUnit];\n"
309 << " return &RCSetsTable[SetListStart];\n"
314 RegisterInfoEmitter::EmitRegMappingTables(raw_ostream &OS,
315 const std::vector<CodeGenRegister*> &Regs,
317 // Collect all information about dwarf register numbers
318 typedef std::map<Record*, std::vector<int64_t>, LessRecordRegister> DwarfRegNumsMapTy;
319 DwarfRegNumsMapTy DwarfRegNums;
321 // First, just pull all provided information to the map
322 unsigned maxLength = 0;
323 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
324 Record *Reg = Regs[i]->TheDef;
325 std::vector<int64_t> RegNums = Reg->getValueAsListOfInts("DwarfNumbers");
326 maxLength = std::max((size_t)maxLength, RegNums.size());
327 if (DwarfRegNums.count(Reg))
328 PrintWarning(Reg->getLoc(), Twine("DWARF numbers for register ") +
329 getQualifiedName(Reg) + "specified multiple times");
330 DwarfRegNums[Reg] = RegNums;
336 // Now we know maximal length of number list. Append -1's, where needed
337 for (DwarfRegNumsMapTy::iterator
338 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I)
339 for (unsigned i = I->second.size(), e = maxLength; i != e; ++i)
340 I->second.push_back(-1);
342 std::string Namespace = Regs[0]->TheDef->getValueAsString("Namespace");
344 OS << "// " << Namespace << " Dwarf<->LLVM register mappings.\n";
346 // Emit reverse information about the dwarf register numbers.
347 for (unsigned j = 0; j < 2; ++j) {
348 for (unsigned i = 0, e = maxLength; i != e; ++i) {
349 OS << "extern const MCRegisterInfo::DwarfLLVMRegPair " << Namespace;
350 OS << (j == 0 ? "DwarfFlavour" : "EHFlavour");
351 OS << i << "Dwarf2L[]";
356 // Store the mapping sorted by the LLVM reg num so lookup can be done
357 // with a binary search.
358 std::map<uint64_t, Record*> Dwarf2LMap;
359 for (DwarfRegNumsMapTy::iterator
360 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
361 int DwarfRegNo = I->second[i];
364 Dwarf2LMap[DwarfRegNo] = I->first;
367 for (std::map<uint64_t, Record*>::iterator
368 I = Dwarf2LMap.begin(), E = Dwarf2LMap.end(); I != E; ++I)
369 OS << " { " << I->first << "U, " << getQualifiedName(I->second)
377 // We have to store the size in a const global, it's used in multiple
379 OS << "extern const unsigned " << Namespace
380 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i << "Dwarf2LSize";
382 OS << " = array_lengthof(" << Namespace
383 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i
390 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
391 Record *Reg = Regs[i]->TheDef;
392 const RecordVal *V = Reg->getValue("DwarfAlias");
393 if (!V || !V->getValue())
396 DefInit *DI = cast<DefInit>(V->getValue());
397 Record *Alias = DI->getDef();
398 DwarfRegNums[Reg] = DwarfRegNums[Alias];
401 // Emit information about the dwarf register numbers.
402 for (unsigned j = 0; j < 2; ++j) {
403 for (unsigned i = 0, e = maxLength; i != e; ++i) {
404 OS << "extern const MCRegisterInfo::DwarfLLVMRegPair " << Namespace;
405 OS << (j == 0 ? "DwarfFlavour" : "EHFlavour");
406 OS << i << "L2Dwarf[]";
409 // Store the mapping sorted by the Dwarf reg num so lookup can be done
410 // with a binary search.
411 for (DwarfRegNumsMapTy::iterator
412 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
413 int RegNo = I->second[i];
414 if (RegNo == -1) // -1 is the default value, don't emit a mapping.
417 OS << " { " << getQualifiedName(I->first) << ", " << RegNo
425 // We have to store the size in a const global, it's used in multiple
427 OS << "extern const unsigned " << Namespace
428 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i << "L2DwarfSize";
430 OS << " = array_lengthof(" << Namespace
431 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i << "L2Dwarf);\n\n";
439 RegisterInfoEmitter::EmitRegMapping(raw_ostream &OS,
440 const std::vector<CodeGenRegister*> &Regs,
442 // Emit the initializer so the tables from EmitRegMappingTables get wired up
443 // to the MCRegisterInfo object.
444 unsigned maxLength = 0;
445 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
446 Record *Reg = Regs[i]->TheDef;
447 maxLength = std::max((size_t)maxLength,
448 Reg->getValueAsListOfInts("DwarfNumbers").size());
454 std::string Namespace = Regs[0]->TheDef->getValueAsString("Namespace");
456 // Emit reverse information about the dwarf register numbers.
457 for (unsigned j = 0; j < 2; ++j) {
460 OS << "DwarfFlavour";
465 << " llvm_unreachable(\"Unknown DWARF flavour\");\n";
467 for (unsigned i = 0, e = maxLength; i != e; ++i) {
468 OS << " case " << i << ":\n";
473 raw_string_ostream(Tmp) << Namespace
474 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i
476 OS << "mapDwarfRegsToLLVMRegs(" << Tmp << ", " << Tmp << "Size, ";
487 // Emit information about the dwarf register numbers.
488 for (unsigned j = 0; j < 2; ++j) {
491 OS << "DwarfFlavour";
496 << " llvm_unreachable(\"Unknown DWARF flavour\");\n";
498 for (unsigned i = 0, e = maxLength; i != e; ++i) {
499 OS << " case " << i << ":\n";
504 raw_string_ostream(Tmp) << Namespace
505 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i
507 OS << "mapLLVMRegsToDwarfRegs(" << Tmp << ", " << Tmp << "Size, ";
519 // Print a BitVector as a sequence of hex numbers using a little-endian mapping.
520 // Width is the number of bits per hex number.
521 static void printBitVectorAsHex(raw_ostream &OS,
522 const BitVector &Bits,
524 assert(Width <= 32 && "Width too large");
525 unsigned Digits = (Width + 3) / 4;
526 for (unsigned i = 0, e = Bits.size(); i < e; i += Width) {
528 for (unsigned j = 0; j != Width && i + j != e; ++j)
529 Value |= Bits.test(i + j) << j;
530 OS << format("0x%0*x, ", Digits, Value);
534 // Helper to emit a set of bits into a constant byte array.
535 class BitVectorEmitter {
538 void add(unsigned v) {
539 if (v >= Values.size())
540 Values.resize(((v/8)+1)*8); // Round up to the next byte.
544 void print(raw_ostream &OS) {
545 printBitVectorAsHex(OS, Values, 8);
549 static void printSimpleValueType(raw_ostream &OS, MVT::SimpleValueType VT) {
550 OS << getEnumName(VT);
553 static void printSubRegIndex(raw_ostream &OS, const CodeGenSubRegIndex *Idx) {
554 OS << Idx->EnumValue;
557 // Differentially encoded register and regunit lists allow for better
558 // compression on regular register banks. The sequence is computed from the
559 // differential list as:
562 // out[n+1] = out[n] + diff[n]; // n = 0, 1, ...
564 // The initial value depends on the specific list. The list is terminated by a
565 // 0 differential which means we can't encode repeated elements.
567 typedef SmallVector<uint16_t, 4> DiffVec;
569 // Differentially encode a sequence of numbers into V. The starting value and
570 // terminating 0 are not added to V, so it will have the same size as List.
572 DiffVec &diffEncode(DiffVec &V, unsigned InitVal, ArrayRef<unsigned> List) {
573 assert(V.empty() && "Clear DiffVec before diffEncode.");
574 uint16_t Val = uint16_t(InitVal);
575 for (unsigned i = 0; i != List.size(); ++i) {
576 uint16_t Cur = List[i];
577 V.push_back(Cur - Val);
583 template<typename Iter>
585 DiffVec &diffEncode(DiffVec &V, unsigned InitVal, Iter Begin, Iter End) {
586 assert(V.empty() && "Clear DiffVec before diffEncode.");
587 uint16_t Val = uint16_t(InitVal);
588 for (Iter I = Begin; I != End; ++I) {
589 uint16_t Cur = (*I)->EnumValue;
590 V.push_back(Cur - Val);
596 static void printDiff16(raw_ostream &OS, uint16_t Val) {
600 // Try to combine Idx's compose map into Vec if it is compatible.
601 // Return false if it's not possible.
602 static bool combine(const CodeGenSubRegIndex *Idx,
603 SmallVectorImpl<CodeGenSubRegIndex*> &Vec) {
604 const CodeGenSubRegIndex::CompMap &Map = Idx->getComposites();
605 for (CodeGenSubRegIndex::CompMap::const_iterator
606 I = Map.begin(), E = Map.end(); I != E; ++I) {
607 CodeGenSubRegIndex *&Entry = Vec[I->first->EnumValue - 1];
608 if (Entry && Entry != I->second)
612 // All entries are compatible. Make it so.
613 for (CodeGenSubRegIndex::CompMap::const_iterator
614 I = Map.begin(), E = Map.end(); I != E; ++I)
615 Vec[I->first->EnumValue - 1] = I->second;
619 static const char *getMinimalTypeForRange(uint64_t Range) {
620 assert(Range < 0xFFFFFFFFULL && "Enum too large");
629 RegisterInfoEmitter::emitComposeSubRegIndices(raw_ostream &OS,
630 CodeGenRegBank &RegBank,
631 const std::string &ClName) {
632 ArrayRef<CodeGenSubRegIndex*> SubRegIndices = RegBank.getSubRegIndices();
633 OS << "unsigned " << ClName
634 << "::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {\n";
636 // Many sub-register indexes are composition-compatible, meaning that
638 // compose(IdxA, IdxB) == compose(IdxA', IdxB)
640 // for many IdxA, IdxA' pairs. Not all sub-register indexes can be composed.
641 // The illegal entries can be use as wildcards to compress the table further.
643 // Map each Sub-register index to a compatible table row.
644 SmallVector<unsigned, 4> RowMap;
645 SmallVector<SmallVector<CodeGenSubRegIndex*, 4>, 4> Rows;
647 for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) {
648 unsigned Found = ~0u;
649 for (unsigned r = 0, re = Rows.size(); r != re; ++r) {
650 if (combine(SubRegIndices[i], Rows[r])) {
657 Rows.resize(Found + 1);
658 Rows.back().resize(SubRegIndices.size());
659 combine(SubRegIndices[i], Rows.back());
661 RowMap.push_back(Found);
664 // Output the row map if there is multiple rows.
665 if (Rows.size() > 1) {
666 OS << " static const " << getMinimalTypeForRange(Rows.size())
667 << " RowMap[" << SubRegIndices.size() << "] = {\n ";
668 for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i)
669 OS << RowMap[i] << ", ";
674 OS << " static const " << getMinimalTypeForRange(SubRegIndices.size()+1)
675 << " Rows[" << Rows.size() << "][" << SubRegIndices.size() << "] = {\n";
676 for (unsigned r = 0, re = Rows.size(); r != re; ++r) {
678 for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i)
680 OS << Rows[r][i]->EnumValue << ", ";
687 OS << " --IdxA; assert(IdxA < " << SubRegIndices.size() << ");\n"
688 << " --IdxB; assert(IdxB < " << SubRegIndices.size() << ");\n";
690 OS << " return Rows[RowMap[IdxA]][IdxB];\n";
692 OS << " return Rows[0][IdxB];\n";
697 // runMCDesc - Print out MC register descriptions.
700 RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target,
701 CodeGenRegBank &RegBank) {
702 emitSourceFileHeader("MC Register Information", OS);
704 OS << "\n#ifdef GET_REGINFO_MC_DESC\n";
705 OS << "#undef GET_REGINFO_MC_DESC\n";
707 const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters();
709 ArrayRef<CodeGenSubRegIndex*> SubRegIndices = RegBank.getSubRegIndices();
710 // The lists of sub-registers and super-registers go in the same array. That
711 // allows us to share suffixes.
712 typedef std::vector<const CodeGenRegister*> RegVec;
714 // Differentially encoded lists.
715 SequenceToOffsetTable<DiffVec> DiffSeqs;
716 SmallVector<DiffVec, 4> SubRegLists(Regs.size());
717 SmallVector<DiffVec, 4> SuperRegLists(Regs.size());
718 SmallVector<DiffVec, 4> RegUnitLists(Regs.size());
719 SmallVector<unsigned, 4> RegUnitInitScale(Regs.size());
721 // Keep track of sub-register names as well. These are not differentially
723 typedef SmallVector<const CodeGenSubRegIndex*, 4> SubRegIdxVec;
724 SequenceToOffsetTable<SubRegIdxVec, CodeGenSubRegIndex::Less> SubRegIdxSeqs;
725 SmallVector<SubRegIdxVec, 4> SubRegIdxLists(Regs.size());
727 SequenceToOffsetTable<std::string> RegStrings;
729 // Precompute register lists for the SequenceToOffsetTable.
730 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
731 const CodeGenRegister *Reg = Regs[i];
733 RegStrings.add(Reg->getName());
735 // Compute the ordered sub-register list.
736 SetVector<const CodeGenRegister*> SR;
737 Reg->addSubRegsPreOrder(SR, RegBank);
738 diffEncode(SubRegLists[i], Reg->EnumValue, SR.begin(), SR.end());
739 DiffSeqs.add(SubRegLists[i]);
741 // Compute the corresponding sub-register indexes.
742 SubRegIdxVec &SRIs = SubRegIdxLists[i];
743 for (unsigned j = 0, je = SR.size(); j != je; ++j)
744 SRIs.push_back(Reg->getSubRegIndex(SR[j]));
745 SubRegIdxSeqs.add(SRIs);
747 // Super-registers are already computed.
748 const RegVec &SuperRegList = Reg->getSuperRegs();
749 diffEncode(SuperRegLists[i], Reg->EnumValue,
750 SuperRegList.begin(), SuperRegList.end());
751 DiffSeqs.add(SuperRegLists[i]);
753 // Differentially encode the register unit list, seeded by register number.
754 // First compute a scale factor that allows more diff-lists to be reused:
759 // A scale factor of 2 allows D0 and D1 to share a diff-list. The initial
760 // value for the differential decoder is the register number multiplied by
763 // Check the neighboring registers for arithmetic progressions.
764 unsigned ScaleA = ~0u, ScaleB = ~0u;
765 ArrayRef<unsigned> RUs = Reg->getNativeRegUnits();
766 if (i > 0 && Regs[i-1]->getNativeRegUnits().size() == RUs.size())
767 ScaleB = RUs.front() - Regs[i-1]->getNativeRegUnits().front();
768 if (i+1 != Regs.size() &&
769 Regs[i+1]->getNativeRegUnits().size() == RUs.size())
770 ScaleA = Regs[i+1]->getNativeRegUnits().front() - RUs.front();
771 unsigned Scale = std::min(ScaleB, ScaleA);
772 // Default the scale to 0 if it can't be encoded in 4 bits.
775 RegUnitInitScale[i] = Scale;
776 DiffSeqs.add(diffEncode(RegUnitLists[i], Scale * Reg->EnumValue, RUs));
779 // Compute the final layout of the sequence table.
781 SubRegIdxSeqs.layout();
783 OS << "namespace llvm {\n\n";
785 const std::string &TargetName = Target.getName();
787 // Emit the shared table of differential lists.
788 OS << "extern const MCPhysReg " << TargetName << "RegDiffLists[] = {\n";
789 DiffSeqs.emit(OS, printDiff16);
792 // Emit the table of sub-register indexes.
793 OS << "extern const uint16_t " << TargetName << "SubRegIdxLists[] = {\n";
794 SubRegIdxSeqs.emit(OS, printSubRegIndex);
797 // Emit the table of sub-register index sizes.
798 OS << "extern const MCRegisterInfo::SubRegCoveredBits "
799 << TargetName << "SubRegIdxRanges[] = {\n";
800 OS << " { " << (uint16_t)-1 << ", " << (uint16_t)-1 << " },\n";
801 for (ArrayRef<CodeGenSubRegIndex*>::const_iterator
802 SRI = SubRegIndices.begin(), SRE = SubRegIndices.end();
804 OS << " { " << (*SRI)->Offset << ", "
806 << " },\t// " << (*SRI)->getName() << "\n";
810 // Emit the string table.
812 OS << "extern const char " << TargetName << "RegStrings[] = {\n";
813 RegStrings.emit(OS, printChar);
816 OS << "extern const MCRegisterDesc " << TargetName
817 << "RegDesc[] = { // Descriptors\n";
818 OS << " { " << RegStrings.get("") << ", 0, 0, 0, 0 },\n";
820 // Emit the register descriptors now.
821 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
822 const CodeGenRegister *Reg = Regs[i];
823 OS << " { " << RegStrings.get(Reg->getName()) << ", "
824 << DiffSeqs.get(SubRegLists[i]) << ", "
825 << DiffSeqs.get(SuperRegLists[i]) << ", "
826 << SubRegIdxSeqs.get(SubRegIdxLists[i]) << ", "
827 << (DiffSeqs.get(RegUnitLists[i])*16 + RegUnitInitScale[i]) << " },\n";
829 OS << "};\n\n"; // End of register descriptors...
831 // Emit the table of register unit roots. Each regunit has one or two root
833 OS << "extern const MCPhysReg " << TargetName << "RegUnitRoots[][2] = {\n";
834 for (unsigned i = 0, e = RegBank.getNumNativeRegUnits(); i != e; ++i) {
835 ArrayRef<const CodeGenRegister*> Roots = RegBank.getRegUnit(i).getRoots();
836 assert(!Roots.empty() && "All regunits must have a root register.");
837 assert(Roots.size() <= 2 && "More than two roots not supported yet.");
838 OS << " { " << getQualifiedName(Roots.front()->TheDef);
839 for (unsigned r = 1; r != Roots.size(); ++r)
840 OS << ", " << getQualifiedName(Roots[r]->TheDef);
845 ArrayRef<CodeGenRegisterClass*> RegisterClasses = RegBank.getRegClasses();
847 // Loop over all of the register classes... emitting each one.
848 OS << "namespace { // Register classes...\n";
850 SequenceToOffsetTable<std::string> RegClassStrings;
852 // Emit the register enum value arrays for each RegisterClass
853 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
854 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
855 ArrayRef<Record*> Order = RC.getOrder();
857 // Give the register class a legal C name if it's anonymous.
858 std::string Name = RC.getName();
860 RegClassStrings.add(Name);
862 // Emit the register list now.
863 OS << " // " << Name << " Register Class...\n"
864 << " const MCPhysReg " << Name
866 for (unsigned i = 0, e = Order.size(); i != e; ++i) {
867 Record *Reg = Order[i];
868 OS << getQualifiedName(Reg) << ", ";
872 OS << " // " << Name << " Bit set.\n"
873 << " const uint8_t " << Name
875 BitVectorEmitter BVE;
876 for (unsigned i = 0, e = Order.size(); i != e; ++i) {
877 Record *Reg = Order[i];
878 BVE.add(Target.getRegBank().getReg(Reg)->EnumValue);
886 RegClassStrings.layout();
887 OS << "extern const char " << TargetName << "RegClassStrings[] = {\n";
888 RegClassStrings.emit(OS, printChar);
891 OS << "extern const MCRegisterClass " << TargetName
892 << "MCRegisterClasses[] = {\n";
894 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
895 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
897 // Asserts to make sure values will fit in table assuming types from
899 assert((RC.SpillSize/8) <= 0xffff && "SpillSize too large.");
900 assert((RC.SpillAlignment/8) <= 0xffff && "SpillAlignment too large.");
901 assert(RC.CopyCost >= -128 && RC.CopyCost <= 127 && "Copy cost too large.");
903 OS << " { " << RC.getName() << ", " << RC.getName() << "Bits, "
904 << RegClassStrings.get(RC.getName()) << ", "
905 << RC.getOrder().size() << ", sizeof(" << RC.getName() << "Bits), "
906 << RC.getQualifiedName() + "RegClassID" << ", "
907 << RC.SpillSize/8 << ", "
908 << RC.SpillAlignment/8 << ", "
909 << RC.CopyCost << ", "
910 << RC.Allocatable << " },\n";
915 EmitRegMappingTables(OS, Regs, false);
917 // Emit Reg encoding table
918 OS << "extern const uint16_t " << TargetName;
919 OS << "RegEncodingTable[] = {\n";
920 // Add entry for NoRegister
922 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
923 Record *Reg = Regs[i]->TheDef;
924 BitsInit *BI = Reg->getValueAsBitsInit("HWEncoding");
926 for (unsigned b = 0, be = BI->getNumBits(); b != be; ++b) {
927 if (BitInit *B = dyn_cast<BitInit>(BI->getBit(b)))
928 Value |= (uint64_t)B->getValue() << b;
930 OS << " " << Value << ",\n";
932 OS << "};\n"; // End of HW encoding table
934 // MCRegisterInfo initialization routine.
935 OS << "static inline void Init" << TargetName
936 << "MCRegisterInfo(MCRegisterInfo *RI, unsigned RA, "
937 << "unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {\n"
938 << " RI->InitMCRegisterInfo(" << TargetName << "RegDesc, "
939 << Regs.size()+1 << ", RA, PC, " << TargetName << "MCRegisterClasses, "
940 << RegisterClasses.size() << ", "
941 << TargetName << "RegUnitRoots, "
942 << RegBank.getNumNativeRegUnits() << ", "
943 << TargetName << "RegDiffLists, "
944 << TargetName << "RegStrings, "
945 << TargetName << "RegClassStrings, "
946 << TargetName << "SubRegIdxLists, "
947 << (SubRegIndices.size() + 1) << ",\n"
948 << TargetName << "SubRegIdxRanges, "
949 << TargetName << "RegEncodingTable);\n\n";
951 EmitRegMapping(OS, Regs, false);
955 OS << "} // End llvm namespace\n";
956 OS << "#endif // GET_REGINFO_MC_DESC\n\n";
960 RegisterInfoEmitter::runTargetHeader(raw_ostream &OS, CodeGenTarget &Target,
961 CodeGenRegBank &RegBank) {
962 emitSourceFileHeader("Register Information Header Fragment", OS);
964 OS << "\n#ifdef GET_REGINFO_HEADER\n";
965 OS << "#undef GET_REGINFO_HEADER\n";
967 const std::string &TargetName = Target.getName();
968 std::string ClassName = TargetName + "GenRegisterInfo";
970 OS << "#include \"llvm/Target/TargetRegisterInfo.h\"\n\n";
972 OS << "namespace llvm {\n\n";
974 OS << "struct " << ClassName << " : public TargetRegisterInfo {\n"
975 << " explicit " << ClassName
976 << "(unsigned RA, unsigned D = 0, unsigned E = 0, unsigned PC = 0);\n"
977 << " bool needsStackRealignment(const MachineFunction &) const override\n"
978 << " { return false; }\n";
979 if (!RegBank.getSubRegIndices().empty()) {
980 OS << " unsigned composeSubRegIndicesImpl"
981 << "(unsigned, unsigned) const override;\n"
982 << " const TargetRegisterClass *getSubClassWithSubReg"
983 << "(const TargetRegisterClass*, unsigned) const override;\n";
985 OS << " const RegClassWeight &getRegClassWeight("
986 << "const TargetRegisterClass *RC) const override;\n"
987 << " unsigned getRegUnitWeight(unsigned RegUnit) const override;\n"
988 << " unsigned getNumRegPressureSets() const override;\n"
989 << " const char *getRegPressureSetName(unsigned Idx) const override;\n"
990 << " unsigned getRegPressureSetLimit(unsigned Idx) const override;\n"
991 << " const int *getRegClassPressureSets("
992 << "const TargetRegisterClass *RC) const override;\n"
993 << " const int *getRegUnitPressureSets("
994 << "unsigned RegUnit) const override;\n"
997 ArrayRef<CodeGenRegisterClass*> RegisterClasses = RegBank.getRegClasses();
999 if (!RegisterClasses.empty()) {
1000 OS << "namespace " << RegisterClasses[0]->Namespace
1001 << " { // Register classes\n";
1003 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
1004 const CodeGenRegisterClass &RC = *RegisterClasses[i];
1005 const std::string &Name = RC.getName();
1007 // Output the extern for the instance.
1008 OS << " extern const TargetRegisterClass " << Name << "RegClass;\n";
1010 OS << "} // end of namespace " << TargetName << "\n\n";
1012 OS << "} // End llvm namespace\n";
1013 OS << "#endif // GET_REGINFO_HEADER\n\n";
1017 // runTargetDesc - Output the target register and register file descriptions.
1020 RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
1021 CodeGenRegBank &RegBank){
1022 emitSourceFileHeader("Target Register and Register Classes Information", OS);
1024 OS << "\n#ifdef GET_REGINFO_TARGET_DESC\n";
1025 OS << "#undef GET_REGINFO_TARGET_DESC\n";
1027 OS << "namespace llvm {\n\n";
1029 // Get access to MCRegisterClass data.
1030 OS << "extern const MCRegisterClass " << Target.getName()
1031 << "MCRegisterClasses[];\n";
1033 // Start out by emitting each of the register classes.
1034 ArrayRef<CodeGenRegisterClass*> RegisterClasses = RegBank.getRegClasses();
1035 ArrayRef<CodeGenSubRegIndex*> SubRegIndices = RegBank.getSubRegIndices();
1037 // Collect all registers belonging to any allocatable class.
1038 std::set<Record*> AllocatableRegs;
1040 // Collect allocatable registers.
1041 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
1042 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
1043 ArrayRef<Record*> Order = RC.getOrder();
1046 AllocatableRegs.insert(Order.begin(), Order.end());
1049 // Build a shared array of value types.
1050 SequenceToOffsetTable<SmallVector<MVT::SimpleValueType, 4> > VTSeqs;
1051 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc)
1052 VTSeqs.add(RegisterClasses[rc]->VTs);
1054 OS << "\nstatic const MVT::SimpleValueType VTLists[] = {\n";
1055 VTSeqs.emit(OS, printSimpleValueType, "MVT::Other");
1058 // Emit SubRegIndex names, skipping 0.
1059 OS << "\nstatic const char *const SubRegIndexNameTable[] = { \"";
1060 for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) {
1061 OS << SubRegIndices[i]->getName();
1067 // Emit SubRegIndex lane masks, including 0.
1068 OS << "\nstatic const unsigned SubRegIndexLaneMaskTable[] = {\n ~0u,\n";
1069 for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) {
1070 OS << format(" 0x%08x, // ", SubRegIndices[i]->LaneMask)
1071 << SubRegIndices[i]->getName() << '\n';
1077 // Now that all of the structs have been emitted, emit the instances.
1078 if (!RegisterClasses.empty()) {
1079 OS << "\nstatic const TargetRegisterClass *const "
1080 << "NullRegClasses[] = { nullptr };\n\n";
1082 // Emit register class bit mask tables. The first bit mask emitted for a
1083 // register class, RC, is the set of sub-classes, including RC itself.
1085 // If RC has super-registers, also create a list of subreg indices and bit
1086 // masks, (Idx, Mask). The bit mask has a bit for every superreg regclass,
1087 // SuperRC, that satisfies:
1089 // For all SuperReg in SuperRC: SuperReg:Idx in RC
1091 // The 0-terminated list of subreg indices starts at:
1093 // RC->getSuperRegIndices() = SuperRegIdxSeqs + ...
1095 // The corresponding bitmasks follow the sub-class mask in memory. Each
1096 // mask has RCMaskWords uint32_t entries.
1098 // Every bit mask present in the list has at least one bit set.
1100 // Compress the sub-reg index lists.
1101 typedef std::vector<const CodeGenSubRegIndex*> IdxList;
1102 SmallVector<IdxList, 8> SuperRegIdxLists(RegisterClasses.size());
1103 SequenceToOffsetTable<IdxList, CodeGenSubRegIndex::Less> SuperRegIdxSeqs;
1104 BitVector MaskBV(RegisterClasses.size());
1106 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
1107 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
1108 OS << "static const uint32_t " << RC.getName() << "SubClassMask[] = {\n ";
1109 printBitVectorAsHex(OS, RC.getSubClasses(), 32);
1111 // Emit super-reg class masks for any relevant SubRegIndices that can
1113 IdxList &SRIList = SuperRegIdxLists[rc];
1114 for (unsigned sri = 0, sre = SubRegIndices.size(); sri != sre; ++sri) {
1115 CodeGenSubRegIndex *Idx = SubRegIndices[sri];
1117 RC.getSuperRegClasses(Idx, MaskBV);
1120 SRIList.push_back(Idx);
1122 printBitVectorAsHex(OS, MaskBV, 32);
1123 OS << "// " << Idx->getName();
1125 SuperRegIdxSeqs.add(SRIList);
1129 OS << "static const uint16_t SuperRegIdxSeqs[] = {\n";
1130 SuperRegIdxSeqs.layout();
1131 SuperRegIdxSeqs.emit(OS, printSubRegIndex);
1134 // Emit NULL terminated super-class lists.
1135 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
1136 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
1137 ArrayRef<CodeGenRegisterClass*> Supers = RC.getSuperClasses();
1139 // Skip classes without supers. We can reuse NullRegClasses.
1143 OS << "static const TargetRegisterClass *const "
1144 << RC.getName() << "Superclasses[] = {\n";
1145 for (unsigned i = 0; i != Supers.size(); ++i)
1146 OS << " &" << Supers[i]->getQualifiedName() << "RegClass,\n";
1147 OS << " nullptr\n};\n\n";
1151 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
1152 const CodeGenRegisterClass &RC = *RegisterClasses[i];
1153 if (!RC.AltOrderSelect.empty()) {
1154 OS << "\nstatic inline unsigned " << RC.getName()
1155 << "AltOrderSelect(const MachineFunction &MF) {"
1156 << RC.AltOrderSelect << "}\n\n"
1157 << "static ArrayRef<MCPhysReg> " << RC.getName()
1158 << "GetRawAllocationOrder(const MachineFunction &MF) {\n";
1159 for (unsigned oi = 1 , oe = RC.getNumOrders(); oi != oe; ++oi) {
1160 ArrayRef<Record*> Elems = RC.getOrder(oi);
1161 if (!Elems.empty()) {
1162 OS << " static const MCPhysReg AltOrder" << oi << "[] = {";
1163 for (unsigned elem = 0; elem != Elems.size(); ++elem)
1164 OS << (elem ? ", " : " ") << getQualifiedName(Elems[elem]);
1168 OS << " const MCRegisterClass &MCR = " << Target.getName()
1169 << "MCRegisterClasses[" << RC.getQualifiedName() + "RegClassID];\n"
1170 << " const ArrayRef<MCPhysReg> Order[] = {\n"
1171 << " makeArrayRef(MCR.begin(), MCR.getNumRegs()";
1172 for (unsigned oi = 1, oe = RC.getNumOrders(); oi != oe; ++oi)
1173 if (RC.getOrder(oi).empty())
1174 OS << "),\n ArrayRef<MCPhysReg>(";
1176 OS << "),\n makeArrayRef(AltOrder" << oi;
1177 OS << ")\n };\n const unsigned Select = " << RC.getName()
1178 << "AltOrderSelect(MF);\n assert(Select < " << RC.getNumOrders()
1179 << ");\n return Order[Select];\n}\n";
1183 // Now emit the actual value-initialized register class instances.
1184 OS << "\nnamespace " << RegisterClasses[0]->Namespace
1185 << " { // Register class instances\n";
1187 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
1188 const CodeGenRegisterClass &RC = *RegisterClasses[i];
1189 OS << " extern const TargetRegisterClass "
1190 << RegisterClasses[i]->getName() << "RegClass = {\n "
1191 << '&' << Target.getName() << "MCRegisterClasses[" << RC.getName()
1192 << "RegClassID],\n "
1193 << "VTLists + " << VTSeqs.get(RC.VTs) << ",\n "
1194 << RC.getName() << "SubClassMask,\n SuperRegIdxSeqs + "
1195 << SuperRegIdxSeqs.get(SuperRegIdxLists[i]) << ",\n ";
1196 if (RC.getSuperClasses().empty())
1197 OS << "NullRegClasses,\n ";
1199 OS << RC.getName() << "Superclasses,\n ";
1200 if (RC.AltOrderSelect.empty())
1203 OS << RC.getName() << "GetRawAllocationOrder\n";
1210 OS << "\nnamespace {\n";
1211 OS << " const TargetRegisterClass* const RegisterClasses[] = {\n";
1212 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i)
1213 OS << " &" << RegisterClasses[i]->getQualifiedName()
1216 OS << "}\n"; // End of anonymous namespace...
1218 // Emit extra information about registers.
1219 const std::string &TargetName = Target.getName();
1220 OS << "\nstatic const TargetRegisterInfoDesc "
1221 << TargetName << "RegInfoDesc[] = { // Extra Descriptors\n";
1222 OS << " { 0, 0 },\n";
1224 const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters();
1225 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
1226 const CodeGenRegister &Reg = *Regs[i];
1228 OS << Reg.CostPerUse << ", "
1229 << int(AllocatableRegs.count(Reg.TheDef)) << " },\n";
1231 OS << "};\n"; // End of register descriptors...
1234 std::string ClassName = Target.getName() + "GenRegisterInfo";
1236 if (!SubRegIndices.empty())
1237 emitComposeSubRegIndices(OS, RegBank, ClassName);
1239 // Emit getSubClassWithSubReg.
1240 if (!SubRegIndices.empty()) {
1241 OS << "const TargetRegisterClass *" << ClassName
1242 << "::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx)"
1244 // Use the smallest type that can hold a regclass ID with room for a
1246 if (RegisterClasses.size() < UINT8_MAX)
1247 OS << " static const uint8_t Table[";
1248 else if (RegisterClasses.size() < UINT16_MAX)
1249 OS << " static const uint16_t Table[";
1251 PrintFatalError("Too many register classes.");
1252 OS << RegisterClasses.size() << "][" << SubRegIndices.size() << "] = {\n";
1253 for (unsigned rci = 0, rce = RegisterClasses.size(); rci != rce; ++rci) {
1254 const CodeGenRegisterClass &RC = *RegisterClasses[rci];
1255 OS << " {\t// " << RC.getName() << "\n";
1256 for (unsigned sri = 0, sre = SubRegIndices.size(); sri != sre; ++sri) {
1257 CodeGenSubRegIndex *Idx = SubRegIndices[sri];
1258 if (CodeGenRegisterClass *SRC = RC.getSubClassWithSubReg(Idx))
1259 OS << " " << SRC->EnumValue + 1 << ",\t// " << Idx->getName()
1260 << " -> " << SRC->getName() << "\n";
1262 OS << " 0,\t// " << Idx->getName() << "\n";
1266 OS << " };\n assert(RC && \"Missing regclass\");\n"
1267 << " if (!Idx) return RC;\n --Idx;\n"
1268 << " assert(Idx < " << SubRegIndices.size() << " && \"Bad subreg\");\n"
1269 << " unsigned TV = Table[RC->getID()][Idx];\n"
1270 << " return TV ? getRegClass(TV - 1) : nullptr;\n}\n\n";
1273 EmitRegUnitPressure(OS, RegBank, ClassName);
1275 // Emit the constructor of the class...
1276 OS << "extern const MCRegisterDesc " << TargetName << "RegDesc[];\n";
1277 OS << "extern const MCPhysReg " << TargetName << "RegDiffLists[];\n";
1278 OS << "extern const char " << TargetName << "RegStrings[];\n";
1279 OS << "extern const char " << TargetName << "RegClassStrings[];\n";
1280 OS << "extern const MCPhysReg " << TargetName << "RegUnitRoots[][2];\n";
1281 OS << "extern const uint16_t " << TargetName << "SubRegIdxLists[];\n";
1282 OS << "extern const MCRegisterInfo::SubRegCoveredBits "
1283 << TargetName << "SubRegIdxRanges[];\n";
1284 OS << "extern const uint16_t " << TargetName << "RegEncodingTable[];\n";
1286 EmitRegMappingTables(OS, Regs, true);
1288 OS << ClassName << "::\n" << ClassName
1289 << "(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour, unsigned PC)\n"
1290 << " : TargetRegisterInfo(" << TargetName << "RegInfoDesc"
1291 << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n"
1292 << " SubRegIndexNameTable, SubRegIndexLaneMaskTable, 0x";
1293 OS.write_hex(RegBank.CoveringLanes);
1295 << " InitMCRegisterInfo(" << TargetName << "RegDesc, "
1296 << Regs.size()+1 << ", RA, PC,\n " << TargetName
1297 << "MCRegisterClasses, " << RegisterClasses.size() << ",\n"
1298 << " " << TargetName << "RegUnitRoots,\n"
1299 << " " << RegBank.getNumNativeRegUnits() << ",\n"
1300 << " " << TargetName << "RegDiffLists,\n"
1301 << " " << TargetName << "RegStrings,\n"
1302 << " " << TargetName << "RegClassStrings,\n"
1303 << " " << TargetName << "SubRegIdxLists,\n"
1304 << " " << SubRegIndices.size() + 1 << ",\n"
1305 << " " << TargetName << "SubRegIdxRanges,\n"
1306 << " " << TargetName << "RegEncodingTable);\n\n";
1308 EmitRegMapping(OS, Regs, true);
1313 // Emit CalleeSavedRegs information.
1314 std::vector<Record*> CSRSets =
1315 Records.getAllDerivedDefinitions("CalleeSavedRegs");
1316 for (unsigned i = 0, e = CSRSets.size(); i != e; ++i) {
1317 Record *CSRSet = CSRSets[i];
1318 const SetTheory::RecVec *Regs = RegBank.getSets().expand(CSRSet);
1319 assert(Regs && "Cannot expand CalleeSavedRegs instance");
1321 // Emit the *_SaveList list of callee-saved registers.
1322 OS << "static const MCPhysReg " << CSRSet->getName()
1323 << "_SaveList[] = { ";
1324 for (unsigned r = 0, re = Regs->size(); r != re; ++r)
1325 OS << getQualifiedName((*Regs)[r]) << ", ";
1328 // Emit the *_RegMask bit mask of call-preserved registers.
1329 BitVector Covered = RegBank.computeCoveredRegisters(*Regs);
1331 // Check for an optional OtherPreserved set.
1332 // Add those registers to RegMask, but not to SaveList.
1333 if (DagInit *OPDag =
1334 dyn_cast<DagInit>(CSRSet->getValueInit("OtherPreserved"))) {
1335 SetTheory::RecSet OPSet;
1336 RegBank.getSets().evaluate(OPDag, OPSet, CSRSet->getLoc());
1337 Covered |= RegBank.computeCoveredRegisters(
1338 ArrayRef<Record*>(OPSet.begin(), OPSet.end()));
1341 OS << "static const uint32_t " << CSRSet->getName()
1342 << "_RegMask[] = { ";
1343 printBitVectorAsHex(OS, Covered, 32);
1348 OS << "} // End llvm namespace\n";
1349 OS << "#endif // GET_REGINFO_TARGET_DESC\n\n";
1352 void RegisterInfoEmitter::run(raw_ostream &OS) {
1353 CodeGenTarget Target(Records);
1354 CodeGenRegBank &RegBank = Target.getRegBank();
1355 RegBank.computeDerivedInfo();
1357 runEnums(OS, Target, RegBank);
1358 runMCDesc(OS, Target, RegBank);
1359 runTargetHeader(OS, Target, RegBank);
1360 runTargetDesc(OS, Target, RegBank);
1365 void EmitRegisterInfo(RecordKeeper &RK, raw_ostream &OS) {
1366 RegisterInfoEmitter(RK).run(OS);
1369 } // End llvm namespace