1 //===- RegisterInfoEmitter.cpp - Generate a Register File Desc. -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend is responsible for emitting a description of a target
11 // register file for a code generator. It uses instances of the Register,
12 // RegisterAliases, and RegisterClass classes to gather this information.
14 //===----------------------------------------------------------------------===//
16 #include "RegisterInfoEmitter.h"
17 #include "CodeGenTarget.h"
18 #include "CodeGenRegisters.h"
20 #include "llvm/ADT/StringExtras.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/Support/Streams.h"
27 // runEnums - Print out enum values for all of the registers.
28 void RegisterInfoEmitter::runEnums(std::ostream &OS) {
30 const std::vector<CodeGenRegister> &Registers = Target.getRegisters();
32 std::string Namespace = Registers[0].TheDef->getValueAsString("Namespace");
34 EmitSourceFileHeader("Target Register Enum Values", OS);
35 OS << "namespace llvm {\n\n";
37 if (!Namespace.empty())
38 OS << "namespace " << Namespace << " {\n";
39 OS << " enum {\n NoRegister,\n";
41 for (unsigned i = 0, e = Registers.size(); i != e; ++i)
42 OS << " " << Registers[i].getName() << ", \t// " << i+1 << "\n";
43 OS << " NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n";
45 if (!Namespace.empty())
47 OS << "} // End llvm namespace \n";
50 void RegisterInfoEmitter::runHeader(std::ostream &OS) {
51 EmitSourceFileHeader("Register Information Header Fragment", OS);
53 const std::string &TargetName = Target.getName();
54 std::string ClassName = TargetName + "GenRegisterInfo";
56 OS << "#include \"llvm/Target/TargetRegisterInfo.h\"\n";
57 OS << "#include <string>\n\n";
59 OS << "namespace llvm {\n\n";
61 OS << "struct " << ClassName << " : public TargetRegisterInfo {\n"
62 << " explicit " << ClassName
63 << "(int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);\n"
64 << " virtual int getDwarfRegNumFull(unsigned RegNum, "
65 << "unsigned Flavour) const;\n"
66 << " virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0;\n"
67 << " unsigned getSubReg(unsigned RegNo, unsigned Index) const;\n"
70 const std::vector<CodeGenRegisterClass> &RegisterClasses =
71 Target.getRegisterClasses();
73 if (!RegisterClasses.empty()) {
74 OS << "namespace " << RegisterClasses[0].Namespace
75 << " { // Register classes\n";
78 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
80 OS << " " << RegisterClasses[i].getName() << "RegClassID";
85 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
86 const std::string &Name = RegisterClasses[i].getName();
88 // Output the register class definition.
89 OS << " struct " << Name << "Class : public TargetRegisterClass {\n"
90 << " " << Name << "Class();\n"
91 << RegisterClasses[i].MethodProtos << " };\n";
93 // Output the extern for the instance.
94 OS << " extern " << Name << "Class\t" << Name << "RegClass;\n";
95 // Output the extern for the pointer to the instance (should remove).
96 OS << " static TargetRegisterClass * const "<< Name <<"RegisterClass = &"
97 << Name << "RegClass;\n";
99 OS << "} // end of namespace " << TargetName << "\n\n";
101 OS << "} // End llvm namespace \n";
104 bool isSubRegisterClass(const CodeGenRegisterClass &RC,
105 std::set<Record*> &RegSet) {
106 for (unsigned i = 0, e = RC.Elements.size(); i != e; ++i) {
107 Record *Reg = RC.Elements[i];
108 if (!RegSet.count(Reg))
114 static void addSuperReg(Record *R, Record *S,
115 std::map<Record*, std::set<Record*> > &SubRegs,
116 std::map<Record*, std::set<Record*> > &SuperRegs,
117 std::map<Record*, std::set<Record*> > &Aliases) {
119 cerr << "Error: recursive sub-register relationship between"
120 << " register " << getQualifiedName(R)
121 << " and its sub-registers?\n";
124 if (!SuperRegs[R].insert(S).second)
126 SubRegs[S].insert(R);
127 Aliases[R].insert(S);
128 Aliases[S].insert(R);
129 if (SuperRegs.count(S))
130 for (std::set<Record*>::iterator I = SuperRegs[S].begin(),
131 E = SuperRegs[S].end(); I != E; ++I)
132 addSuperReg(R, *I, SubRegs, SuperRegs, Aliases);
135 static void addSubSuperReg(Record *R, Record *S,
136 std::map<Record*, std::set<Record*> > &SubRegs,
137 std::map<Record*, std::set<Record*> > &SuperRegs,
138 std::map<Record*, std::set<Record*> > &Aliases) {
140 cerr << "Error: recursive sub-register relationship between"
141 << " register " << getQualifiedName(R)
142 << " and its sub-registers?\n";
146 if (!SubRegs[R].insert(S).second)
148 addSuperReg(S, R, SubRegs, SuperRegs, Aliases);
149 Aliases[R].insert(S);
150 Aliases[S].insert(R);
151 if (SubRegs.count(S))
152 for (std::set<Record*>::iterator I = SubRegs[S].begin(),
153 E = SubRegs[S].end(); I != E; ++I)
154 addSubSuperReg(R, *I, SubRegs, SuperRegs, Aliases);
157 class RegisterSorter {
159 std::map<Record*, std::set<Record*> > &RegisterSubRegs;
162 RegisterSorter(std::map<Record*, std::set<Record*> > &RS)
163 : RegisterSubRegs(RS) {};
165 bool operator()(Record *RegA, Record *RegB) {
166 // B is sub-register of A.
167 return RegisterSubRegs.count(RegA) && RegisterSubRegs[RegA].count(RegB);
171 // RegisterInfoEmitter::run - Main register file description emitter.
173 void RegisterInfoEmitter::run(std::ostream &OS) {
174 CodeGenTarget Target;
175 EmitSourceFileHeader("Register Information Source Fragment", OS);
177 OS << "namespace llvm {\n\n";
179 // Start out by emitting each of the register classes... to do this, we build
180 // a set of registers which belong to a register class, this is to ensure that
181 // each register is only in a single register class.
183 const std::vector<CodeGenRegisterClass> &RegisterClasses =
184 Target.getRegisterClasses();
186 // Loop over all of the register classes... emitting each one.
187 OS << "namespace { // Register classes...\n";
189 // RegClassesBelongedTo - Keep track of which register classes each reg
191 std::multimap<Record*, const CodeGenRegisterClass*> RegClassesBelongedTo;
193 // Emit the register enum value arrays for each RegisterClass
194 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
195 const CodeGenRegisterClass &RC = RegisterClasses[rc];
197 // Give the register class a legal C name if it's anonymous.
198 std::string Name = RC.TheDef->getName();
200 // Emit the register list now.
201 OS << " // " << Name << " Register Class...\n"
202 << " static const unsigned " << Name
204 for (unsigned i = 0, e = RC.Elements.size(); i != e; ++i) {
205 Record *Reg = RC.Elements[i];
206 OS << getQualifiedName(Reg) << ", ";
208 // Keep track of which regclasses this register is in.
209 RegClassesBelongedTo.insert(std::make_pair(Reg, &RC));
214 // Emit the ValueType arrays for each RegisterClass
215 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
216 const CodeGenRegisterClass &RC = RegisterClasses[rc];
218 // Give the register class a legal C name if it's anonymous.
219 std::string Name = RC.TheDef->getName() + "VTs";
221 // Emit the register list now.
223 << " Register Class Value Types...\n"
224 << " static const MVT::ValueType " << Name
226 for (unsigned i = 0, e = RC.VTs.size(); i != e; ++i)
227 OS << getEnumName(RC.VTs[i]) << ", ";
228 OS << "MVT::Other\n };\n\n";
230 OS << "} // end anonymous namespace\n\n";
232 // Now that all of the structs have been emitted, emit the instances.
233 if (!RegisterClasses.empty()) {
234 OS << "namespace " << RegisterClasses[0].Namespace
235 << " { // Register class instances\n";
236 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i)
237 OS << " " << RegisterClasses[i].getName() << "Class\t"
238 << RegisterClasses[i].getName() << "RegClass;\n";
240 std::map<unsigned, std::set<unsigned> > SuperClassMap;
241 std::map<unsigned, std::set<unsigned> > SuperRegClassMap;
244 // Emit the sub-register classes for each RegisterClass
245 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
246 const CodeGenRegisterClass &RC = RegisterClasses[rc];
248 // Give the register class a legal C name if it's anonymous.
249 std::string Name = RC.TheDef->getName();
252 << " Sub-register Classess...\n"
253 << " static const TargetRegisterClass* const "
254 << Name << "SubRegClasses [] = {\n ";
258 for (unsigned subrc = 0, subrcMax = RC.SubRegClasses.size();
259 subrc != subrcMax; ++subrc) {
260 unsigned rc2 = 0, e2 = RegisterClasses.size();
261 for (; rc2 != e2; ++rc2) {
262 const CodeGenRegisterClass &RC2 = RegisterClasses[rc2];
263 if (RC.SubRegClasses[subrc]->getName() == RC2.getName()) {
266 OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
269 std::map<unsigned, std::set<unsigned> >::iterator SCMI =
270 SuperRegClassMap.find(rc2);
271 if (SCMI == SuperRegClassMap.end()) {
272 SuperRegClassMap.insert(std::make_pair(rc2, std::set<unsigned>()));
273 SCMI = SuperRegClassMap.find(rc2);
275 SCMI->second.insert(rc);
280 throw "Register Class member '" +
281 RC.SubRegClasses[subrc]->getName() +
282 "' is not a valid RegisterClass!";
285 OS << (!Empty ? ", " : "") << "NULL";
289 // Emit the super-register classes for each RegisterClass
290 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
291 const CodeGenRegisterClass &RC = RegisterClasses[rc];
293 // Give the register class a legal C name if it's anonymous.
294 std::string Name = RC.TheDef->getName();
297 << " Super-register Classess...\n"
298 << " static const TargetRegisterClass* const "
299 << Name << "SuperRegClasses [] = {\n ";
302 std::map<unsigned, std::set<unsigned> >::iterator I =
303 SuperRegClassMap.find(rc);
304 if (I != SuperRegClassMap.end()) {
305 for (std::set<unsigned>::iterator II = I->second.begin(),
306 EE = I->second.end(); II != EE; ++II) {
307 const CodeGenRegisterClass &RC2 = RegisterClasses[*II];
310 OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
315 OS << (!Empty ? ", " : "") << "NULL";
319 // Emit the sub-classes array for each RegisterClass
320 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
321 const CodeGenRegisterClass &RC = RegisterClasses[rc];
323 // Give the register class a legal C name if it's anonymous.
324 std::string Name = RC.TheDef->getName();
326 std::set<Record*> RegSet;
327 for (unsigned i = 0, e = RC.Elements.size(); i != e; ++i) {
328 Record *Reg = RC.Elements[i];
333 << " Register Class sub-classes...\n"
334 << " static const TargetRegisterClass* const "
335 << Name << "Subclasses [] = {\n ";
338 for (unsigned rc2 = 0, e2 = RegisterClasses.size(); rc2 != e2; ++rc2) {
339 const CodeGenRegisterClass &RC2 = RegisterClasses[rc2];
340 if (rc == rc2 || RC2.Elements.size() > RC.Elements.size() ||
341 RC.SpillSize != RC2.SpillSize || !isSubRegisterClass(RC2, RegSet))
344 if (!Empty) OS << ", ";
345 OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
348 std::map<unsigned, std::set<unsigned> >::iterator SCMI =
349 SuperClassMap.find(rc2);
350 if (SCMI == SuperClassMap.end()) {
351 SuperClassMap.insert(std::make_pair(rc2, std::set<unsigned>()));
352 SCMI = SuperClassMap.find(rc2);
354 SCMI->second.insert(rc);
357 OS << (!Empty ? ", " : "") << "NULL";
361 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
362 const CodeGenRegisterClass &RC = RegisterClasses[rc];
364 // Give the register class a legal C name if it's anonymous.
365 std::string Name = RC.TheDef->getName();
368 << " Register Class super-classes...\n"
369 << " static const TargetRegisterClass* const "
370 << Name << "Superclasses [] = {\n ";
373 std::map<unsigned, std::set<unsigned> >::iterator I =
374 SuperClassMap.find(rc);
375 if (I != SuperClassMap.end()) {
376 for (std::set<unsigned>::iterator II = I->second.begin(),
377 EE = I->second.end(); II != EE; ++II) {
378 const CodeGenRegisterClass &RC2 = RegisterClasses[*II];
379 if (!Empty) OS << ", ";
380 OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
385 OS << (!Empty ? ", " : "") << "NULL";
390 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
391 const CodeGenRegisterClass &RC = RegisterClasses[i];
392 OS << RC.MethodBodies << "\n";
393 OS << RC.getName() << "Class::" << RC.getName()
394 << "Class() : TargetRegisterClass("
395 << RC.getName() + "RegClassID" << ", "
396 << RC.getName() + "VTs" << ", "
397 << RC.getName() + "Subclasses" << ", "
398 << RC.getName() + "Superclasses" << ", "
399 << RC.getName() + "SubRegClasses" << ", "
400 << RC.getName() + "SuperRegClasses" << ", "
401 << RC.SpillSize/8 << ", "
402 << RC.SpillAlignment/8 << ", "
403 << RC.CopyCost << ", "
404 << RC.getName() << ", " << RC.getName() << " + " << RC.Elements.size()
411 OS << "\nnamespace {\n";
412 OS << " const TargetRegisterClass* const RegisterClasses[] = {\n";
413 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i)
414 OS << " &" << getQualifiedName(RegisterClasses[i].TheDef)
418 // Emit register sub-registers / super-registers, aliases...
419 std::map<Record*, std::set<Record*> > RegisterImmSubRegs;
420 std::map<Record*, std::set<Record*> > RegisterSubRegs;
421 std::map<Record*, std::set<Record*> > RegisterSuperRegs;
422 std::map<Record*, std::set<Record*> > RegisterAliases;
423 std::map<Record*, std::vector<std::pair<int, Record*> > > SubRegVectors;
424 std::map<Record*, std::vector<int> > DwarfRegNums;
426 const std::vector<CodeGenRegister> &Regs = Target.getRegisters();
428 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
429 Record *R = Regs[i].TheDef;
430 std::vector<Record*> LI = Regs[i].TheDef->getValueAsListOfDefs("Aliases");
431 // Add information that R aliases all of the elements in the list... and
432 // that everything in the list aliases R.
433 for (unsigned j = 0, e = LI.size(); j != e; ++j) {
435 if (RegisterAliases[R].count(Reg))
436 cerr << "Warning: register alias between " << getQualifiedName(R)
437 << " and " << getQualifiedName(Reg)
438 << " specified multiple times!\n";
439 RegisterAliases[R].insert(Reg);
441 if (RegisterAliases[Reg].count(R))
442 cerr << "Warning: register alias between " << getQualifiedName(R)
443 << " and " << getQualifiedName(Reg)
444 << " specified multiple times!\n";
445 RegisterAliases[Reg].insert(R);
449 // Process sub-register sets.
450 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
451 Record *R = Regs[i].TheDef;
452 std::vector<Record*> LI = Regs[i].TheDef->getValueAsListOfDefs("SubRegs");
453 // Process sub-register set and add aliases information.
454 for (unsigned j = 0, e = LI.size(); j != e; ++j) {
455 Record *SubReg = LI[j];
456 if (RegisterSubRegs[R].count(SubReg))
457 cerr << "Warning: register " << getQualifiedName(SubReg)
458 << " specified as a sub-register of " << getQualifiedName(R)
459 << " multiple times!\n";
460 RegisterImmSubRegs[R].insert(SubReg);
461 addSubSuperReg(R, SubReg, RegisterSubRegs, RegisterSuperRegs,
466 if (!RegisterAliases.empty())
467 OS << "\n\n // Register Alias Sets...\n";
469 // Emit the empty alias list
470 OS << " const unsigned Empty_AliasSet[] = { 0 };\n";
471 // Loop over all of the registers which have aliases, emitting the alias list
473 for (std::map<Record*, std::set<Record*> >::iterator
474 I = RegisterAliases.begin(), E = RegisterAliases.end(); I != E; ++I) {
475 OS << " const unsigned " << I->first->getName() << "_AliasSet[] = { ";
476 for (std::set<Record*>::iterator ASI = I->second.begin(),
477 E = I->second.end(); ASI != E; ++ASI)
478 OS << getQualifiedName(*ASI) << ", ";
482 if (!RegisterSubRegs.empty())
483 OS << "\n\n // Register Sub-registers Sets...\n";
485 // Emit the empty sub-registers list
486 OS << " const unsigned Empty_SubRegsSet[] = { 0 };\n";
487 // Loop over all of the registers which have sub-registers, emitting the
488 // sub-registers list to memory.
489 for (std::map<Record*, std::set<Record*> >::iterator
490 I = RegisterSubRegs.begin(), E = RegisterSubRegs.end(); I != E; ++I) {
491 OS << " const unsigned " << I->first->getName() << "_SubRegsSet[] = { ";
492 std::vector<Record*> SubRegsVector;
493 for (std::set<Record*>::iterator ASI = I->second.begin(),
494 E = I->second.end(); ASI != E; ++ASI)
495 SubRegsVector.push_back(*ASI);
496 RegisterSorter RS(RegisterSubRegs);
497 std::stable_sort(SubRegsVector.begin(), SubRegsVector.end(), RS);
498 for (unsigned i = 0, e = SubRegsVector.size(); i != e; ++i)
499 OS << getQualifiedName(SubRegsVector[i]) << ", ";
503 if (!RegisterImmSubRegs.empty())
504 OS << "\n\n // Register Immediate Sub-registers Sets...\n";
506 // Loop over all of the registers which have sub-registers, emitting the
507 // sub-registers list to memory.
508 for (std::map<Record*, std::set<Record*> >::iterator
509 I = RegisterImmSubRegs.begin(), E = RegisterImmSubRegs.end();
511 OS << " const unsigned " << I->first->getName() << "_ImmSubRegsSet[] = { ";
512 for (std::set<Record*>::iterator ASI = I->second.begin(),
513 E = I->second.end(); ASI != E; ++ASI)
514 OS << getQualifiedName(*ASI) << ", ";
518 if (!RegisterSuperRegs.empty())
519 OS << "\n\n // Register Super-registers Sets...\n";
521 // Emit the empty super-registers list
522 OS << " const unsigned Empty_SuperRegsSet[] = { 0 };\n";
523 // Loop over all of the registers which have super-registers, emitting the
524 // super-registers list to memory.
525 for (std::map<Record*, std::set<Record*> >::iterator
526 I = RegisterSuperRegs.begin(), E = RegisterSuperRegs.end(); I != E; ++I) {
527 OS << " const unsigned " << I->first->getName() << "_SuperRegsSet[] = { ";
529 std::vector<Record*> SuperRegsVector;
530 for (std::set<Record*>::iterator ASI = I->second.begin(),
531 E = I->second.end(); ASI != E; ++ASI)
532 SuperRegsVector.push_back(*ASI);
533 RegisterSorter RS(RegisterSubRegs);
534 std::stable_sort(SuperRegsVector.begin(), SuperRegsVector.end(), RS);
535 for (unsigned i = 0, e = SuperRegsVector.size(); i != e; ++i)
536 OS << getQualifiedName(SuperRegsVector[i]) << ", ";
540 OS<<"\n const TargetRegisterDesc RegisterDescriptors[] = { // Descriptors\n";
541 OS << " { \"NOREG\",\t\"NOREG\",\t0,\t0,\t0,\t0 },\n";
543 // Now that register alias and sub-registers sets have been emitted, emit the
544 // register descriptors now.
545 const std::vector<CodeGenRegister> &Registers = Target.getRegisters();
546 for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
547 const CodeGenRegister &Reg = Registers[i];
549 if (!Reg.TheDef->getValueAsString("AsmName").empty())
550 OS << Reg.TheDef->getValueAsString("AsmName");
554 if (!Reg.TheDef->getValueAsString("Name").empty()) {
555 OS << Reg.TheDef->getValueAsString("Name");
557 // Default to "name".
558 if (!Reg.TheDef->getValueAsString("AsmName").empty())
559 OS << Reg.TheDef->getValueAsString("AsmName");
564 if (RegisterAliases.count(Reg.TheDef))
565 OS << Reg.getName() << "_AliasSet,\t";
567 OS << "Empty_AliasSet,\t";
568 if (RegisterSubRegs.count(Reg.TheDef))
569 OS << Reg.getName() << "_SubRegsSet,\t";
571 OS << "Empty_SubRegsSet,\t";
572 if (RegisterImmSubRegs.count(Reg.TheDef))
573 OS << Reg.getName() << "_ImmSubRegsSet,\t";
575 OS << "Empty_SubRegsSet,\t";
576 if (RegisterSuperRegs.count(Reg.TheDef))
577 OS << Reg.getName() << "_SuperRegsSet },\n";
579 OS << "Empty_SuperRegsSet },\n";
581 OS << " };\n"; // End of register descriptors...
582 OS << "}\n\n"; // End of anonymous namespace...
584 std::string ClassName = Target.getName() + "GenRegisterInfo";
586 // Calculate the mapping of subregister+index pairs to physical registers.
587 std::vector<Record*> SubRegs = Records.getAllDerivedDefinitions("SubRegSet");
588 for (unsigned i = 0, e = SubRegs.size(); i != e; ++i) {
589 int subRegIndex = SubRegs[i]->getValueAsInt("index");
590 std::vector<Record*> From = SubRegs[i]->getValueAsListOfDefs("From");
591 std::vector<Record*> To = SubRegs[i]->getValueAsListOfDefs("To");
593 if (From.size() != To.size()) {
594 cerr << "Error: register list and sub-register list not of equal length"
595 << " in SubRegSet\n";
599 // For each entry in from/to vectors, insert the to register at index
600 for (unsigned ii = 0, ee = From.size(); ii != ee; ++ii)
601 SubRegVectors[From[ii]].push_back(std::make_pair(subRegIndex, To[ii]));
604 // Emit the subregister + index mapping function based on the information
606 OS << "unsigned " << ClassName
607 << "::getSubReg(unsigned RegNo, unsigned Index) const {\n"
608 << " switch (RegNo) {\n"
609 << " default: abort(); break;\n";
610 for (std::map<Record*, std::vector<std::pair<int, Record*> > >::iterator
611 I = SubRegVectors.begin(), E = SubRegVectors.end(); I != E; ++I) {
612 OS << " case " << getQualifiedName(I->first) << ":\n";
613 OS << " switch (Index) {\n";
614 OS << " default: abort(); break;\n";
615 for (unsigned i = 0, e = I->second.size(); i != e; ++i)
616 OS << " case " << (I->second)[i].first << ": return "
617 << getQualifiedName((I->second)[i].second) << ";\n";
618 OS << " }; break;\n";
621 OS << " return 0;\n";
624 // Emit the constructor of the class...
625 OS << ClassName << "::" << ClassName
626 << "(int CallFrameSetupOpcode, int CallFrameDestroyOpcode)\n"
627 << " : TargetRegisterInfo(RegisterDescriptors, " << Registers.size()+1
628 << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n "
629 << " CallFrameSetupOpcode, CallFrameDestroyOpcode) {}\n\n";
631 // Collect all information about dwarf register numbers
633 // First, just pull all provided information to the map
634 unsigned maxLength = 0;
635 for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
636 Record *Reg = Registers[i].TheDef;
637 std::vector<int> RegNums = Reg->getValueAsListOfInts("DwarfNumbers");
638 maxLength = std::max((size_t)maxLength, RegNums.size());
639 if (DwarfRegNums.count(Reg))
640 cerr << "Warning: DWARF numbers for register " << getQualifiedName(Reg)
641 << "specified multiple times\n";
642 DwarfRegNums[Reg] = RegNums;
645 // Now we know maximal length of number list. Append -1's, where needed
646 for (std::map<Record*, std::vector<int> >::iterator
647 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I)
648 for (unsigned i = I->second.size(), e = maxLength; i != e; ++i)
649 I->second.push_back(-1);
651 // Emit information about the dwarf register numbers.
652 OS << "int " << ClassName << "::getDwarfRegNumFull(unsigned RegNum, "
653 << "unsigned Flavour) const {\n"
654 << " switch (Flavour) {\n"
656 << " assert(0 && \"Unknown DWARF flavour\");\n"
659 for (unsigned i = 0, e = maxLength; i != e; ++i) {
660 OS << " case " << i << ":\n"
661 << " switch (RegNum) {\n"
663 << " assert(0 && \"Invalid RegNum\");\n"
666 for (std::map<Record*, std::vector<int> >::iterator
667 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
668 int RegNo = I->second[i];
670 OS << " case " << getQualifiedName(I->first) << ":\n"
671 << " return " << RegNo << ";\n";
673 OS << " case " << getQualifiedName(I->first) << ":\n"
674 << " assert(0 && \"Invalid register for this mode\");\n"
682 OS << "} // End llvm namespace \n";