1 //===- RegisterInfoEmitter.cpp - Generate a Register File Desc. -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend is responsible for emitting a description of a target
11 // register file for a code generator. It uses instances of the Register,
12 // RegisterAliases, and RegisterClass classes to gather this information.
14 //===----------------------------------------------------------------------===//
16 #include "RegisterInfoEmitter.h"
17 #include "CodeGenTarget.h"
18 #include "CodeGenRegisters.h"
20 #include "llvm/ADT/StringExtras.h"
21 #include "llvm/ADT/STLExtras.h"
26 // runEnums - Print out enum values for all of the registers.
27 void RegisterInfoEmitter::runEnums(raw_ostream &OS) {
29 const std::vector<CodeGenRegister> &Registers = Target.getRegisters();
31 std::string Namespace = Registers[0].TheDef->getValueAsString("Namespace");
33 EmitSourceFileHeader("Target Register Enum Values", OS);
34 OS << "namespace llvm {\n\n";
36 if (!Namespace.empty())
37 OS << "namespace " << Namespace << " {\n";
38 OS << "enum {\n NoRegister,\n";
40 for (unsigned i = 0, e = Registers.size(); i != e; ++i)
41 OS << " " << Registers[i].getName() << ", \t// " << i+1 << "\n";
42 OS << " NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n";
44 if (!Namespace.empty())
47 const std::vector<Record*> SubRegIndices = Target.getSubRegIndices();
48 if (!SubRegIndices.empty()) {
49 OS << "\n// Subregister indices\n";
50 Namespace = SubRegIndices[0]->getValueAsString("Namespace");
51 if (!Namespace.empty())
52 OS << "namespace " << Namespace << " {\n";
53 OS << "enum {\n NoSubRegister,\n";
54 for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i)
55 OS << " " << SubRegIndices[i]->getName() << ",\t// " << i+1 << "\n";
56 OS << " NUM_TARGET_SUBREGS = " << SubRegIndices.size()+1 << "\n";
58 if (!Namespace.empty())
61 OS << "} // End llvm namespace \n";
64 void RegisterInfoEmitter::runHeader(raw_ostream &OS) {
65 EmitSourceFileHeader("Register Information Header Fragment", OS);
67 const std::string &TargetName = Target.getName();
68 std::string ClassName = TargetName + "GenRegisterInfo";
70 OS << "#include \"llvm/Target/TargetRegisterInfo.h\"\n";
71 OS << "#include <string>\n\n";
73 OS << "namespace llvm {\n\n";
75 OS << "struct " << ClassName << " : public TargetRegisterInfo {\n"
76 << " explicit " << ClassName
77 << "(int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);\n"
78 << " virtual int getDwarfRegNumFull(unsigned RegNum, "
79 << "unsigned Flavour) const;\n"
80 << " virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0;\n"
81 << " virtual bool needsStackRealignment(const MachineFunction &) const\n"
82 << " { return false; }\n"
83 << " unsigned getSubReg(unsigned RegNo, unsigned Index) const;\n"
84 << " unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const;\n"
85 << " unsigned composeSubRegIndices(unsigned, unsigned) const;\n"
88 const std::vector<CodeGenRegisterClass> &RegisterClasses =
89 Target.getRegisterClasses();
91 if (!RegisterClasses.empty()) {
92 OS << "namespace " << RegisterClasses[0].Namespace
93 << " { // Register classes\n";
96 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
98 OS << " " << RegisterClasses[i].getName() << "RegClassID";
103 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
104 const std::string &Name = RegisterClasses[i].getName();
106 // Output the register class definition.
107 OS << " struct " << Name << "Class : public TargetRegisterClass {\n"
108 << " " << Name << "Class();\n"
109 << RegisterClasses[i].MethodProtos << " };\n";
111 // Output the extern for the instance.
112 OS << " extern " << Name << "Class\t" << Name << "RegClass;\n";
113 // Output the extern for the pointer to the instance (should remove).
114 OS << " static TargetRegisterClass * const "<< Name <<"RegisterClass = &"
115 << Name << "RegClass;\n";
117 OS << "} // end of namespace " << TargetName << "\n\n";
119 OS << "} // End llvm namespace \n";
122 bool isSubRegisterClass(const CodeGenRegisterClass &RC,
123 std::set<Record*> &RegSet) {
124 for (unsigned i = 0, e = RC.Elements.size(); i != e; ++i) {
125 Record *Reg = RC.Elements[i];
126 if (!RegSet.count(Reg))
132 static void addSuperReg(Record *R, Record *S,
133 std::map<Record*, std::set<Record*>, LessRecord> &SubRegs,
134 std::map<Record*, std::set<Record*>, LessRecord> &SuperRegs,
135 std::map<Record*, std::set<Record*>, LessRecord> &Aliases) {
137 errs() << "Error: recursive sub-register relationship between"
138 << " register " << getQualifiedName(R)
139 << " and its sub-registers?\n";
142 if (!SuperRegs[R].insert(S).second)
144 SubRegs[S].insert(R);
145 Aliases[R].insert(S);
146 Aliases[S].insert(R);
147 if (SuperRegs.count(S))
148 for (std::set<Record*>::iterator I = SuperRegs[S].begin(),
149 E = SuperRegs[S].end(); I != E; ++I)
150 addSuperReg(R, *I, SubRegs, SuperRegs, Aliases);
153 static void addSubSuperReg(Record *R, Record *S,
154 std::map<Record*, std::set<Record*>, LessRecord> &SubRegs,
155 std::map<Record*, std::set<Record*>, LessRecord> &SuperRegs,
156 std::map<Record*, std::set<Record*>, LessRecord> &Aliases) {
158 errs() << "Error: recursive sub-register relationship between"
159 << " register " << getQualifiedName(R)
160 << " and its sub-registers?\n";
164 if (!SubRegs[R].insert(S).second)
166 addSuperReg(S, R, SubRegs, SuperRegs, Aliases);
167 Aliases[R].insert(S);
168 Aliases[S].insert(R);
169 if (SubRegs.count(S))
170 for (std::set<Record*>::iterator I = SubRegs[S].begin(),
171 E = SubRegs[S].end(); I != E; ++I)
172 addSubSuperReg(R, *I, SubRegs, SuperRegs, Aliases);
175 struct RegisterMaps {
176 // Map SubRegIndex -> Register
177 typedef std::map<Record*, Record*, LessRecord> SubRegMap;
178 // Map Register -> SubRegMap
179 typedef std::map<Record*, SubRegMap> SubRegMaps;
182 SubRegMap &inferSubRegIndices(Record *Reg);
184 // Composite SubRegIndex instances.
185 // Map (SubRegIndex,SubRegIndex) -> SubRegIndex
186 typedef DenseMap<std::pair<Record*,Record*>,Record*> CompositeMap;
187 CompositeMap Composite;
189 // Compute SubRegIndex compositions after inferSubRegIndices has run on all
191 void computeComposites();
194 // Calculate all subregindices for Reg. Loopy subregs cause infinite recursion.
195 RegisterMaps::SubRegMap &RegisterMaps::inferSubRegIndices(Record *Reg) {
196 SubRegMap &SRM = SubReg[Reg];
199 std::vector<Record*> SubRegs = Reg->getValueAsListOfDefs("SubRegs");
200 std::vector<Record*> Indices = Reg->getValueAsListOfDefs("SubRegIndices");
201 if (SubRegs.size() != Indices.size())
202 throw "Register " + Reg->getName() + " SubRegIndices doesn't match SubRegs";
204 // First insert the direct subregs and make sure they are fully indexed.
205 for (unsigned i = 0, e = SubRegs.size(); i != e; ++i) {
206 if (!SRM.insert(std::make_pair(Indices[i], SubRegs[i])).second)
207 throw "SubRegIndex " + Indices[i]->getName()
208 + " appears twice in Register " + Reg->getName();
209 inferSubRegIndices(SubRegs[i]);
212 // Keep track of inherited subregs and how they can be reached.
213 // Register -> (SubRegIndex, SubRegIndex)
214 typedef std::map<Record*, std::pair<Record*,Record*>, LessRecord> OrphanMap;
217 // Clone inherited subregs. Here the order is important - earlier subregs take
219 for (unsigned i = 0, e = SubRegs.size(); i != e; ++i) {
220 SubRegMap &M = SubReg[SubRegs[i]];
221 for (SubRegMap::iterator si = M.begin(), se = M.end(); si != se; ++si)
222 if (!SRM.insert(*si).second)
223 Orphans[si->second] = std::make_pair(Indices[i], si->first);
226 // Finally process the composites.
227 ListInit *Comps = Reg->getValueAsListInit("CompositeIndices");
228 for (unsigned i = 0, e = Comps->size(); i != e; ++i) {
229 DagInit *Pat = dynamic_cast<DagInit*>(Comps->getElement(i));
231 throw "Invalid dag '" + Comps->getElement(i)->getAsString()
232 + "' in CompositeIndices";
233 DefInit *BaseIdxInit = dynamic_cast<DefInit*>(Pat->getOperator());
234 if (!BaseIdxInit || !BaseIdxInit->getDef()->isSubClassOf("SubRegIndex"))
235 throw "Invalid SubClassIndex in " + Pat->getAsString();
237 // Resolve list of subreg indices into R2.
239 for (DagInit::const_arg_iterator di = Pat->arg_begin(),
240 de = Pat->arg_end(); di != de; ++di) {
241 DefInit *IdxInit = dynamic_cast<DefInit*>(*di);
242 if (!IdxInit || !IdxInit->getDef()->isSubClassOf("SubRegIndex"))
243 throw "Invalid SubClassIndex in " + Pat->getAsString();
244 SubRegMap::const_iterator ni = SubReg[R2].find(IdxInit->getDef());
245 if (ni == SubReg[R2].end())
246 throw "Composite " + Pat->getAsString() + " refers to bad index in "
251 // Insert composite index. Allow overriding inherited indices etc.
252 SRM[BaseIdxInit->getDef()] = R2;
254 // R2 is now directly addressable, no longer an orphan.
258 // Now, Orphans contains the inherited subregisters without a direct index.
259 if (!Orphans.empty()) {
260 errs() << "Error: Register " << getQualifiedName(Reg)
261 << " inherited subregisters without an index:\n";
262 for (OrphanMap::iterator i = Orphans.begin(), e = Orphans.end(); i != e;
264 errs() << " " << getQualifiedName(i->first)
265 << " = " << i->second.first->getName()
266 << ", " << i->second.second->getName() << "\n";
273 void RegisterMaps::computeComposites() {
274 for (SubRegMaps::const_iterator sri = SubReg.begin(), sre = SubReg.end();
276 Record *Reg1 = sri->first;
277 const SubRegMap &SRM1 = sri->second;
278 for (SubRegMap::const_iterator i1 = SRM1.begin(), e1 = SRM1.end();
280 Record *Idx1 = i1->first;
281 Record *Reg2 = i1->second;
282 // Ignore identity compositions.
285 // If Reg2 has no subregs, Idx1 doesn't compose.
286 if (!SubReg.count(Reg2))
288 const SubRegMap &SRM2 = SubReg[Reg2];
289 // Try composing Idx1 with another SubRegIndex.
290 for (SubRegMap::const_iterator i2 = SRM2.begin(), e2 = SRM2.end();
292 std::pair<Record*,Record*> IdxPair(Idx1, i2->first);
293 Record *Reg3 = i2->second;
294 // OK Reg1:IdxPair == Reg3. Find the index with Reg:Idx == Reg3.
295 for (SubRegMap::const_iterator i1d = SRM1.begin(), e1d = SRM1.end();
297 // Ignore identity compositions.
300 if (i1d->second == Reg3) {
301 std::pair<CompositeMap::iterator,bool> Ins =
302 Composite.insert(std::make_pair(IdxPair, i1d->first));
303 // Conflicting composition?
304 if (!Ins.second && Ins.first->second != i1d->first) {
305 errs() << "Error: SubRegIndex " << getQualifiedName(Idx1)
306 << " and " << getQualifiedName(IdxPair.second)
307 << " compose ambiguously as "
308 << getQualifiedName(Ins.first->second) << " or "
309 << getQualifiedName(i1d->first) << "\n";
318 // We don't care about the difference between (Idx1, Idx2) -> Idx2 and invalid
319 // compositions, so remove any mappings of that form.
320 for (CompositeMap::iterator i = Composite.begin(), e = Composite.end();
322 CompositeMap::iterator j = i;
324 if (j->first.second == j->second)
329 class RegisterSorter {
331 std::map<Record*, std::set<Record*>, LessRecord> &RegisterSubRegs;
334 RegisterSorter(std::map<Record*, std::set<Record*>, LessRecord> &RS)
335 : RegisterSubRegs(RS) {}
337 bool operator()(Record *RegA, Record *RegB) {
338 // B is sub-register of A.
339 return RegisterSubRegs.count(RegA) && RegisterSubRegs[RegA].count(RegB);
343 // RegisterInfoEmitter::run - Main register file description emitter.
345 void RegisterInfoEmitter::run(raw_ostream &OS) {
346 CodeGenTarget Target;
347 EmitSourceFileHeader("Register Information Source Fragment", OS);
349 OS << "namespace llvm {\n\n";
351 // Start out by emitting each of the register classes... to do this, we build
352 // a set of registers which belong to a register class, this is to ensure that
353 // each register is only in a single register class.
355 const std::vector<CodeGenRegisterClass> &RegisterClasses =
356 Target.getRegisterClasses();
358 // Loop over all of the register classes... emitting each one.
359 OS << "namespace { // Register classes...\n";
361 // RegClassesBelongedTo - Keep track of which register classes each reg
363 std::multimap<Record*, const CodeGenRegisterClass*> RegClassesBelongedTo;
365 // Emit the register enum value arrays for each RegisterClass
366 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
367 const CodeGenRegisterClass &RC = RegisterClasses[rc];
369 // Give the register class a legal C name if it's anonymous.
370 std::string Name = RC.TheDef->getName();
372 // Emit the register list now.
373 OS << " // " << Name << " Register Class...\n"
374 << " static const unsigned " << Name
376 for (unsigned i = 0, e = RC.Elements.size(); i != e; ++i) {
377 Record *Reg = RC.Elements[i];
378 OS << getQualifiedName(Reg) << ", ";
380 // Keep track of which regclasses this register is in.
381 RegClassesBelongedTo.insert(std::make_pair(Reg, &RC));
386 // Emit the ValueType arrays for each RegisterClass
387 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
388 const CodeGenRegisterClass &RC = RegisterClasses[rc];
390 // Give the register class a legal C name if it's anonymous.
391 std::string Name = RC.TheDef->getName() + "VTs";
393 // Emit the register list now.
395 << " Register Class Value Types...\n"
396 << " static const EVT " << Name
398 for (unsigned i = 0, e = RC.VTs.size(); i != e; ++i)
399 OS << getEnumName(RC.VTs[i]) << ", ";
400 OS << "MVT::Other\n };\n\n";
402 OS << "} // end anonymous namespace\n\n";
404 // Now that all of the structs have been emitted, emit the instances.
405 if (!RegisterClasses.empty()) {
406 OS << "namespace " << RegisterClasses[0].Namespace
407 << " { // Register class instances\n";
408 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i)
409 OS << " " << RegisterClasses[i].getName() << "Class\t"
410 << RegisterClasses[i].getName() << "RegClass;\n";
412 std::map<unsigned, std::set<unsigned> > SuperClassMap;
413 std::map<unsigned, std::set<unsigned> > SuperRegClassMap;
416 unsigned NumSubRegIndices = Target.getSubRegIndices().size();
418 if (NumSubRegIndices) {
419 // Emit the sub-register classes for each RegisterClass
420 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
421 const CodeGenRegisterClass &RC = RegisterClasses[rc];
422 std::vector<Record*> SRC(NumSubRegIndices);
423 for (DenseMap<Record*,Record*>::const_iterator
424 i = RC.SubRegClasses.begin(),
425 e = RC.SubRegClasses.end(); i != e; ++i) {
427 unsigned idx = Target.getSubRegIndexNo(i->first);
428 SRC.at(idx-1) = i->second;
430 // Find the register class number of i->second for SuperRegClassMap.
431 for (unsigned rc2 = 0, e2 = RegisterClasses.size(); rc2 != e2; ++rc2) {
432 const CodeGenRegisterClass &RC2 = RegisterClasses[rc2];
433 if (RC2.TheDef == i->second) {
434 SuperRegClassMap[rc2].insert(rc);
440 // Give the register class a legal C name if it's anonymous.
441 std::string Name = RC.TheDef->getName();
444 << " Sub-register Classes...\n"
445 << " static const TargetRegisterClass* const "
446 << Name << "SubRegClasses[] = {\n ";
448 for (unsigned idx = 0; idx != NumSubRegIndices; ++idx) {
452 OS << "&" << getQualifiedName(SRC[idx]) << "RegClass";
459 // Emit the super-register classes for each RegisterClass
460 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
461 const CodeGenRegisterClass &RC = RegisterClasses[rc];
463 // Give the register class a legal C name if it's anonymous.
464 std::string Name = RC.TheDef->getName();
467 << " Super-register Classes...\n"
468 << " static const TargetRegisterClass* const "
469 << Name << "SuperRegClasses[] = {\n ";
472 std::map<unsigned, std::set<unsigned> >::iterator I =
473 SuperRegClassMap.find(rc);
474 if (I != SuperRegClassMap.end()) {
475 for (std::set<unsigned>::iterator II = I->second.begin(),
476 EE = I->second.end(); II != EE; ++II) {
477 const CodeGenRegisterClass &RC2 = RegisterClasses[*II];
480 OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
485 OS << (!Empty ? ", " : "") << "NULL";
489 // No subregindices in this target
490 OS << " static const TargetRegisterClass* const "
491 << "NullRegClasses[] = { NULL };\n\n";
494 // Emit the sub-classes array for each RegisterClass
495 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
496 const CodeGenRegisterClass &RC = RegisterClasses[rc];
498 // Give the register class a legal C name if it's anonymous.
499 std::string Name = RC.TheDef->getName();
501 std::set<Record*> RegSet;
502 for (unsigned i = 0, e = RC.Elements.size(); i != e; ++i) {
503 Record *Reg = RC.Elements[i];
508 << " Register Class sub-classes...\n"
509 << " static const TargetRegisterClass* const "
510 << Name << "Subclasses[] = {\n ";
513 for (unsigned rc2 = 0, e2 = RegisterClasses.size(); rc2 != e2; ++rc2) {
514 const CodeGenRegisterClass &RC2 = RegisterClasses[rc2];
516 // RC2 is a sub-class of RC if it is a valid replacement for any
517 // instruction operand where an RC register is required. It must satisfy
520 // 1. All RC2 registers are also in RC.
521 // 2. The RC2 spill size must not be smaller that the RC spill size.
522 // 3. RC2 spill alignment must be compatible with RC.
524 // Sub-classes are used to determine if a virtual register can be used
525 // as an instruction operand, or if it must be copied first.
527 if (rc == rc2 || RC2.Elements.size() > RC.Elements.size() ||
528 (RC.SpillAlignment && RC2.SpillAlignment % RC.SpillAlignment) ||
529 RC.SpillSize > RC2.SpillSize || !isSubRegisterClass(RC2, RegSet))
532 if (!Empty) OS << ", ";
533 OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
536 std::map<unsigned, std::set<unsigned> >::iterator SCMI =
537 SuperClassMap.find(rc2);
538 if (SCMI == SuperClassMap.end()) {
539 SuperClassMap.insert(std::make_pair(rc2, std::set<unsigned>()));
540 SCMI = SuperClassMap.find(rc2);
542 SCMI->second.insert(rc);
545 OS << (!Empty ? ", " : "") << "NULL";
549 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
550 const CodeGenRegisterClass &RC = RegisterClasses[rc];
552 // Give the register class a legal C name if it's anonymous.
553 std::string Name = RC.TheDef->getName();
556 << " Register Class super-classes...\n"
557 << " static const TargetRegisterClass* const "
558 << Name << "Superclasses[] = {\n ";
561 std::map<unsigned, std::set<unsigned> >::iterator I =
562 SuperClassMap.find(rc);
563 if (I != SuperClassMap.end()) {
564 for (std::set<unsigned>::iterator II = I->second.begin(),
565 EE = I->second.end(); II != EE; ++II) {
566 const CodeGenRegisterClass &RC2 = RegisterClasses[*II];
567 if (!Empty) OS << ", ";
568 OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
573 OS << (!Empty ? ", " : "") << "NULL";
578 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
579 const CodeGenRegisterClass &RC = RegisterClasses[i];
580 OS << RC.MethodBodies << "\n";
581 OS << RC.getName() << "Class::" << RC.getName()
582 << "Class() : TargetRegisterClass("
583 << RC.getName() + "RegClassID" << ", "
584 << '\"' << RC.getName() << "\", "
585 << RC.getName() + "VTs" << ", "
586 << RC.getName() + "Subclasses" << ", "
587 << RC.getName() + "Superclasses" << ", "
588 << (NumSubRegIndices ? RC.getName() + "Sub" : std::string("Null"))
590 << (NumSubRegIndices ? RC.getName() + "Super" : std::string("Null"))
592 << RC.SpillSize/8 << ", "
593 << RC.SpillAlignment/8 << ", "
594 << RC.CopyCost << ", "
595 << RC.getName() << ", " << RC.getName() << " + " << RC.Elements.size()
602 OS << "\nnamespace {\n";
603 OS << " const TargetRegisterClass* const RegisterClasses[] = {\n";
604 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i)
605 OS << " &" << getQualifiedName(RegisterClasses[i].TheDef)
609 // Emit register sub-registers / super-registers, aliases...
610 std::map<Record*, std::set<Record*>, LessRecord> RegisterSubRegs;
611 std::map<Record*, std::set<Record*>, LessRecord> RegisterSuperRegs;
612 std::map<Record*, std::set<Record*>, LessRecord> RegisterAliases;
613 typedef std::map<Record*, std::vector<int64_t>, LessRecord> DwarfRegNumsMapTy;
614 DwarfRegNumsMapTy DwarfRegNums;
616 const std::vector<CodeGenRegister> &Regs = Target.getRegisters();
618 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
619 Record *R = Regs[i].TheDef;
620 std::vector<Record*> LI = Regs[i].TheDef->getValueAsListOfDefs("Aliases");
621 // Add information that R aliases all of the elements in the list... and
622 // that everything in the list aliases R.
623 for (unsigned j = 0, e = LI.size(); j != e; ++j) {
625 if (RegisterAliases[R].count(Reg))
626 errs() << "Warning: register alias between " << getQualifiedName(R)
627 << " and " << getQualifiedName(Reg)
628 << " specified multiple times!\n";
629 RegisterAliases[R].insert(Reg);
631 if (RegisterAliases[Reg].count(R))
632 errs() << "Warning: register alias between " << getQualifiedName(R)
633 << " and " << getQualifiedName(Reg)
634 << " specified multiple times!\n";
635 RegisterAliases[Reg].insert(R);
639 // Process sub-register sets.
640 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
641 Record *R = Regs[i].TheDef;
642 std::vector<Record*> LI = Regs[i].TheDef->getValueAsListOfDefs("SubRegs");
643 // Process sub-register set and add aliases information.
644 for (unsigned j = 0, e = LI.size(); j != e; ++j) {
645 Record *SubReg = LI[j];
646 if (RegisterSubRegs[R].count(SubReg))
647 errs() << "Warning: register " << getQualifiedName(SubReg)
648 << " specified as a sub-register of " << getQualifiedName(R)
649 << " multiple times!\n";
650 addSubSuperReg(R, SubReg, RegisterSubRegs, RegisterSuperRegs,
655 // Print the SubregHashTable, a simple quadratically probed
656 // hash table for determining if a register is a subregister
657 // of another register.
658 unsigned NumSubRegs = 0;
659 std::map<Record*, unsigned> RegNo;
660 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
661 RegNo[Regs[i].TheDef] = i;
662 NumSubRegs += RegisterSubRegs[Regs[i].TheDef].size();
665 unsigned SubregHashTableSize = 2 * NextPowerOf2(2 * NumSubRegs);
666 unsigned* SubregHashTable = new unsigned[2 * SubregHashTableSize];
667 std::fill(SubregHashTable, SubregHashTable + 2 * SubregHashTableSize, ~0U);
669 unsigned hashMisses = 0;
671 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
672 Record* R = Regs[i].TheDef;
673 for (std::set<Record*>::iterator I = RegisterSubRegs[R].begin(),
674 E = RegisterSubRegs[R].end(); I != E; ++I) {
676 // We have to increase the indices of both registers by one when
677 // computing the hash because, in the generated code, there
678 // will be an extra empty slot at register 0.
679 size_t index = ((i+1) + (RegNo[RJ]+1) * 37) & (SubregHashTableSize-1);
680 unsigned ProbeAmt = 2;
681 while (SubregHashTable[index*2] != ~0U &&
682 SubregHashTable[index*2+1] != ~0U) {
683 index = (index + ProbeAmt) & (SubregHashTableSize-1);
689 SubregHashTable[index*2] = i;
690 SubregHashTable[index*2+1] = RegNo[RJ];
694 OS << "\n\n // Number of hash collisions: " << hashMisses << "\n";
696 if (SubregHashTableSize) {
697 std::string Namespace = Regs[0].TheDef->getValueAsString("Namespace");
699 OS << " const unsigned SubregHashTable[] = { ";
700 for (unsigned i = 0; i < SubregHashTableSize - 1; ++i) {
702 // Insert spaces for nice formatting.
705 if (SubregHashTable[2*i] != ~0U) {
706 OS << getQualifiedName(Regs[SubregHashTable[2*i]].TheDef) << ", "
707 << getQualifiedName(Regs[SubregHashTable[2*i+1]].TheDef) << ", \n";
709 OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister, \n";
713 unsigned Idx = SubregHashTableSize*2-2;
714 if (SubregHashTable[Idx] != ~0U) {
716 << getQualifiedName(Regs[SubregHashTable[Idx]].TheDef) << ", "
717 << getQualifiedName(Regs[SubregHashTable[Idx+1]].TheDef) << " };\n";
719 OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister };\n";
722 OS << " const unsigned SubregHashTableSize = "
723 << SubregHashTableSize << ";\n";
725 OS << " const unsigned SubregHashTable[] = { ~0U, ~0U };\n"
726 << " const unsigned SubregHashTableSize = 1;\n";
729 delete [] SubregHashTable;
732 // Print the AliasHashTable, a simple quadratically probed
733 // hash table for determining if a register aliases another register.
734 unsigned NumAliases = 0;
736 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
737 RegNo[Regs[i].TheDef] = i;
738 NumAliases += RegisterAliases[Regs[i].TheDef].size();
741 unsigned AliasesHashTableSize = 2 * NextPowerOf2(2 * NumAliases);
742 unsigned* AliasesHashTable = new unsigned[2 * AliasesHashTableSize];
743 std::fill(AliasesHashTable, AliasesHashTable + 2 * AliasesHashTableSize, ~0U);
747 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
748 Record* R = Regs[i].TheDef;
749 for (std::set<Record*>::iterator I = RegisterAliases[R].begin(),
750 E = RegisterAliases[R].end(); I != E; ++I) {
752 // We have to increase the indices of both registers by one when
753 // computing the hash because, in the generated code, there
754 // will be an extra empty slot at register 0.
755 size_t index = ((i+1) + (RegNo[RJ]+1) * 37) & (AliasesHashTableSize-1);
756 unsigned ProbeAmt = 2;
757 while (AliasesHashTable[index*2] != ~0U &&
758 AliasesHashTable[index*2+1] != ~0U) {
759 index = (index + ProbeAmt) & (AliasesHashTableSize-1);
765 AliasesHashTable[index*2] = i;
766 AliasesHashTable[index*2+1] = RegNo[RJ];
770 OS << "\n\n // Number of hash collisions: " << hashMisses << "\n";
772 if (AliasesHashTableSize) {
773 std::string Namespace = Regs[0].TheDef->getValueAsString("Namespace");
775 OS << " const unsigned AliasesHashTable[] = { ";
776 for (unsigned i = 0; i < AliasesHashTableSize - 1; ++i) {
778 // Insert spaces for nice formatting.
781 if (AliasesHashTable[2*i] != ~0U) {
782 OS << getQualifiedName(Regs[AliasesHashTable[2*i]].TheDef) << ", "
783 << getQualifiedName(Regs[AliasesHashTable[2*i+1]].TheDef) << ", \n";
785 OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister, \n";
789 unsigned Idx = AliasesHashTableSize*2-2;
790 if (AliasesHashTable[Idx] != ~0U) {
792 << getQualifiedName(Regs[AliasesHashTable[Idx]].TheDef) << ", "
793 << getQualifiedName(Regs[AliasesHashTable[Idx+1]].TheDef) << " };\n";
795 OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister };\n";
798 OS << " const unsigned AliasesHashTableSize = "
799 << AliasesHashTableSize << ";\n";
801 OS << " const unsigned AliasesHashTable[] = { ~0U, ~0U };\n"
802 << " const unsigned AliasesHashTableSize = 1;\n";
805 delete [] AliasesHashTable;
807 if (!RegisterAliases.empty())
808 OS << "\n\n // Register Alias Sets...\n";
810 // Emit the empty alias list
811 OS << " const unsigned Empty_AliasSet[] = { 0 };\n";
812 // Loop over all of the registers which have aliases, emitting the alias list
814 for (std::map<Record*, std::set<Record*>, LessRecord >::iterator
815 I = RegisterAliases.begin(), E = RegisterAliases.end(); I != E; ++I) {
816 if (I->second.empty())
818 OS << " const unsigned " << I->first->getName() << "_AliasSet[] = { ";
819 for (std::set<Record*>::iterator ASI = I->second.begin(),
820 E = I->second.end(); ASI != E; ++ASI)
821 OS << getQualifiedName(*ASI) << ", ";
825 if (!RegisterSubRegs.empty())
826 OS << "\n\n // Register Sub-registers Sets...\n";
828 // Emit the empty sub-registers list
829 OS << " const unsigned Empty_SubRegsSet[] = { 0 };\n";
830 // Loop over all of the registers which have sub-registers, emitting the
831 // sub-registers list to memory.
832 for (std::map<Record*, std::set<Record*>, LessRecord>::iterator
833 I = RegisterSubRegs.begin(), E = RegisterSubRegs.end(); I != E; ++I) {
834 if (I->second.empty())
836 OS << " const unsigned " << I->first->getName() << "_SubRegsSet[] = { ";
837 std::vector<Record*> SubRegsVector;
838 for (std::set<Record*>::iterator ASI = I->second.begin(),
839 E = I->second.end(); ASI != E; ++ASI)
840 SubRegsVector.push_back(*ASI);
841 RegisterSorter RS(RegisterSubRegs);
842 std::stable_sort(SubRegsVector.begin(), SubRegsVector.end(), RS);
843 for (unsigned i = 0, e = SubRegsVector.size(); i != e; ++i)
844 OS << getQualifiedName(SubRegsVector[i]) << ", ";
848 if (!RegisterSuperRegs.empty())
849 OS << "\n\n // Register Super-registers Sets...\n";
851 // Emit the empty super-registers list
852 OS << " const unsigned Empty_SuperRegsSet[] = { 0 };\n";
853 // Loop over all of the registers which have super-registers, emitting the
854 // super-registers list to memory.
855 for (std::map<Record*, std::set<Record*>, LessRecord >::iterator
856 I = RegisterSuperRegs.begin(), E = RegisterSuperRegs.end(); I != E; ++I) {
857 if (I->second.empty())
859 OS << " const unsigned " << I->first->getName() << "_SuperRegsSet[] = { ";
861 std::vector<Record*> SuperRegsVector;
862 for (std::set<Record*>::iterator ASI = I->second.begin(),
863 E = I->second.end(); ASI != E; ++ASI)
864 SuperRegsVector.push_back(*ASI);
865 RegisterSorter RS(RegisterSubRegs);
866 std::stable_sort(SuperRegsVector.begin(), SuperRegsVector.end(), RS);
867 for (unsigned i = 0, e = SuperRegsVector.size(); i != e; ++i)
868 OS << getQualifiedName(SuperRegsVector[i]) << ", ";
872 OS<<"\n const TargetRegisterDesc RegisterDescriptors[] = { // Descriptors\n";
873 OS << " { \"NOREG\",\t0,\t0,\t0 },\n";
875 // Now that register alias and sub-registers sets have been emitted, emit the
876 // register descriptors now.
877 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
878 const CodeGenRegister &Reg = Regs[i];
880 OS << Reg.getName() << "\",\t";
881 if (!RegisterAliases[Reg.TheDef].empty())
882 OS << Reg.getName() << "_AliasSet,\t";
884 OS << "Empty_AliasSet,\t";
885 if (!RegisterSubRegs[Reg.TheDef].empty())
886 OS << Reg.getName() << "_SubRegsSet,\t";
888 OS << "Empty_SubRegsSet,\t";
889 if (!RegisterSuperRegs[Reg.TheDef].empty())
890 OS << Reg.getName() << "_SuperRegsSet },\n";
892 OS << "Empty_SuperRegsSet },\n";
894 OS << " };\n"; // End of register descriptors...
896 // Emit SubRegIndex names, skipping 0
897 const std::vector<Record*> SubRegIndices = Target.getSubRegIndices();
898 OS << "\n const char *const SubRegIndexTable[] = { \"";
899 for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) {
900 OS << SubRegIndices[i]->getName();
905 OS << "}\n\n"; // End of anonymous namespace...
907 std::string ClassName = Target.getName() + "GenRegisterInfo";
909 // Calculate the mapping of subregister+index pairs to physical registers.
910 RegisterMaps RegMaps;
912 // Emit the subregister + index mapping function based on the information
914 OS << "unsigned " << ClassName
915 << "::getSubReg(unsigned RegNo, unsigned Index) const {\n"
916 << " switch (RegNo) {\n"
917 << " default:\n return 0;\n";
918 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
919 RegisterMaps::SubRegMap &SRM = RegMaps.inferSubRegIndices(Regs[i].TheDef);
922 OS << " case " << getQualifiedName(Regs[i].TheDef) << ":\n";
923 OS << " switch (Index) {\n";
924 OS << " default: return 0;\n";
925 for (RegisterMaps::SubRegMap::const_iterator ii = SRM.begin(),
926 ie = SRM.end(); ii != ie; ++ii)
927 OS << " case " << getQualifiedName(ii->first)
928 << ": return " << getQualifiedName(ii->second) << ";\n";
929 OS << " };\n" << " break;\n";
932 OS << " return 0;\n";
935 OS << "unsigned " << ClassName
936 << "::getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const {\n"
937 << " switch (RegNo) {\n"
938 << " default:\n return 0;\n";
939 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
940 RegisterMaps::SubRegMap &SRM = RegMaps.SubReg[Regs[i].TheDef];
943 OS << " case " << getQualifiedName(Regs[i].TheDef) << ":\n";
944 for (RegisterMaps::SubRegMap::const_iterator ii = SRM.begin(),
945 ie = SRM.end(); ii != ie; ++ii)
946 OS << " if (SubRegNo == " << getQualifiedName(ii->second)
947 << ") return " << getQualifiedName(ii->first) << ";\n";
948 OS << " return 0;\n";
951 OS << " return 0;\n";
954 // Emit composeSubRegIndices
955 RegMaps.computeComposites();
956 OS << "unsigned " << ClassName
957 << "::composeSubRegIndices(unsigned IdxA, unsigned IdxB) const {\n"
958 << " switch (IdxA) {\n"
959 << " default:\n return IdxB;\n";
960 for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) {
962 for (unsigned j = 0; j != e; ++j) {
963 if (Record *Comp = RegMaps.Composite.lookup(
964 std::make_pair(SubRegIndices[i], SubRegIndices[j]))) {
966 OS << " case " << getQualifiedName(SubRegIndices[i])
967 << ": switch(IdxB) {\n default: return IdxB;\n";
970 OS << " case " << getQualifiedName(SubRegIndices[j])
971 << ": return " << getQualifiedName(Comp) << ";\n";
979 // Emit the constructor of the class...
980 OS << ClassName << "::" << ClassName
981 << "(int CallFrameSetupOpcode, int CallFrameDestroyOpcode)\n"
982 << " : TargetRegisterInfo(RegisterDescriptors, " << Regs.size()+1
983 << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n"
984 << " SubRegIndexTable,\n"
985 << " CallFrameSetupOpcode, CallFrameDestroyOpcode,\n"
986 << " SubregHashTable, SubregHashTableSize,\n"
987 << " AliasesHashTable, AliasesHashTableSize) {\n"
990 // Collect all information about dwarf register numbers
992 // First, just pull all provided information to the map
993 unsigned maxLength = 0;
994 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
995 Record *Reg = Regs[i].TheDef;
996 std::vector<int64_t> RegNums = Reg->getValueAsListOfInts("DwarfNumbers");
997 maxLength = std::max((size_t)maxLength, RegNums.size());
998 if (DwarfRegNums.count(Reg))
999 errs() << "Warning: DWARF numbers for register " << getQualifiedName(Reg)
1000 << "specified multiple times\n";
1001 DwarfRegNums[Reg] = RegNums;
1004 // Now we know maximal length of number list. Append -1's, where needed
1005 for (DwarfRegNumsMapTy::iterator
1006 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I)
1007 for (unsigned i = I->second.size(), e = maxLength; i != e; ++i)
1008 I->second.push_back(-1);
1010 // Emit information about the dwarf register numbers.
1011 OS << "int " << ClassName << "::getDwarfRegNumFull(unsigned RegNum, "
1012 << "unsigned Flavour) const {\n"
1013 << " switch (Flavour) {\n"
1015 << " assert(0 && \"Unknown DWARF flavour\");\n"
1018 for (unsigned i = 0, e = maxLength; i != e; ++i) {
1019 OS << " case " << i << ":\n"
1020 << " switch (RegNum) {\n"
1022 << " assert(0 && \"Invalid RegNum\");\n"
1025 // Sort by name to get a stable order.
1028 for (DwarfRegNumsMapTy::iterator
1029 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
1030 int RegNo = I->second[i];
1032 OS << " case " << getQualifiedName(I->first) << ":\n"
1033 << " return " << RegNo << ";\n";
1035 OS << " case " << getQualifiedName(I->first) << ":\n"
1036 << " assert(0 && \"Invalid register for this mode\");\n"
1044 OS << "} // End llvm namespace \n";