1 //===- RegisterInfoEmitter.cpp - Generate a Register File Desc. -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend is responsible for emitting a description of a target
11 // register file for a code generator. It uses instances of the Register,
12 // RegisterAliases, and RegisterClass classes to gather this information.
14 //===----------------------------------------------------------------------===//
16 #include "RegisterInfoEmitter.h"
17 #include "CodeGenTarget.h"
18 #include "CodeGenRegisters.h"
19 #include "SequenceToOffsetTable.h"
20 #include "llvm/TableGen/Error.h"
21 #include "llvm/TableGen/Record.h"
22 #include "llvm/ADT/BitVector.h"
23 #include "llvm/ADT/StringExtras.h"
24 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/ADT/Twine.h"
26 #include "llvm/Support/Format.h"
31 // runEnums - Print out enum values for all of the registers.
32 void RegisterInfoEmitter::runEnums(raw_ostream &OS,
33 CodeGenTarget &Target, CodeGenRegBank &Bank) {
34 const std::vector<CodeGenRegister*> &Registers = Bank.getRegisters();
36 // Register enums are stored as uint16_t in the tables. Make sure we'll fit.
37 assert(Registers.size() <= 0xffff && "Too many regs to fit in tables");
39 std::string Namespace = Registers[0]->TheDef->getValueAsString("Namespace");
41 EmitSourceFileHeader("Target Register Enum Values", OS);
43 OS << "\n#ifdef GET_REGINFO_ENUM\n";
44 OS << "#undef GET_REGINFO_ENUM\n";
46 OS << "namespace llvm {\n\n";
48 OS << "class MCRegisterClass;\n"
49 << "extern const MCRegisterClass " << Namespace
50 << "MCRegisterClasses[];\n\n";
52 if (!Namespace.empty())
53 OS << "namespace " << Namespace << " {\n";
54 OS << "enum {\n NoRegister,\n";
56 for (unsigned i = 0, e = Registers.size(); i != e; ++i)
57 OS << " " << Registers[i]->getName() << " = " <<
58 Registers[i]->EnumValue << ",\n";
59 assert(Registers.size() == Registers[Registers.size()-1]->EnumValue &&
60 "Register enum value mismatch!");
61 OS << " NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n";
63 if (!Namespace.empty())
66 ArrayRef<CodeGenRegisterClass*> RegisterClasses = Bank.getRegClasses();
67 if (!RegisterClasses.empty()) {
69 // RegisterClass enums are stored as uint16_t in the tables.
70 assert(RegisterClasses.size() <= 0xffff &&
71 "Too many register classes to fit in tables");
73 OS << "\n// Register classes\n";
74 if (!Namespace.empty())
75 OS << "namespace " << Namespace << " {\n";
77 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
79 OS << " " << RegisterClasses[i]->getName() << "RegClassID";
83 if (!Namespace.empty())
87 const std::vector<Record*> RegAltNameIndices = Target.getRegAltNameIndices();
88 // If the only definition is the default NoRegAltName, we don't need to
90 if (RegAltNameIndices.size() > 1) {
91 OS << "\n// Register alternate name indices\n";
92 if (!Namespace.empty())
93 OS << "namespace " << Namespace << " {\n";
95 for (unsigned i = 0, e = RegAltNameIndices.size(); i != e; ++i)
96 OS << " " << RegAltNameIndices[i]->getName() << ",\t// " << i << "\n";
97 OS << " NUM_TARGET_REG_ALT_NAMES = " << RegAltNameIndices.size() << "\n";
99 if (!Namespace.empty())
103 ArrayRef<CodeGenSubRegIndex*> SubRegIndices = Bank.getSubRegIndices();
104 if (!SubRegIndices.empty()) {
105 OS << "\n// Subregister indices\n";
106 std::string Namespace =
107 SubRegIndices[0]->getNamespace();
108 if (!Namespace.empty())
109 OS << "namespace " << Namespace << " {\n";
110 OS << "enum {\n NoSubRegister,\n";
111 for (unsigned i = 0, e = Bank.getNumNamedIndices(); i != e; ++i)
112 OS << " " << SubRegIndices[i]->getName() << ",\t// " << i+1 << "\n";
113 OS << " NUM_TARGET_NAMED_SUBREGS\n};\n";
114 if (!Namespace.empty())
118 OS << "} // End llvm namespace \n";
119 OS << "#endif // GET_REGINFO_ENUM\n\n";
122 void RegisterInfoEmitter::
123 EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank,
124 const std::string &ClassName) {
125 unsigned NumRCs = RegBank.getRegClasses().size();
126 unsigned NumSets = RegBank.getNumRegPressureSets();
128 OS << "/// Get the weight in units of pressure for this register class.\n"
129 << "const RegClassWeight &" << ClassName << "::\n"
130 << "getRegClassWeight(const TargetRegisterClass *RC) const {\n"
131 << " static const RegClassWeight RCWeightTable[] = {\n";
132 for (unsigned i = 0, e = NumRCs; i != e; ++i) {
133 const CodeGenRegisterClass &RC = *RegBank.getRegClasses()[i];
134 const CodeGenRegister::Set &Regs = RC.getMembers();
138 std::vector<unsigned> RegUnits;
139 RC.buildRegUnitSet(RegUnits);
140 OS << " {" << (*Regs.begin())->getWeight(RegBank)
141 << ", " << RegBank.getRegUnitSetWeight(RegUnits);
143 OS << "}, \t// " << RC.getName() << "\n";
146 << " return RCWeightTable[RC->getID()];\n"
150 << "// Get the number of dimensions of register pressure.\n"
151 << "unsigned " << ClassName << "::getNumRegPressureSets() const {\n"
152 << " return " << NumSets << ";\n}\n\n";
154 OS << "// Get the name of this register unit pressure set.\n"
155 << "const char *" << ClassName << "::\n"
156 << "getRegPressureSetName(unsigned Idx) const {\n"
157 << " static const char *PressureNameTable[] = {\n";
158 for (unsigned i = 0; i < NumSets; ++i ) {
159 OS << " \"" << RegBank.getRegPressureSet(i).Name << "\",\n";
162 << " return PressureNameTable[Idx];\n"
165 OS << "// Get the register unit pressure limit for this dimension.\n"
166 << "// This limit must be adjusted dynamically for reserved registers.\n"
167 << "unsigned " << ClassName << "::\n"
168 << "getRegPressureSetLimit(unsigned Idx) const {\n"
169 << " static const unsigned PressureLimitTable[] = {\n";
170 for (unsigned i = 0; i < NumSets; ++i ) {
171 const RegUnitSet &RegUnits = RegBank.getRegPressureSet(i);
172 OS << " " << RegBank.getRegUnitSetWeight(RegUnits.Units)
173 << ", \t// " << i << ": " << RegUnits.Name << "\n";
176 << " return PressureLimitTable[Idx];\n"
179 OS << "/// Get the dimensions of register pressure "
180 << "impacted by this register class.\n"
181 << "/// Returns a -1 terminated array of pressure set IDs\n"
182 << "const int* " << ClassName << "::\n"
183 << "getRegClassPressureSets(const TargetRegisterClass *RC) const {\n"
184 << " static const int RCSetsTable[] = {\n ";
185 std::vector<unsigned> RCSetStarts(NumRCs);
186 for (unsigned i = 0, StartIdx = 0, e = NumRCs; i != e; ++i) {
187 RCSetStarts[i] = StartIdx;
188 ArrayRef<unsigned> PSetIDs = RegBank.getRCPressureSetIDs(i);
189 for (ArrayRef<unsigned>::iterator PSetI = PSetIDs.begin(),
190 PSetE = PSetIDs.end(); PSetI != PSetE; ++PSetI) {
191 OS << *PSetI << ", ";
194 OS << "-1, \t// " << RegBank.getRegClasses()[i]->getName() << "\n ";
198 OS << " static const unsigned RCSetStartTable[] = {\n ";
199 for (unsigned i = 0, e = NumRCs; i != e; ++i) {
200 OS << RCSetStarts[i] << ",";
203 << " unsigned SetListStart = RCSetStartTable[RC->getID()];\n"
204 << " return &RCSetsTable[SetListStart];\n"
209 RegisterInfoEmitter::EmitRegMappingTables(raw_ostream &OS,
210 const std::vector<CodeGenRegister*> &Regs,
212 // Collect all information about dwarf register numbers
213 typedef std::map<Record*, std::vector<int64_t>, LessRecord> DwarfRegNumsMapTy;
214 DwarfRegNumsMapTy DwarfRegNums;
216 // First, just pull all provided information to the map
217 unsigned maxLength = 0;
218 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
219 Record *Reg = Regs[i]->TheDef;
220 std::vector<int64_t> RegNums = Reg->getValueAsListOfInts("DwarfNumbers");
221 maxLength = std::max((size_t)maxLength, RegNums.size());
222 if (DwarfRegNums.count(Reg))
223 PrintWarning(Reg->getLoc(), Twine("DWARF numbers for register ") +
224 getQualifiedName(Reg) + "specified multiple times");
225 DwarfRegNums[Reg] = RegNums;
231 // Now we know maximal length of number list. Append -1's, where needed
232 for (DwarfRegNumsMapTy::iterator
233 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I)
234 for (unsigned i = I->second.size(), e = maxLength; i != e; ++i)
235 I->second.push_back(-1);
237 std::string Namespace = Regs[0]->TheDef->getValueAsString("Namespace");
239 OS << "// " << Namespace << " Dwarf<->LLVM register mappings.\n";
241 // Emit reverse information about the dwarf register numbers.
242 for (unsigned j = 0; j < 2; ++j) {
243 for (unsigned i = 0, e = maxLength; i != e; ++i) {
244 OS << "extern const MCRegisterInfo::DwarfLLVMRegPair " << Namespace;
245 OS << (j == 0 ? "DwarfFlavour" : "EHFlavour");
246 OS << i << "Dwarf2L[]";
251 // Store the mapping sorted by the LLVM reg num so lookup can be done
252 // with a binary search.
253 std::map<uint64_t, Record*> Dwarf2LMap;
254 for (DwarfRegNumsMapTy::iterator
255 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
256 int DwarfRegNo = I->second[i];
259 Dwarf2LMap[DwarfRegNo] = I->first;
262 for (std::map<uint64_t, Record*>::iterator
263 I = Dwarf2LMap.begin(), E = Dwarf2LMap.end(); I != E; ++I)
264 OS << " { " << I->first << "U, " << getQualifiedName(I->second)
272 // We have to store the size in a const global, it's used in multiple
274 OS << "extern const unsigned " << Namespace
275 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i << "Dwarf2LSize";
277 OS << " = sizeof(" << Namespace
278 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i
279 << "Dwarf2L)/sizeof(MCRegisterInfo::DwarfLLVMRegPair);\n\n";
285 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
286 Record *Reg = Regs[i]->TheDef;
287 const RecordVal *V = Reg->getValue("DwarfAlias");
288 if (!V || !V->getValue())
291 DefInit *DI = dynamic_cast<DefInit*>(V->getValue());
292 Record *Alias = DI->getDef();
293 DwarfRegNums[Reg] = DwarfRegNums[Alias];
296 // Emit information about the dwarf register numbers.
297 for (unsigned j = 0; j < 2; ++j) {
298 for (unsigned i = 0, e = maxLength; i != e; ++i) {
299 OS << "extern const MCRegisterInfo::DwarfLLVMRegPair " << Namespace;
300 OS << (j == 0 ? "DwarfFlavour" : "EHFlavour");
301 OS << i << "L2Dwarf[]";
304 // Store the mapping sorted by the Dwarf reg num so lookup can be done
305 // with a binary search.
306 for (DwarfRegNumsMapTy::iterator
307 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
308 int RegNo = I->second[i];
309 if (RegNo == -1) // -1 is the default value, don't emit a mapping.
312 OS << " { " << getQualifiedName(I->first) << ", " << RegNo
320 // We have to store the size in a const global, it's used in multiple
322 OS << "extern const unsigned " << Namespace
323 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i << "L2DwarfSize";
325 OS << " = sizeof(" << Namespace
326 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i
327 << "L2Dwarf)/sizeof(MCRegisterInfo::DwarfLLVMRegPair);\n\n";
335 RegisterInfoEmitter::EmitRegMapping(raw_ostream &OS,
336 const std::vector<CodeGenRegister*> &Regs,
338 // Emit the initializer so the tables from EmitRegMappingTables get wired up
339 // to the MCRegisterInfo object.
340 unsigned maxLength = 0;
341 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
342 Record *Reg = Regs[i]->TheDef;
343 maxLength = std::max((size_t)maxLength,
344 Reg->getValueAsListOfInts("DwarfNumbers").size());
350 std::string Namespace = Regs[0]->TheDef->getValueAsString("Namespace");
352 // Emit reverse information about the dwarf register numbers.
353 for (unsigned j = 0; j < 2; ++j) {
356 OS << "DwarfFlavour";
361 << " llvm_unreachable(\"Unknown DWARF flavour\");\n";
363 for (unsigned i = 0, e = maxLength; i != e; ++i) {
364 OS << " case " << i << ":\n";
369 raw_string_ostream(Tmp) << Namespace
370 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i
372 OS << "mapDwarfRegsToLLVMRegs(" << Tmp << ", " << Tmp << "Size, ";
383 // Emit information about the dwarf register numbers.
384 for (unsigned j = 0; j < 2; ++j) {
387 OS << "DwarfFlavour";
392 << " llvm_unreachable(\"Unknown DWARF flavour\");\n";
394 for (unsigned i = 0, e = maxLength; i != e; ++i) {
395 OS << " case " << i << ":\n";
400 raw_string_ostream(Tmp) << Namespace
401 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i
403 OS << "mapLLVMRegsToDwarfRegs(" << Tmp << ", " << Tmp << "Size, ";
415 // Print a BitVector as a sequence of hex numbers using a little-endian mapping.
416 // Width is the number of bits per hex number.
417 static void printBitVectorAsHex(raw_ostream &OS,
418 const BitVector &Bits,
420 assert(Width <= 32 && "Width too large");
421 unsigned Digits = (Width + 3) / 4;
422 for (unsigned i = 0, e = Bits.size(); i < e; i += Width) {
424 for (unsigned j = 0; j != Width && i + j != e; ++j)
425 Value |= Bits.test(i + j) << j;
426 OS << format("0x%0*x, ", Digits, Value);
430 // Helper to emit a set of bits into a constant byte array.
431 class BitVectorEmitter {
434 void add(unsigned v) {
435 if (v >= Values.size())
436 Values.resize(((v/8)+1)*8); // Round up to the next byte.
440 void print(raw_ostream &OS) {
441 printBitVectorAsHex(OS, Values, 8);
445 static void printRegister(raw_ostream &OS, const CodeGenRegister *Reg) {
446 OS << getQualifiedName(Reg->TheDef);
449 static void printSimpleValueType(raw_ostream &OS, MVT::SimpleValueType VT) {
450 OS << getEnumName(VT);
453 static void printSubRegIndex(raw_ostream &OS, const CodeGenSubRegIndex *Idx) {
454 OS << Idx->getQualifiedName();
457 // Differentially encoded register and regunit lists allow for better
458 // compression on regular register banks. The sequence is computed from the
459 // differential list as:
462 // out[n+1] = out[n] + diff[n]; // n = 0, 1, ...
464 // The initial value depends on the specific list. The list is terminated by a
465 // 0 differential which means we can't encode repeated elements.
467 typedef SmallVector<uint16_t, 4> DiffVec;
469 // Differentially encode a sequence of numbers into V. The starting value and
470 // terminating 0 are not added to V, so it will have the same size as List.
472 DiffVec &diffEncode(DiffVec &V, unsigned InitVal, ArrayRef<unsigned> List) {
473 assert(V.empty() && "Clear DiffVec before diffEncode.");
474 uint16_t Val = uint16_t(InitVal);
475 for (unsigned i = 0; i != List.size(); ++i) {
476 uint16_t Cur = List[i];
477 V.push_back(Cur - Val);
483 static void printDiff16(raw_ostream &OS, uint16_t Val) {
488 // runMCDesc - Print out MC register descriptions.
491 RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target,
492 CodeGenRegBank &RegBank) {
493 EmitSourceFileHeader("MC Register Information", OS);
495 OS << "\n#ifdef GET_REGINFO_MC_DESC\n";
496 OS << "#undef GET_REGINFO_MC_DESC\n";
498 const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters();
500 // The lists of sub-registers, super-registers, and overlaps all go in the
501 // same array. That allows us to share suffixes.
502 typedef std::vector<const CodeGenRegister*> RegVec;
503 SmallVector<RegVec, 4> SubRegLists(Regs.size());
504 SmallVector<RegVec, 4> OverlapLists(Regs.size());
505 SequenceToOffsetTable<RegVec, CodeGenRegister::Less> RegSeqs;
507 // Differentially encoded lists.
508 SequenceToOffsetTable<DiffVec> DiffSeqs;
509 SmallVector<DiffVec, 4> RegUnitLists(Regs.size());
510 SmallVector<unsigned, 4> RegUnitInitScale(Regs.size());
512 SequenceToOffsetTable<std::string> RegStrings;
514 // Precompute register lists for the SequenceToOffsetTable.
515 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
516 const CodeGenRegister *Reg = Regs[i];
518 RegStrings.add(Reg->getName());
520 // Compute the ordered sub-register list.
521 SetVector<const CodeGenRegister*> SR;
522 Reg->addSubRegsPreOrder(SR, RegBank);
523 RegVec &SubRegList = SubRegLists[i];
524 SubRegList.assign(SR.begin(), SR.end());
525 RegSeqs.add(SubRegList);
527 // Super-registers are already computed.
528 const RegVec &SuperRegList = Reg->getSuperRegs();
529 RegSeqs.add(SuperRegList);
531 // The list of overlaps doesn't need to have any particular order, except
532 // Reg itself must be the first element. Pick an ordering that has one of
533 // the other lists as a suffix.
534 RegVec &OverlapList = OverlapLists[i];
535 const RegVec &Suffix = SubRegList.size() > SuperRegList.size() ?
536 SubRegList : SuperRegList;
537 CodeGenRegister::Set Omit(Suffix.begin(), Suffix.end());
539 // First element is Reg itself.
540 OverlapList.push_back(Reg);
543 // Any elements not in Suffix.
544 CodeGenRegister::Set OSet;
545 Reg->computeOverlaps(OSet, RegBank);
546 std::set_difference(OSet.begin(), OSet.end(),
547 Omit.begin(), Omit.end(),
548 std::back_inserter(OverlapList),
549 CodeGenRegister::Less());
551 // Finally, Suffix itself.
552 OverlapList.insert(OverlapList.end(), Suffix.begin(), Suffix.end());
553 RegSeqs.add(OverlapList);
555 // Differentially encode the register unit list, seeded by register number.
556 // First compute a scale factor that allows more diff-lists to be reused:
561 // A scale factor of 2 allows D0 and D1 to share a diff-list. The initial
562 // value for the differential decoder is the register number multiplied by
565 // Check the neighboring registers for arithmetic progressions.
566 unsigned ScaleA = ~0u, ScaleB = ~0u;
567 ArrayRef<unsigned> RUs = Reg->getNativeRegUnits();
568 if (i > 0 && Regs[i-1]->getNativeRegUnits().size() == RUs.size())
569 ScaleB = RUs.front() - Regs[i-1]->getNativeRegUnits().front();
570 if (i+1 != Regs.size() &&
571 Regs[i+1]->getNativeRegUnits().size() == RUs.size())
572 ScaleA = Regs[i+1]->getNativeRegUnits().front() - RUs.front();
573 unsigned Scale = std::min(ScaleB, ScaleA);
574 // Default the scale to 0 if it can't be encoded in 4 bits.
577 RegUnitInitScale[i] = Scale;
578 DiffSeqs.add(diffEncode(RegUnitLists[i], Scale * Reg->EnumValue, RUs));
581 // Compute the final layout of the sequence table.
585 OS << "namespace llvm {\n\n";
587 const std::string &TargetName = Target.getName();
589 // Emit the shared table of register lists.
590 OS << "extern const uint16_t " << TargetName << "RegLists[] = {\n";
591 RegSeqs.emit(OS, printRegister);
594 // Emit the shared table of differential lists.
595 OS << "extern const uint16_t " << TargetName << "RegDiffLists[] = {\n";
596 DiffSeqs.emit(OS, printDiff16);
599 // Emit the string table.
601 OS << "extern const char " << TargetName << "RegStrings[] = {\n";
602 RegStrings.emit(OS, printChar);
605 OS << "extern const MCRegisterDesc " << TargetName
606 << "RegDesc[] = { // Descriptors\n";
607 OS << " { " << RegStrings.get("") << ", 0, 0, 0, 0 },\n";
609 // Emit the register descriptors now.
610 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
611 const CodeGenRegister *Reg = Regs[i];
612 OS << " { " << RegStrings.get(Reg->getName()) << ", "
613 << RegSeqs.get(OverlapLists[i]) << ", "
614 << RegSeqs.get(SubRegLists[i]) << ", "
615 << RegSeqs.get(Reg->getSuperRegs()) << ", "
616 << (DiffSeqs.get(RegUnitLists[i])*16 + RegUnitInitScale[i]) << " },\n";
618 OS << "};\n\n"; // End of register descriptors...
620 // Emit the table of register unit roots. Each regunit has one or two root
622 OS << "extern const uint16_t " << TargetName << "RegUnitRoots[][2] = {\n";
623 for (unsigned i = 0, e = RegBank.getNumNativeRegUnits(); i != e; ++i) {
624 ArrayRef<const CodeGenRegister*> Roots = RegBank.getRegUnit(i).getRoots();
625 assert(!Roots.empty() && "All regunits must have a root register.");
626 assert(Roots.size() <= 2 && "More than two roots not supported yet.");
627 OS << " { " << getQualifiedName(Roots.front()->TheDef);
628 for (unsigned r = 1; r != Roots.size(); ++r)
629 OS << ", " << getQualifiedName(Roots[r]->TheDef);
634 ArrayRef<CodeGenRegisterClass*> RegisterClasses = RegBank.getRegClasses();
636 // Loop over all of the register classes... emitting each one.
637 OS << "namespace { // Register classes...\n";
639 // Emit the register enum value arrays for each RegisterClass
640 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
641 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
642 ArrayRef<Record*> Order = RC.getOrder();
644 // Give the register class a legal C name if it's anonymous.
645 std::string Name = RC.getName();
647 // Emit the register list now.
648 OS << " // " << Name << " Register Class...\n"
649 << " const uint16_t " << Name
651 for (unsigned i = 0, e = Order.size(); i != e; ++i) {
652 Record *Reg = Order[i];
653 OS << getQualifiedName(Reg) << ", ";
657 OS << " // " << Name << " Bit set.\n"
658 << " const uint8_t " << Name
660 BitVectorEmitter BVE;
661 for (unsigned i = 0, e = Order.size(); i != e; ++i) {
662 Record *Reg = Order[i];
663 BVE.add(Target.getRegBank().getReg(Reg)->EnumValue);
671 OS << "extern const MCRegisterClass " << TargetName
672 << "MCRegisterClasses[] = {\n";
674 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
675 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
677 // Asserts to make sure values will fit in table assuming types from
679 assert((RC.SpillSize/8) <= 0xffff && "SpillSize too large.");
680 assert((RC.SpillAlignment/8) <= 0xffff && "SpillAlignment too large.");
681 assert(RC.CopyCost >= -128 && RC.CopyCost <= 127 && "Copy cost too large.");
683 OS << " { " << '\"' << RC.getName() << "\", "
684 << RC.getName() << ", " << RC.getName() << "Bits, "
685 << RC.getOrder().size() << ", sizeof(" << RC.getName() << "Bits), "
686 << RC.getQualifiedName() + "RegClassID" << ", "
687 << RC.SpillSize/8 << ", "
688 << RC.SpillAlignment/8 << ", "
689 << RC.CopyCost << ", "
690 << RC.Allocatable << " },\n";
695 // Emit the data table for getSubReg().
696 ArrayRef<CodeGenSubRegIndex*> SubRegIndices = RegBank.getSubRegIndices();
697 if (SubRegIndices.size()) {
698 OS << "const uint16_t " << TargetName << "SubRegTable[]["
699 << SubRegIndices.size() << "] = {\n";
700 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
701 const CodeGenRegister::SubRegMap &SRM = Regs[i]->getSubRegs();
702 OS << " /* " << Regs[i]->TheDef->getName() << " */\n";
708 for (unsigned j = 0, je = SubRegIndices.size(); j != je; ++j) {
709 // FIXME: We really should keep this to 80 columns...
710 CodeGenRegister::SubRegMap::const_iterator SubReg =
711 SRM.find(SubRegIndices[j]);
712 if (SubReg != SRM.end())
713 OS << getQualifiedName(SubReg->second->TheDef);
719 OS << "}" << (i != e ? "," : "") << "\n";
722 OS << "const uint16_t *get" << TargetName
723 << "SubRegTable() {\n return (const uint16_t *)" << TargetName
724 << "SubRegTable;\n}\n\n";
727 EmitRegMappingTables(OS, Regs, false);
729 // Emit Reg encoding table
730 OS << "extern const uint16_t " << TargetName;
731 OS << "RegEncodingTable[] = {\n";
732 // Add entry for NoRegister
734 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
735 Record *Reg = Regs[i]->TheDef;
736 BitsInit *BI = Reg->getValueAsBitsInit("HWEncoding");
738 for (unsigned b = 0, be = BI->getNumBits(); b != be; ++b) {
739 if (BitInit *B = dynamic_cast<BitInit*>(BI->getBit(b)))
740 Value |= (uint64_t)B->getValue() << b;
742 OS << " " << Value << ",\n";
744 OS << "};\n"; // End of HW encoding table
746 // MCRegisterInfo initialization routine.
747 OS << "static inline void Init" << TargetName
748 << "MCRegisterInfo(MCRegisterInfo *RI, unsigned RA, "
749 << "unsigned DwarfFlavour = 0, unsigned EHFlavour = 0) {\n";
750 OS << " RI->InitMCRegisterInfo(" << TargetName << "RegDesc, "
751 << Regs.size()+1 << ", RA, " << TargetName << "MCRegisterClasses, "
752 << RegisterClasses.size() << ", "
753 << TargetName << "RegUnitRoots, "
754 << RegBank.getNumNativeRegUnits() << ", "
755 << TargetName << "RegLists, "
756 << TargetName << "RegDiffLists, "
757 << TargetName << "RegStrings, ";
758 if (SubRegIndices.size() != 0)
759 OS << "(uint16_t*)" << TargetName << "SubRegTable, "
760 << SubRegIndices.size() << ",\n";
764 OS << " " << TargetName << "RegEncodingTable);\n\n";
766 EmitRegMapping(OS, Regs, false);
770 OS << "} // End llvm namespace \n";
771 OS << "#endif // GET_REGINFO_MC_DESC\n\n";
775 RegisterInfoEmitter::runTargetHeader(raw_ostream &OS, CodeGenTarget &Target,
776 CodeGenRegBank &RegBank) {
777 EmitSourceFileHeader("Register Information Header Fragment", OS);
779 OS << "\n#ifdef GET_REGINFO_HEADER\n";
780 OS << "#undef GET_REGINFO_HEADER\n";
782 const std::string &TargetName = Target.getName();
783 std::string ClassName = TargetName + "GenRegisterInfo";
785 OS << "#include \"llvm/Target/TargetRegisterInfo.h\"\n\n";
787 OS << "namespace llvm {\n\n";
789 OS << "struct " << ClassName << " : public TargetRegisterInfo {\n"
790 << " explicit " << ClassName
791 << "(unsigned RA, unsigned D = 0, unsigned E = 0);\n"
792 << " virtual bool needsStackRealignment(const MachineFunction &) const\n"
793 << " { return false; }\n";
794 if (!RegBank.getSubRegIndices().empty()) {
795 OS << " unsigned composeSubRegIndices(unsigned, unsigned) const;\n"
796 << " const TargetRegisterClass *"
797 "getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const;\n";
799 OS << " const RegClassWeight &getRegClassWeight("
800 << "const TargetRegisterClass *RC) const;\n"
801 << " unsigned getNumRegPressureSets() const;\n"
802 << " const char *getRegPressureSetName(unsigned Idx) const;\n"
803 << " unsigned getRegPressureSetLimit(unsigned Idx) const;\n"
804 << " const int *getRegClassPressureSets("
805 << "const TargetRegisterClass *RC) const;\n"
808 ArrayRef<CodeGenRegisterClass*> RegisterClasses = RegBank.getRegClasses();
810 if (!RegisterClasses.empty()) {
811 OS << "namespace " << RegisterClasses[0]->Namespace
812 << " { // Register classes\n";
814 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
815 const CodeGenRegisterClass &RC = *RegisterClasses[i];
816 const std::string &Name = RC.getName();
818 // Output the extern for the instance.
819 OS << " extern const TargetRegisterClass " << Name << "RegClass;\n";
821 OS << "} // end of namespace " << TargetName << "\n\n";
823 OS << "} // End llvm namespace \n";
824 OS << "#endif // GET_REGINFO_HEADER\n\n";
828 // runTargetDesc - Output the target register and register file descriptions.
831 RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
832 CodeGenRegBank &RegBank){
833 EmitSourceFileHeader("Target Register and Register Classes Information", OS);
835 OS << "\n#ifdef GET_REGINFO_TARGET_DESC\n";
836 OS << "#undef GET_REGINFO_TARGET_DESC\n";
838 OS << "namespace llvm {\n\n";
840 // Get access to MCRegisterClass data.
841 OS << "extern const MCRegisterClass " << Target.getName()
842 << "MCRegisterClasses[];\n";
844 // Start out by emitting each of the register classes.
845 ArrayRef<CodeGenRegisterClass*> RegisterClasses = RegBank.getRegClasses();
846 ArrayRef<CodeGenSubRegIndex*> SubRegIndices = RegBank.getSubRegIndices();
848 // Collect all registers belonging to any allocatable class.
849 std::set<Record*> AllocatableRegs;
851 // Collect allocatable registers.
852 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
853 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
854 ArrayRef<Record*> Order = RC.getOrder();
857 AllocatableRegs.insert(Order.begin(), Order.end());
860 // Build a shared array of value types.
861 SequenceToOffsetTable<std::vector<MVT::SimpleValueType> > VTSeqs;
862 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc)
863 VTSeqs.add(RegisterClasses[rc]->VTs);
865 OS << "\nstatic const MVT::SimpleValueType VTLists[] = {\n";
866 VTSeqs.emit(OS, printSimpleValueType, "MVT::Other");
869 // Emit SubRegIndex names, skipping 0
870 OS << "\nstatic const char *const SubRegIndexTable[] = { \"";
871 for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) {
872 OS << SubRegIndices[i]->getName();
878 // Emit names of the anonymous subreg indices.
879 unsigned NamedIndices = RegBank.getNumNamedIndices();
880 if (SubRegIndices.size() > NamedIndices) {
882 for (unsigned i = NamedIndices, e = SubRegIndices.size(); i != e; ++i) {
883 OS << "\n " << SubRegIndices[i]->getName() << " = " << i+1;
891 // Now that all of the structs have been emitted, emit the instances.
892 if (!RegisterClasses.empty()) {
893 OS << "\nstatic const TargetRegisterClass *const "
894 << "NullRegClasses[] = { NULL };\n\n";
896 // Emit register class bit mask tables. The first bit mask emitted for a
897 // register class, RC, is the set of sub-classes, including RC itself.
899 // If RC has super-registers, also create a list of subreg indices and bit
900 // masks, (Idx, Mask). The bit mask has a bit for every superreg regclass,
901 // SuperRC, that satisfies:
903 // For all SuperReg in SuperRC: SuperReg:Idx in RC
905 // The 0-terminated list of subreg indices starts at:
907 // RC->getSuperRegIndices() = SuperRegIdxSeqs + ...
909 // The corresponding bitmasks follow the sub-class mask in memory. Each
910 // mask has RCMaskWords uint32_t entries.
912 // Every bit mask present in the list has at least one bit set.
914 // Compress the sub-reg index lists.
915 typedef std::vector<const CodeGenSubRegIndex*> IdxList;
916 SmallVector<IdxList, 8> SuperRegIdxLists(RegisterClasses.size());
917 SequenceToOffsetTable<IdxList> SuperRegIdxSeqs;
918 BitVector MaskBV(RegisterClasses.size());
920 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
921 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
922 OS << "static const uint32_t " << RC.getName() << "SubClassMask[] = {\n ";
923 printBitVectorAsHex(OS, RC.getSubClasses(), 32);
925 // Emit super-reg class masks for any relevant SubRegIndices that can
927 IdxList &SRIList = SuperRegIdxLists[rc];
928 for (unsigned sri = 0, sre = SubRegIndices.size(); sri != sre; ++sri) {
929 CodeGenSubRegIndex *Idx = SubRegIndices[sri];
931 RC.getSuperRegClasses(Idx, MaskBV);
934 SRIList.push_back(Idx);
936 printBitVectorAsHex(OS, MaskBV, 32);
937 OS << "// " << Idx->getName();
939 SuperRegIdxSeqs.add(SRIList);
943 OS << "static const uint16_t SuperRegIdxSeqs[] = {\n";
944 SuperRegIdxSeqs.layout();
945 SuperRegIdxSeqs.emit(OS, printSubRegIndex);
948 // Emit NULL terminated super-class lists.
949 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
950 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
951 ArrayRef<CodeGenRegisterClass*> Supers = RC.getSuperClasses();
953 // Skip classes without supers. We can reuse NullRegClasses.
957 OS << "static const TargetRegisterClass *const "
958 << RC.getName() << "Superclasses[] = {\n";
959 for (unsigned i = 0; i != Supers.size(); ++i)
960 OS << " &" << Supers[i]->getQualifiedName() << "RegClass,\n";
961 OS << " NULL\n};\n\n";
965 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
966 const CodeGenRegisterClass &RC = *RegisterClasses[i];
967 if (!RC.AltOrderSelect.empty()) {
968 OS << "\nstatic inline unsigned " << RC.getName()
969 << "AltOrderSelect(const MachineFunction &MF) {"
970 << RC.AltOrderSelect << "}\n\n"
971 << "static ArrayRef<uint16_t> " << RC.getName()
972 << "GetRawAllocationOrder(const MachineFunction &MF) {\n";
973 for (unsigned oi = 1 , oe = RC.getNumOrders(); oi != oe; ++oi) {
974 ArrayRef<Record*> Elems = RC.getOrder(oi);
975 if (!Elems.empty()) {
976 OS << " static const uint16_t AltOrder" << oi << "[] = {";
977 for (unsigned elem = 0; elem != Elems.size(); ++elem)
978 OS << (elem ? ", " : " ") << getQualifiedName(Elems[elem]);
982 OS << " const MCRegisterClass &MCR = " << Target.getName()
983 << "MCRegisterClasses[" << RC.getQualifiedName() + "RegClassID];\n"
984 << " const ArrayRef<uint16_t> Order[] = {\n"
985 << " makeArrayRef(MCR.begin(), MCR.getNumRegs()";
986 for (unsigned oi = 1, oe = RC.getNumOrders(); oi != oe; ++oi)
987 if (RC.getOrder(oi).empty())
988 OS << "),\n ArrayRef<uint16_t>(";
990 OS << "),\n makeArrayRef(AltOrder" << oi;
991 OS << ")\n };\n const unsigned Select = " << RC.getName()
992 << "AltOrderSelect(MF);\n assert(Select < " << RC.getNumOrders()
993 << ");\n return Order[Select];\n}\n";
997 // Now emit the actual value-initialized register class instances.
998 OS << "namespace " << RegisterClasses[0]->Namespace
999 << " { // Register class instances\n";
1001 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
1002 const CodeGenRegisterClass &RC = *RegisterClasses[i];
1003 OS << " extern const TargetRegisterClass "
1004 << RegisterClasses[i]->getName() << "RegClass = {\n "
1005 << '&' << Target.getName() << "MCRegisterClasses[" << RC.getName()
1006 << "RegClassID],\n "
1007 << "VTLists + " << VTSeqs.get(RC.VTs) << ",\n "
1008 << RC.getName() << "SubClassMask,\n SuperRegIdxSeqs + "
1009 << SuperRegIdxSeqs.get(SuperRegIdxLists[i]) << ",\n ";
1010 if (RC.getSuperClasses().empty())
1011 OS << "NullRegClasses,\n ";
1013 OS << RC.getName() << "Superclasses,\n ";
1014 if (RC.AltOrderSelect.empty())
1017 OS << RC.getName() << "GetRawAllocationOrder\n";
1024 OS << "\nnamespace {\n";
1025 OS << " const TargetRegisterClass* const RegisterClasses[] = {\n";
1026 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i)
1027 OS << " &" << RegisterClasses[i]->getQualifiedName()
1030 OS << "}\n"; // End of anonymous namespace...
1032 // Emit extra information about registers.
1033 const std::string &TargetName = Target.getName();
1034 OS << "\nstatic const TargetRegisterInfoDesc "
1035 << TargetName << "RegInfoDesc[] = { // Extra Descriptors\n";
1036 OS << " { 0, 0 },\n";
1038 const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters();
1039 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
1040 const CodeGenRegister &Reg = *Regs[i];
1042 OS << Reg.CostPerUse << ", "
1043 << int(AllocatableRegs.count(Reg.TheDef)) << " },\n";
1045 OS << "};\n"; // End of register descriptors...
1048 std::string ClassName = Target.getName() + "GenRegisterInfo";
1050 // Emit composeSubRegIndices
1051 if (!SubRegIndices.empty()) {
1052 OS << "unsigned " << ClassName
1053 << "::composeSubRegIndices(unsigned IdxA, unsigned IdxB) const {\n"
1054 << " switch (IdxA) {\n"
1055 << " default:\n return IdxB;\n";
1056 for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) {
1058 for (unsigned j = 0; j != e; ++j) {
1059 if (CodeGenSubRegIndex *Comp =
1060 SubRegIndices[i]->compose(SubRegIndices[j])) {
1062 OS << " case " << SubRegIndices[i]->getQualifiedName()
1063 << ": switch(IdxB) {\n default: return IdxB;\n";
1066 OS << " case " << SubRegIndices[j]->getQualifiedName()
1067 << ": return " << Comp->getQualifiedName() << ";\n";
1076 // Emit getSubClassWithSubReg.
1077 if (!SubRegIndices.empty()) {
1078 OS << "const TargetRegisterClass *" << ClassName
1079 << "::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx)"
1081 // Use the smallest type that can hold a regclass ID with room for a
1083 if (RegisterClasses.size() < UINT8_MAX)
1084 OS << " static const uint8_t Table[";
1085 else if (RegisterClasses.size() < UINT16_MAX)
1086 OS << " static const uint16_t Table[";
1088 throw "Too many register classes.";
1089 OS << RegisterClasses.size() << "][" << SubRegIndices.size() << "] = {\n";
1090 for (unsigned rci = 0, rce = RegisterClasses.size(); rci != rce; ++rci) {
1091 const CodeGenRegisterClass &RC = *RegisterClasses[rci];
1092 OS << " {\t// " << RC.getName() << "\n";
1093 for (unsigned sri = 0, sre = SubRegIndices.size(); sri != sre; ++sri) {
1094 CodeGenSubRegIndex *Idx = SubRegIndices[sri];
1095 if (CodeGenRegisterClass *SRC = RC.getSubClassWithSubReg(Idx))
1096 OS << " " << SRC->EnumValue + 1 << ",\t// " << Idx->getName()
1097 << " -> " << SRC->getName() << "\n";
1099 OS << " 0,\t// " << Idx->getName() << "\n";
1103 OS << " };\n assert(RC && \"Missing regclass\");\n"
1104 << " if (!Idx) return RC;\n --Idx;\n"
1105 << " assert(Idx < " << SubRegIndices.size() << " && \"Bad subreg\");\n"
1106 << " unsigned TV = Table[RC->getID()][Idx];\n"
1107 << " return TV ? getRegClass(TV - 1) : 0;\n}\n\n";
1110 EmitRegUnitPressure(OS, RegBank, ClassName);
1112 // Emit the constructor of the class...
1113 OS << "extern const MCRegisterDesc " << TargetName << "RegDesc[];\n";
1114 OS << "extern const uint16_t " << TargetName << "RegLists[];\n";
1115 OS << "extern const uint16_t " << TargetName << "RegDiffLists[];\n";
1116 OS << "extern const char " << TargetName << "RegStrings[];\n";
1117 OS << "extern const uint16_t " << TargetName << "RegUnitRoots[][2];\n";
1118 if (SubRegIndices.size() != 0)
1119 OS << "extern const uint16_t *get" << TargetName
1120 << "SubRegTable();\n";
1121 OS << "extern const uint16_t " << TargetName << "RegEncodingTable[];\n";
1123 EmitRegMappingTables(OS, Regs, true);
1125 OS << ClassName << "::\n" << ClassName
1126 << "(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour)\n"
1127 << " : TargetRegisterInfo(" << TargetName << "RegInfoDesc"
1128 << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n"
1129 << " SubRegIndexTable) {\n"
1130 << " InitMCRegisterInfo(" << TargetName << "RegDesc, "
1131 << Regs.size()+1 << ", RA,\n " << TargetName
1132 << "MCRegisterClasses, " << RegisterClasses.size() << ",\n"
1133 << " " << TargetName << "RegUnitRoots,\n"
1134 << " " << RegBank.getNumNativeRegUnits() << ",\n"
1135 << " " << TargetName << "RegLists,\n"
1136 << " " << TargetName << "RegDiffLists,\n"
1137 << " " << TargetName << "RegStrings,\n"
1139 if (SubRegIndices.size() != 0)
1140 OS << "get" << TargetName << "SubRegTable(), "
1141 << SubRegIndices.size() << ",\n";
1145 OS << " " << TargetName << "RegEncodingTable);\n\n";
1147 EmitRegMapping(OS, Regs, true);
1152 // Emit CalleeSavedRegs information.
1153 std::vector<Record*> CSRSets =
1154 Records.getAllDerivedDefinitions("CalleeSavedRegs");
1155 for (unsigned i = 0, e = CSRSets.size(); i != e; ++i) {
1156 Record *CSRSet = CSRSets[i];
1157 const SetTheory::RecVec *Regs = RegBank.getSets().expand(CSRSet);
1158 assert(Regs && "Cannot expand CalleeSavedRegs instance");
1160 // Emit the *_SaveList list of callee-saved registers.
1161 OS << "static const uint16_t " << CSRSet->getName()
1162 << "_SaveList[] = { ";
1163 for (unsigned r = 0, re = Regs->size(); r != re; ++r)
1164 OS << getQualifiedName((*Regs)[r]) << ", ";
1167 // Emit the *_RegMask bit mask of call-preserved registers.
1168 OS << "static const uint32_t " << CSRSet->getName()
1169 << "_RegMask[] = { ";
1170 printBitVectorAsHex(OS, RegBank.computeCoveredRegisters(*Regs), 32);
1175 OS << "} // End llvm namespace \n";
1176 OS << "#endif // GET_REGINFO_TARGET_DESC\n\n";
1179 void RegisterInfoEmitter::run(raw_ostream &OS) {
1180 CodeGenTarget Target(Records);
1181 CodeGenRegBank &RegBank = Target.getRegBank();
1182 RegBank.computeDerivedInfo();
1184 runEnums(OS, Target, RegBank);
1185 runMCDesc(OS, Target, RegBank);
1186 runTargetHeader(OS, Target, RegBank);
1187 runTargetDesc(OS, Target, RegBank);