1 //===- RegisterInfoEmitter.cpp - Generate a Register File Desc. -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend is responsible for emitting a description of a target
11 // register file for a code generator. It uses instances of the Register,
12 // RegisterAliases, and RegisterClass classes to gather this information.
14 //===----------------------------------------------------------------------===//
16 #include "RegisterInfoEmitter.h"
17 #include "CodeGenTarget.h"
18 #include "CodeGenRegisters.h"
20 #include "llvm/ADT/StringExtras.h"
21 #include "llvm/ADT/STLExtras.h"
26 // runEnums - Print out enum values for all of the registers.
27 void RegisterInfoEmitter::runEnums(raw_ostream &OS) {
28 CodeGenTarget Target(Records);
29 const std::vector<CodeGenRegister> &Registers = Target.getRegisters();
31 std::string Namespace = Registers[0].TheDef->getValueAsString("Namespace");
33 EmitSourceFileHeader("Target Register Enum Values", OS);
34 OS << "namespace llvm {\n\n";
36 if (!Namespace.empty())
37 OS << "namespace " << Namespace << " {\n";
38 OS << "enum {\n NoRegister,\n";
40 for (unsigned i = 0, e = Registers.size(); i != e; ++i)
41 OS << " " << Registers[i].getName() << " = " <<
42 Registers[i].EnumValue << ",\n";
43 assert(Registers.size() == Registers[Registers.size()-1].EnumValue &&
44 "Register enum value mismatch!");
45 OS << " NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n";
47 if (!Namespace.empty())
50 const std::vector<Record*> SubRegIndices = Target.getSubRegIndices();
51 if (!SubRegIndices.empty()) {
52 OS << "\n// Subregister indices\n";
53 Namespace = SubRegIndices[0]->getValueAsString("Namespace");
54 if (!Namespace.empty())
55 OS << "namespace " << Namespace << " {\n";
56 OS << "enum {\n NoSubRegister,\n";
57 for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i)
58 OS << " " << SubRegIndices[i]->getName() << ",\t// " << i+1 << "\n";
59 OS << " NUM_TARGET_NAMED_SUBREGS = " << SubRegIndices.size()+1 << "\n";
61 if (!Namespace.empty())
64 OS << "} // End llvm namespace \n";
67 void RegisterInfoEmitter::runHeader(raw_ostream &OS) {
68 EmitSourceFileHeader("Register Information Header Fragment", OS);
69 CodeGenTarget Target(Records);
70 const std::string &TargetName = Target.getName();
71 std::string ClassName = TargetName + "GenRegisterInfo";
73 OS << "#include \"llvm/Target/TargetRegisterInfo.h\"\n";
74 OS << "#include <string>\n\n";
76 OS << "namespace llvm {\n\n";
78 OS << "struct " << ClassName << " : public TargetRegisterInfo {\n"
79 << " explicit " << ClassName
80 << "(int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);\n"
81 << " virtual int getDwarfRegNumFull(unsigned RegNum, "
82 << "unsigned Flavour) const;\n"
83 << " virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0;\n"
84 << " virtual bool needsStackRealignment(const MachineFunction &) const\n"
85 << " { return false; }\n"
86 << " unsigned getSubReg(unsigned RegNo, unsigned Index) const;\n"
87 << " unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const;\n"
88 << " unsigned composeSubRegIndices(unsigned, unsigned) const;\n"
91 const std::vector<CodeGenRegisterClass> &RegisterClasses =
92 Target.getRegisterClasses();
94 if (!RegisterClasses.empty()) {
95 OS << "namespace " << RegisterClasses[0].Namespace
96 << " { // Register classes\n";
99 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
101 OS << " " << RegisterClasses[i].getName() << "RegClassID";
106 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
107 const std::string &Name = RegisterClasses[i].getName();
109 // Output the register class definition.
110 OS << " struct " << Name << "Class : public TargetRegisterClass {\n"
111 << " " << Name << "Class();\n"
112 << RegisterClasses[i].MethodProtos << " };\n";
114 // Output the extern for the instance.
115 OS << " extern " << Name << "Class\t" << Name << "RegClass;\n";
116 // Output the extern for the pointer to the instance (should remove).
117 OS << " static TargetRegisterClass * const "<< Name <<"RegisterClass = &"
118 << Name << "RegClass;\n";
120 OS << "} // end of namespace " << TargetName << "\n\n";
122 OS << "} // End llvm namespace \n";
125 static void addSuperReg(Record *R, Record *S,
126 std::map<Record*, std::set<Record*>, LessRecord> &SubRegs,
127 std::map<Record*, std::set<Record*>, LessRecord> &SuperRegs,
128 std::map<Record*, std::set<Record*>, LessRecord> &Aliases) {
130 errs() << "Error: recursive sub-register relationship between"
131 << " register " << getQualifiedName(R)
132 << " and its sub-registers?\n";
135 if (!SuperRegs[R].insert(S).second)
137 SubRegs[S].insert(R);
138 Aliases[R].insert(S);
139 Aliases[S].insert(R);
140 if (SuperRegs.count(S))
141 for (std::set<Record*>::iterator I = SuperRegs[S].begin(),
142 E = SuperRegs[S].end(); I != E; ++I)
143 addSuperReg(R, *I, SubRegs, SuperRegs, Aliases);
146 static void addSubSuperReg(Record *R, Record *S,
147 std::map<Record*, std::set<Record*>, LessRecord> &SubRegs,
148 std::map<Record*, std::set<Record*>, LessRecord> &SuperRegs,
149 std::map<Record*, std::set<Record*>, LessRecord> &Aliases) {
151 errs() << "Error: recursive sub-register relationship between"
152 << " register " << getQualifiedName(R)
153 << " and its sub-registers?\n";
157 if (!SubRegs[R].insert(S).second)
159 addSuperReg(S, R, SubRegs, SuperRegs, Aliases);
160 Aliases[R].insert(S);
161 Aliases[S].insert(R);
162 if (SubRegs.count(S))
163 for (std::set<Record*>::iterator I = SubRegs[S].begin(),
164 E = SubRegs[S].end(); I != E; ++I)
165 addSubSuperReg(R, *I, SubRegs, SuperRegs, Aliases);
168 struct RegisterMaps {
169 // Map SubRegIndex -> Register
170 typedef std::map<Record*, Record*, LessRecord> SubRegMap;
171 // Map Register -> SubRegMap
172 typedef std::map<Record*, SubRegMap> SubRegMaps;
175 SubRegMap &inferSubRegIndices(Record *Reg, CodeGenTarget &);
177 // Composite SubRegIndex instances.
178 // Map (SubRegIndex,SubRegIndex) -> SubRegIndex
179 typedef DenseMap<std::pair<Record*,Record*>,Record*> CompositeMap;
180 CompositeMap Composite;
182 // Compute SubRegIndex compositions after inferSubRegIndices has run on all
184 void computeComposites();
187 // Calculate all subregindices for Reg. Loopy subregs cause infinite recursion.
188 RegisterMaps::SubRegMap &RegisterMaps::inferSubRegIndices(Record *Reg,
189 CodeGenTarget &Target) {
190 SubRegMap &SRM = SubReg[Reg];
193 std::vector<Record*> SubRegs = Reg->getValueAsListOfDefs("SubRegs");
194 std::vector<Record*> Indices = Reg->getValueAsListOfDefs("SubRegIndices");
195 if (SubRegs.size() != Indices.size())
196 throw "Register " + Reg->getName() + " SubRegIndices doesn't match SubRegs";
198 // First insert the direct subregs and make sure they are fully indexed.
199 for (unsigned i = 0, e = SubRegs.size(); i != e; ++i) {
200 if (!SRM.insert(std::make_pair(Indices[i], SubRegs[i])).second)
201 throw "SubRegIndex " + Indices[i]->getName()
202 + " appears twice in Register " + Reg->getName();
203 inferSubRegIndices(SubRegs[i], Target);
206 // Keep track of inherited subregs and how they can be reached.
207 // Register -> (SubRegIndex, SubRegIndex)
208 typedef std::map<Record*, std::pair<Record*,Record*>, LessRecord> OrphanMap;
211 // Clone inherited subregs. Here the order is important - earlier subregs take
213 for (unsigned i = 0, e = SubRegs.size(); i != e; ++i) {
214 SubRegMap &M = SubReg[SubRegs[i]];
215 for (SubRegMap::iterator si = M.begin(), se = M.end(); si != se; ++si)
216 if (!SRM.insert(*si).second)
217 Orphans[si->second] = std::make_pair(Indices[i], si->first);
220 // Finally process the composites.
221 ListInit *Comps = Reg->getValueAsListInit("CompositeIndices");
222 for (unsigned i = 0, e = Comps->size(); i != e; ++i) {
223 DagInit *Pat = dynamic_cast<DagInit*>(Comps->getElement(i));
225 throw "Invalid dag '" + Comps->getElement(i)->getAsString()
226 + "' in CompositeIndices";
227 DefInit *BaseIdxInit = dynamic_cast<DefInit*>(Pat->getOperator());
228 if (!BaseIdxInit || !BaseIdxInit->getDef()->isSubClassOf("SubRegIndex"))
229 throw "Invalid SubClassIndex in " + Pat->getAsString();
231 // Resolve list of subreg indices into R2.
233 for (DagInit::const_arg_iterator di = Pat->arg_begin(),
234 de = Pat->arg_end(); di != de; ++di) {
235 DefInit *IdxInit = dynamic_cast<DefInit*>(*di);
236 if (!IdxInit || !IdxInit->getDef()->isSubClassOf("SubRegIndex"))
237 throw "Invalid SubClassIndex in " + Pat->getAsString();
238 SubRegMap::const_iterator ni = SubReg[R2].find(IdxInit->getDef());
239 if (ni == SubReg[R2].end())
240 throw "Composite " + Pat->getAsString() + " refers to bad index in "
245 // Insert composite index. Allow overriding inherited indices etc.
246 SRM[BaseIdxInit->getDef()] = R2;
248 // R2 is now directly addressable, no longer an orphan.
252 // Now Orphans contains the inherited subregisters without a direct index.
253 // Create inferred indexes for all missing entries.
254 for (OrphanMap::iterator I = Orphans.begin(), E = Orphans.end(); I != E;
256 Record *&Comp = Composite[I->second];
258 Comp = Target.createSubRegIndex(I->second.first->getName() + "_then_" +
259 I->second.second->getName());
260 SRM[Comp] = I->first;
266 void RegisterMaps::computeComposites() {
267 for (SubRegMaps::const_iterator sri = SubReg.begin(), sre = SubReg.end();
269 Record *Reg1 = sri->first;
270 const SubRegMap &SRM1 = sri->second;
271 for (SubRegMap::const_iterator i1 = SRM1.begin(), e1 = SRM1.end();
273 Record *Idx1 = i1->first;
274 Record *Reg2 = i1->second;
275 // Ignore identity compositions.
278 // If Reg2 has no subregs, Idx1 doesn't compose.
279 if (!SubReg.count(Reg2))
281 const SubRegMap &SRM2 = SubReg[Reg2];
282 // Try composing Idx1 with another SubRegIndex.
283 for (SubRegMap::const_iterator i2 = SRM2.begin(), e2 = SRM2.end();
285 std::pair<Record*,Record*> IdxPair(Idx1, i2->first);
286 Record *Reg3 = i2->second;
287 // OK Reg1:IdxPair == Reg3. Find the index with Reg:Idx == Reg3.
288 for (SubRegMap::const_iterator i1d = SRM1.begin(), e1d = SRM1.end();
290 // Ignore identity compositions.
293 if (i1d->second == Reg3) {
294 std::pair<CompositeMap::iterator,bool> Ins =
295 Composite.insert(std::make_pair(IdxPair, i1d->first));
296 // Conflicting composition? Emit a warning but allow it.
297 if (!Ins.second && Ins.first->second != i1d->first) {
298 errs() << "Warning: SubRegIndex " << getQualifiedName(Idx1)
299 << " and " << getQualifiedName(IdxPair.second)
300 << " compose ambiguously as "
301 << getQualifiedName(Ins.first->second) << " or "
302 << getQualifiedName(i1d->first) << "\n";
310 // We don't care about the difference between (Idx1, Idx2) -> Idx2 and invalid
311 // compositions, so remove any mappings of that form.
312 for (CompositeMap::iterator i = Composite.begin(), e = Composite.end();
314 CompositeMap::iterator j = i;
316 if (j->first.second == j->second)
321 class RegisterSorter {
323 std::map<Record*, std::set<Record*>, LessRecord> &RegisterSubRegs;
326 RegisterSorter(std::map<Record*, std::set<Record*>, LessRecord> &RS)
327 : RegisterSubRegs(RS) {}
329 bool operator()(Record *RegA, Record *RegB) {
330 // B is sub-register of A.
331 return RegisterSubRegs.count(RegA) && RegisterSubRegs[RegA].count(RegB);
335 // RegisterInfoEmitter::run - Main register file description emitter.
337 void RegisterInfoEmitter::run(raw_ostream &OS) {
338 CodeGenTarget Target(Records);
339 EmitSourceFileHeader("Register Information Source Fragment", OS);
341 OS << "namespace llvm {\n\n";
343 // Start out by emitting each of the register classes... to do this, we build
344 // a set of registers which belong to a register class, this is to ensure that
345 // each register is only in a single register class.
347 const std::vector<CodeGenRegisterClass> &RegisterClasses =
348 Target.getRegisterClasses();
350 // Loop over all of the register classes... emitting each one.
351 OS << "namespace { // Register classes...\n";
353 // RegClassesBelongedTo - Keep track of which register classes each reg
355 std::multimap<Record*, const CodeGenRegisterClass*> RegClassesBelongedTo;
357 // Emit the register enum value arrays for each RegisterClass
358 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
359 const CodeGenRegisterClass &RC = RegisterClasses[rc];
361 // Give the register class a legal C name if it's anonymous.
362 std::string Name = RC.TheDef->getName();
364 // Emit the register list now.
365 OS << " // " << Name << " Register Class...\n"
366 << " static const unsigned " << Name
368 for (unsigned i = 0, e = RC.Elements.size(); i != e; ++i) {
369 Record *Reg = RC.Elements[i];
370 OS << getQualifiedName(Reg) << ", ";
372 // Keep track of which regclasses this register is in.
373 RegClassesBelongedTo.insert(std::make_pair(Reg, &RC));
378 // Emit the ValueType arrays for each RegisterClass
379 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
380 const CodeGenRegisterClass &RC = RegisterClasses[rc];
382 // Give the register class a legal C name if it's anonymous.
383 std::string Name = RC.TheDef->getName() + "VTs";
385 // Emit the register list now.
387 << " Register Class Value Types...\n"
388 << " static const EVT " << Name
390 for (unsigned i = 0, e = RC.VTs.size(); i != e; ++i)
391 OS << getEnumName(RC.VTs[i]) << ", ";
392 OS << "MVT::Other\n };\n\n";
394 OS << "} // end anonymous namespace\n\n";
396 // Now that all of the structs have been emitted, emit the instances.
397 if (!RegisterClasses.empty()) {
398 OS << "namespace " << RegisterClasses[0].Namespace
399 << " { // Register class instances\n";
400 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i)
401 OS << " " << RegisterClasses[i].getName() << "Class\t"
402 << RegisterClasses[i].getName() << "RegClass;\n";
404 std::map<unsigned, std::set<unsigned> > SuperClassMap;
405 std::map<unsigned, std::set<unsigned> > SuperRegClassMap;
408 unsigned NumSubRegIndices = Target.getSubRegIndices().size();
410 if (NumSubRegIndices) {
411 // Emit the sub-register classes for each RegisterClass
412 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
413 const CodeGenRegisterClass &RC = RegisterClasses[rc];
414 std::vector<Record*> SRC(NumSubRegIndices);
415 for (DenseMap<Record*,Record*>::const_iterator
416 i = RC.SubRegClasses.begin(),
417 e = RC.SubRegClasses.end(); i != e; ++i) {
419 unsigned idx = Target.getSubRegIndexNo(i->first);
420 SRC.at(idx-1) = i->second;
422 // Find the register class number of i->second for SuperRegClassMap.
423 for (unsigned rc2 = 0, e2 = RegisterClasses.size(); rc2 != e2; ++rc2) {
424 const CodeGenRegisterClass &RC2 = RegisterClasses[rc2];
425 if (RC2.TheDef == i->second) {
426 SuperRegClassMap[rc2].insert(rc);
432 // Give the register class a legal C name if it's anonymous.
433 std::string Name = RC.TheDef->getName();
436 << " Sub-register Classes...\n"
437 << " static const TargetRegisterClass* const "
438 << Name << "SubRegClasses[] = {\n ";
440 for (unsigned idx = 0; idx != NumSubRegIndices; ++idx) {
444 OS << "&" << getQualifiedName(SRC[idx]) << "RegClass";
451 // Emit the super-register classes for each RegisterClass
452 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
453 const CodeGenRegisterClass &RC = RegisterClasses[rc];
455 // Give the register class a legal C name if it's anonymous.
456 std::string Name = RC.TheDef->getName();
459 << " Super-register Classes...\n"
460 << " static const TargetRegisterClass* const "
461 << Name << "SuperRegClasses[] = {\n ";
464 std::map<unsigned, std::set<unsigned> >::iterator I =
465 SuperRegClassMap.find(rc);
466 if (I != SuperRegClassMap.end()) {
467 for (std::set<unsigned>::iterator II = I->second.begin(),
468 EE = I->second.end(); II != EE; ++II) {
469 const CodeGenRegisterClass &RC2 = RegisterClasses[*II];
472 OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
477 OS << (!Empty ? ", " : "") << "NULL";
481 // No subregindices in this target
482 OS << " static const TargetRegisterClass* const "
483 << "NullRegClasses[] = { NULL };\n\n";
486 // Emit the sub-classes array for each RegisterClass
487 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
488 const CodeGenRegisterClass &RC = RegisterClasses[rc];
490 // Give the register class a legal C name if it's anonymous.
491 std::string Name = RC.TheDef->getName();
494 << " Register Class sub-classes...\n"
495 << " static const TargetRegisterClass* const "
496 << Name << "Subclasses[] = {\n ";
499 for (unsigned rc2 = 0, e2 = RegisterClasses.size(); rc2 != e2; ++rc2) {
500 const CodeGenRegisterClass &RC2 = RegisterClasses[rc2];
502 // Sub-classes are used to determine if a virtual register can be used
503 // as an instruction operand, or if it must be copied first.
504 if (rc == rc2 || !RC.hasSubClass(&RC2)) continue;
506 if (!Empty) OS << ", ";
507 OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
510 std::map<unsigned, std::set<unsigned> >::iterator SCMI =
511 SuperClassMap.find(rc2);
512 if (SCMI == SuperClassMap.end()) {
513 SuperClassMap.insert(std::make_pair(rc2, std::set<unsigned>()));
514 SCMI = SuperClassMap.find(rc2);
516 SCMI->second.insert(rc);
519 OS << (!Empty ? ", " : "") << "NULL";
523 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
524 const CodeGenRegisterClass &RC = RegisterClasses[rc];
526 // Give the register class a legal C name if it's anonymous.
527 std::string Name = RC.TheDef->getName();
530 << " Register Class super-classes...\n"
531 << " static const TargetRegisterClass* const "
532 << Name << "Superclasses[] = {\n ";
535 std::map<unsigned, std::set<unsigned> >::iterator I =
536 SuperClassMap.find(rc);
537 if (I != SuperClassMap.end()) {
538 for (std::set<unsigned>::iterator II = I->second.begin(),
539 EE = I->second.end(); II != EE; ++II) {
540 const CodeGenRegisterClass &RC2 = RegisterClasses[*II];
541 if (!Empty) OS << ", ";
542 OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
547 OS << (!Empty ? ", " : "") << "NULL";
552 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
553 const CodeGenRegisterClass &RC = RegisterClasses[i];
554 OS << RC.MethodBodies << "\n";
555 OS << RC.getName() << "Class::" << RC.getName()
556 << "Class() : TargetRegisterClass("
557 << RC.getName() + "RegClassID" << ", "
558 << '\"' << RC.getName() << "\", "
559 << RC.getName() + "VTs" << ", "
560 << RC.getName() + "Subclasses" << ", "
561 << RC.getName() + "Superclasses" << ", "
562 << (NumSubRegIndices ? RC.getName() + "Sub" : std::string("Null"))
564 << (NumSubRegIndices ? RC.getName() + "Super" : std::string("Null"))
566 << RC.SpillSize/8 << ", "
567 << RC.SpillAlignment/8 << ", "
568 << RC.CopyCost << ", "
569 << RC.getName() << ", " << RC.getName() << " + " << RC.Elements.size()
576 OS << "\nnamespace {\n";
577 OS << " const TargetRegisterClass* const RegisterClasses[] = {\n";
578 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i)
579 OS << " &" << getQualifiedName(RegisterClasses[i].TheDef)
583 // Emit register sub-registers / super-registers, aliases...
584 std::map<Record*, std::set<Record*>, LessRecord> RegisterSubRegs;
585 std::map<Record*, std::set<Record*>, LessRecord> RegisterSuperRegs;
586 std::map<Record*, std::set<Record*>, LessRecord> RegisterAliases;
587 typedef std::map<Record*, std::vector<int64_t>, LessRecord> DwarfRegNumsMapTy;
588 DwarfRegNumsMapTy DwarfRegNums;
590 const std::vector<CodeGenRegister> &Regs = Target.getRegisters();
592 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
593 Record *R = Regs[i].TheDef;
594 std::vector<Record*> LI = Regs[i].TheDef->getValueAsListOfDefs("Aliases");
595 // Add information that R aliases all of the elements in the list... and
596 // that everything in the list aliases R.
597 for (unsigned j = 0, e = LI.size(); j != e; ++j) {
599 if (RegisterAliases[R].count(Reg))
600 errs() << "Warning: register alias between " << getQualifiedName(R)
601 << " and " << getQualifiedName(Reg)
602 << " specified multiple times!\n";
603 RegisterAliases[R].insert(Reg);
605 if (RegisterAliases[Reg].count(R))
606 errs() << "Warning: register alias between " << getQualifiedName(R)
607 << " and " << getQualifiedName(Reg)
608 << " specified multiple times!\n";
609 RegisterAliases[Reg].insert(R);
613 // Process sub-register sets.
614 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
615 Record *R = Regs[i].TheDef;
616 std::vector<Record*> LI = Regs[i].TheDef->getValueAsListOfDefs("SubRegs");
617 // Process sub-register set and add aliases information.
618 for (unsigned j = 0, e = LI.size(); j != e; ++j) {
619 Record *SubReg = LI[j];
620 if (RegisterSubRegs[R].count(SubReg))
621 errs() << "Warning: register " << getQualifiedName(SubReg)
622 << " specified as a sub-register of " << getQualifiedName(R)
623 << " multiple times!\n";
624 addSubSuperReg(R, SubReg, RegisterSubRegs, RegisterSuperRegs,
629 // Print the SubregHashTable, a simple quadratically probed
630 // hash table for determining if a register is a subregister
631 // of another register.
632 unsigned NumSubRegs = 0;
633 std::map<Record*, unsigned> RegNo;
634 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
635 RegNo[Regs[i].TheDef] = i;
636 NumSubRegs += RegisterSubRegs[Regs[i].TheDef].size();
639 unsigned SubregHashTableSize = 2 * NextPowerOf2(2 * NumSubRegs);
640 unsigned* SubregHashTable = new unsigned[2 * SubregHashTableSize];
641 std::fill(SubregHashTable, SubregHashTable + 2 * SubregHashTableSize, ~0U);
643 unsigned hashMisses = 0;
645 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
646 Record* R = Regs[i].TheDef;
647 for (std::set<Record*>::iterator I = RegisterSubRegs[R].begin(),
648 E = RegisterSubRegs[R].end(); I != E; ++I) {
650 // We have to increase the indices of both registers by one when
651 // computing the hash because, in the generated code, there
652 // will be an extra empty slot at register 0.
653 size_t index = ((i+1) + (RegNo[RJ]+1) * 37) & (SubregHashTableSize-1);
654 unsigned ProbeAmt = 2;
655 while (SubregHashTable[index*2] != ~0U &&
656 SubregHashTable[index*2+1] != ~0U) {
657 index = (index + ProbeAmt) & (SubregHashTableSize-1);
663 SubregHashTable[index*2] = i;
664 SubregHashTable[index*2+1] = RegNo[RJ];
668 OS << "\n\n // Number of hash collisions: " << hashMisses << "\n";
670 if (SubregHashTableSize) {
671 std::string Namespace = Regs[0].TheDef->getValueAsString("Namespace");
673 OS << " const unsigned SubregHashTable[] = { ";
674 for (unsigned i = 0; i < SubregHashTableSize - 1; ++i) {
676 // Insert spaces for nice formatting.
679 if (SubregHashTable[2*i] != ~0U) {
680 OS << getQualifiedName(Regs[SubregHashTable[2*i]].TheDef) << ", "
681 << getQualifiedName(Regs[SubregHashTable[2*i+1]].TheDef) << ", \n";
683 OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister, \n";
687 unsigned Idx = SubregHashTableSize*2-2;
688 if (SubregHashTable[Idx] != ~0U) {
690 << getQualifiedName(Regs[SubregHashTable[Idx]].TheDef) << ", "
691 << getQualifiedName(Regs[SubregHashTable[Idx+1]].TheDef) << " };\n";
693 OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister };\n";
696 OS << " const unsigned SubregHashTableSize = "
697 << SubregHashTableSize << ";\n";
699 OS << " const unsigned SubregHashTable[] = { ~0U, ~0U };\n"
700 << " const unsigned SubregHashTableSize = 1;\n";
703 delete [] SubregHashTable;
706 // Print the AliasHashTable, a simple quadratically probed
707 // hash table for determining if a register aliases another register.
708 unsigned NumAliases = 0;
710 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
711 RegNo[Regs[i].TheDef] = i;
712 NumAliases += RegisterAliases[Regs[i].TheDef].size();
715 unsigned AliasesHashTableSize = 2 * NextPowerOf2(2 * NumAliases);
716 unsigned* AliasesHashTable = new unsigned[2 * AliasesHashTableSize];
717 std::fill(AliasesHashTable, AliasesHashTable + 2 * AliasesHashTableSize, ~0U);
721 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
722 Record* R = Regs[i].TheDef;
723 for (std::set<Record*>::iterator I = RegisterAliases[R].begin(),
724 E = RegisterAliases[R].end(); I != E; ++I) {
726 // We have to increase the indices of both registers by one when
727 // computing the hash because, in the generated code, there
728 // will be an extra empty slot at register 0.
729 size_t index = ((i+1) + (RegNo[RJ]+1) * 37) & (AliasesHashTableSize-1);
730 unsigned ProbeAmt = 2;
731 while (AliasesHashTable[index*2] != ~0U &&
732 AliasesHashTable[index*2+1] != ~0U) {
733 index = (index + ProbeAmt) & (AliasesHashTableSize-1);
739 AliasesHashTable[index*2] = i;
740 AliasesHashTable[index*2+1] = RegNo[RJ];
744 OS << "\n\n // Number of hash collisions: " << hashMisses << "\n";
746 if (AliasesHashTableSize) {
747 std::string Namespace = Regs[0].TheDef->getValueAsString("Namespace");
749 OS << " const unsigned AliasesHashTable[] = { ";
750 for (unsigned i = 0; i < AliasesHashTableSize - 1; ++i) {
752 // Insert spaces for nice formatting.
755 if (AliasesHashTable[2*i] != ~0U) {
756 OS << getQualifiedName(Regs[AliasesHashTable[2*i]].TheDef) << ", "
757 << getQualifiedName(Regs[AliasesHashTable[2*i+1]].TheDef) << ", \n";
759 OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister, \n";
763 unsigned Idx = AliasesHashTableSize*2-2;
764 if (AliasesHashTable[Idx] != ~0U) {
766 << getQualifiedName(Regs[AliasesHashTable[Idx]].TheDef) << ", "
767 << getQualifiedName(Regs[AliasesHashTable[Idx+1]].TheDef) << " };\n";
769 OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister };\n";
772 OS << " const unsigned AliasesHashTableSize = "
773 << AliasesHashTableSize << ";\n";
775 OS << " const unsigned AliasesHashTable[] = { ~0U, ~0U };\n"
776 << " const unsigned AliasesHashTableSize = 1;\n";
779 delete [] AliasesHashTable;
781 if (!RegisterAliases.empty())
782 OS << "\n\n // Register Overlap Lists...\n";
784 // Emit an overlap list for all registers.
785 for (std::map<Record*, std::set<Record*>, LessRecord >::iterator
786 I = RegisterAliases.begin(), E = RegisterAliases.end(); I != E; ++I) {
787 OS << " const unsigned " << I->first->getName() << "_Overlaps[] = { "
788 << getQualifiedName(I->first) << ", ";
789 for (std::set<Record*>::iterator ASI = I->second.begin(),
790 E = I->second.end(); ASI != E; ++ASI)
791 OS << getQualifiedName(*ASI) << ", ";
795 if (!RegisterSubRegs.empty())
796 OS << "\n\n // Register Sub-registers Sets...\n";
798 // Emit the empty sub-registers list
799 OS << " const unsigned Empty_SubRegsSet[] = { 0 };\n";
800 // Loop over all of the registers which have sub-registers, emitting the
801 // sub-registers list to memory.
802 for (std::map<Record*, std::set<Record*>, LessRecord>::iterator
803 I = RegisterSubRegs.begin(), E = RegisterSubRegs.end(); I != E; ++I) {
804 if (I->second.empty())
806 OS << " const unsigned " << I->first->getName() << "_SubRegsSet[] = { ";
807 std::vector<Record*> SubRegsVector;
808 for (std::set<Record*>::iterator ASI = I->second.begin(),
809 E = I->second.end(); ASI != E; ++ASI)
810 SubRegsVector.push_back(*ASI);
811 RegisterSorter RS(RegisterSubRegs);
812 std::stable_sort(SubRegsVector.begin(), SubRegsVector.end(), RS);
813 for (unsigned i = 0, e = SubRegsVector.size(); i != e; ++i)
814 OS << getQualifiedName(SubRegsVector[i]) << ", ";
818 if (!RegisterSuperRegs.empty())
819 OS << "\n\n // Register Super-registers Sets...\n";
821 // Emit the empty super-registers list
822 OS << " const unsigned Empty_SuperRegsSet[] = { 0 };\n";
823 // Loop over all of the registers which have super-registers, emitting the
824 // super-registers list to memory.
825 for (std::map<Record*, std::set<Record*>, LessRecord >::iterator
826 I = RegisterSuperRegs.begin(), E = RegisterSuperRegs.end(); I != E; ++I) {
827 if (I->second.empty())
829 OS << " const unsigned " << I->first->getName() << "_SuperRegsSet[] = { ";
831 std::vector<Record*> SuperRegsVector;
832 for (std::set<Record*>::iterator ASI = I->second.begin(),
833 E = I->second.end(); ASI != E; ++ASI)
834 SuperRegsVector.push_back(*ASI);
835 RegisterSorter RS(RegisterSubRegs);
836 std::stable_sort(SuperRegsVector.begin(), SuperRegsVector.end(), RS);
837 for (unsigned i = 0, e = SuperRegsVector.size(); i != e; ++i)
838 OS << getQualifiedName(SuperRegsVector[i]) << ", ";
842 OS<<"\n const TargetRegisterDesc RegisterDescriptors[] = { // Descriptors\n";
843 OS << " { \"NOREG\",\t0,\t0,\t0,\t0 },\n";
845 // Now that register alias and sub-registers sets have been emitted, emit the
846 // register descriptors now.
847 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
848 const CodeGenRegister &Reg = Regs[i];
850 OS << Reg.getName() << "\",\t" << Reg.getName() << "_Overlaps,\t";
851 if (!RegisterSubRegs[Reg.TheDef].empty())
852 OS << Reg.getName() << "_SubRegsSet,\t";
854 OS << "Empty_SubRegsSet,\t";
855 if (!RegisterSuperRegs[Reg.TheDef].empty())
856 OS << Reg.getName() << "_SuperRegsSet,\t";
858 OS << "Empty_SuperRegsSet,\t";
859 OS << Reg.CostPerUse << " },\n";
861 OS << " };\n"; // End of register descriptors...
863 // Calculate the mapping of subregister+index pairs to physical registers.
864 // This will also create further anonymous indexes.
865 unsigned NamedIndices = Target.getSubRegIndices().size();
866 RegisterMaps RegMaps;
867 for (unsigned i = 0, e = Regs.size(); i != e; ++i)
868 RegMaps.inferSubRegIndices(Regs[i].TheDef, Target);
870 // Emit SubRegIndex names, skipping 0
871 const std::vector<Record*> SubRegIndices = Target.getSubRegIndices();
872 OS << "\n const char *const SubRegIndexTable[] = { \"";
873 for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) {
874 OS << SubRegIndices[i]->getName();
880 // Emit names of the anonymus subreg indexes.
881 if (SubRegIndices.size() > NamedIndices) {
883 for (unsigned i = NamedIndices, e = SubRegIndices.size(); i != e; ++i) {
884 OS << "\n " << SubRegIndices[i]->getName() << " = " << i+1;
890 OS << "}\n\n"; // End of anonymous namespace...
892 std::string ClassName = Target.getName() + "GenRegisterInfo";
894 // Emit the subregister + index mapping function based on the information
896 OS << "unsigned " << ClassName
897 << "::getSubReg(unsigned RegNo, unsigned Index) const {\n"
898 << " switch (RegNo) {\n"
899 << " default:\n return 0;\n";
900 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
901 RegisterMaps::SubRegMap &SRM = RegMaps.SubReg[Regs[i].TheDef];
904 OS << " case " << getQualifiedName(Regs[i].TheDef) << ":\n";
905 OS << " switch (Index) {\n";
906 OS << " default: return 0;\n";
907 for (RegisterMaps::SubRegMap::const_iterator ii = SRM.begin(),
908 ie = SRM.end(); ii != ie; ++ii)
909 OS << " case " << getQualifiedName(ii->first)
910 << ": return " << getQualifiedName(ii->second) << ";\n";
911 OS << " };\n" << " break;\n";
914 OS << " return 0;\n";
917 OS << "unsigned " << ClassName
918 << "::getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const {\n"
919 << " switch (RegNo) {\n"
920 << " default:\n return 0;\n";
921 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
922 RegisterMaps::SubRegMap &SRM = RegMaps.SubReg[Regs[i].TheDef];
925 OS << " case " << getQualifiedName(Regs[i].TheDef) << ":\n";
926 for (RegisterMaps::SubRegMap::const_iterator ii = SRM.begin(),
927 ie = SRM.end(); ii != ie; ++ii)
928 OS << " if (SubRegNo == " << getQualifiedName(ii->second)
929 << ") return " << getQualifiedName(ii->first) << ";\n";
930 OS << " return 0;\n";
933 OS << " return 0;\n";
936 // Emit composeSubRegIndices
937 RegMaps.computeComposites();
938 OS << "unsigned " << ClassName
939 << "::composeSubRegIndices(unsigned IdxA, unsigned IdxB) const {\n"
940 << " switch (IdxA) {\n"
941 << " default:\n return IdxB;\n";
942 for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) {
944 for (unsigned j = 0; j != e; ++j) {
945 if (Record *Comp = RegMaps.Composite.lookup(
946 std::make_pair(SubRegIndices[i], SubRegIndices[j]))) {
948 OS << " case " << getQualifiedName(SubRegIndices[i])
949 << ": switch(IdxB) {\n default: return IdxB;\n";
952 OS << " case " << getQualifiedName(SubRegIndices[j])
953 << ": return " << getQualifiedName(Comp) << ";\n";
961 // Emit the constructor of the class...
962 OS << ClassName << "::" << ClassName
963 << "(int CallFrameSetupOpcode, int CallFrameDestroyOpcode)\n"
964 << " : TargetRegisterInfo(RegisterDescriptors, " << Regs.size()+1
965 << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n"
966 << " SubRegIndexTable,\n"
967 << " CallFrameSetupOpcode, CallFrameDestroyOpcode,\n"
968 << " SubregHashTable, SubregHashTableSize,\n"
969 << " AliasesHashTable, AliasesHashTableSize) {\n"
972 // Collect all information about dwarf register numbers
974 // First, just pull all provided information to the map
975 unsigned maxLength = 0;
976 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
977 Record *Reg = Regs[i].TheDef;
978 std::vector<int64_t> RegNums = Reg->getValueAsListOfInts("DwarfNumbers");
979 maxLength = std::max((size_t)maxLength, RegNums.size());
980 if (DwarfRegNums.count(Reg))
981 errs() << "Warning: DWARF numbers for register " << getQualifiedName(Reg)
982 << "specified multiple times\n";
983 DwarfRegNums[Reg] = RegNums;
986 // Now we know maximal length of number list. Append -1's, where needed
987 for (DwarfRegNumsMapTy::iterator
988 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I)
989 for (unsigned i = I->second.size(), e = maxLength; i != e; ++i)
990 I->second.push_back(-1);
992 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
993 Record *Reg = Regs[i].TheDef;
994 const RecordVal *V = Reg->getValue("DwarfAlias");
995 if (!V || !V->getValue())
998 DefInit *DI = dynamic_cast<DefInit*>(V->getValue());
999 Record *Alias = DI->getDef();
1000 DwarfRegNums[Reg] = DwarfRegNums[Alias];
1003 // Emit information about the dwarf register numbers.
1004 OS << "int " << ClassName << "::getDwarfRegNumFull(unsigned RegNum, "
1005 << "unsigned Flavour) const {\n"
1006 << " switch (Flavour) {\n"
1008 << " assert(0 && \"Unknown DWARF flavour\");\n"
1011 for (unsigned i = 0, e = maxLength; i != e; ++i) {
1012 OS << " case " << i << ":\n"
1013 << " switch (RegNum) {\n"
1015 << " assert(0 && \"Invalid RegNum\");\n"
1018 // Sort by name to get a stable order.
1021 for (DwarfRegNumsMapTy::iterator
1022 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
1023 int RegNo = I->second[i];
1024 OS << " case " << getQualifiedName(I->first) << ":\n"
1025 << " return " << RegNo << ";\n";
1032 OS << "} // End llvm namespace \n";