1 //===- RegisterInfoEmitter.cpp - Generate a Register File Desc. -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend is responsible for emitting a description of a target
11 // register file for a code generator. It uses instances of the Register,
12 // RegisterAliases, and RegisterClass classes to gather this information.
14 //===----------------------------------------------------------------------===//
16 #include "RegisterInfoEmitter.h"
17 #include "CodeGenTarget.h"
18 #include "CodeGenRegisters.h"
19 #include "SequenceToOffsetTable.h"
20 #include "llvm/TableGen/Record.h"
21 #include "llvm/ADT/BitVector.h"
22 #include "llvm/ADT/StringExtras.h"
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/Support/Format.h"
29 // runEnums - Print out enum values for all of the registers.
31 RegisterInfoEmitter::runEnums(raw_ostream &OS,
32 CodeGenTarget &Target, CodeGenRegBank &Bank) {
33 const std::vector<CodeGenRegister*> &Registers = Bank.getRegisters();
35 // Register enums are stored as uint16_t in the tables. Make sure we'll fit.
36 assert(Registers.size() <= 0xffff && "Too many regs to fit in tables");
38 std::string Namespace = Registers[0]->TheDef->getValueAsString("Namespace");
40 EmitSourceFileHeader("Target Register Enum Values", OS);
42 OS << "\n#ifdef GET_REGINFO_ENUM\n";
43 OS << "#undef GET_REGINFO_ENUM\n";
45 OS << "namespace llvm {\n\n";
47 OS << "class MCRegisterClass;\n"
48 << "extern const MCRegisterClass " << Namespace
49 << "MCRegisterClasses[];\n\n";
51 if (!Namespace.empty())
52 OS << "namespace " << Namespace << " {\n";
53 OS << "enum {\n NoRegister,\n";
55 for (unsigned i = 0, e = Registers.size(); i != e; ++i)
56 OS << " " << Registers[i]->getName() << " = " <<
57 Registers[i]->EnumValue << ",\n";
58 assert(Registers.size() == Registers[Registers.size()-1]->EnumValue &&
59 "Register enum value mismatch!");
60 OS << " NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n";
62 if (!Namespace.empty())
65 ArrayRef<CodeGenRegisterClass*> RegisterClasses = Bank.getRegClasses();
66 if (!RegisterClasses.empty()) {
68 // RegisterClass enums are stored as uint16_t in the tables.
69 assert(RegisterClasses.size() <= 0xffff &&
70 "Too many register classes to fit in tables");
72 OS << "\n// Register classes\n";
73 if (!Namespace.empty())
74 OS << "namespace " << Namespace << " {\n";
76 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
78 OS << " " << RegisterClasses[i]->getName() << "RegClassID";
82 if (!Namespace.empty())
86 const std::vector<Record*> RegAltNameIndices = Target.getRegAltNameIndices();
87 // If the only definition is the default NoRegAltName, we don't need to
89 if (RegAltNameIndices.size() > 1) {
90 OS << "\n// Register alternate name indices\n";
91 if (!Namespace.empty())
92 OS << "namespace " << Namespace << " {\n";
94 for (unsigned i = 0, e = RegAltNameIndices.size(); i != e; ++i)
95 OS << " " << RegAltNameIndices[i]->getName() << ",\t// " << i << "\n";
96 OS << " NUM_TARGET_REG_ALT_NAMES = " << RegAltNameIndices.size() << "\n";
98 if (!Namespace.empty())
102 ArrayRef<CodeGenSubRegIndex*> SubRegIndices = Bank.getSubRegIndices();
103 if (!SubRegIndices.empty()) {
104 OS << "\n// Subregister indices\n";
105 std::string Namespace =
106 SubRegIndices[0]->getNamespace();
107 if (!Namespace.empty())
108 OS << "namespace " << Namespace << " {\n";
109 OS << "enum {\n NoSubRegister,\n";
110 for (unsigned i = 0, e = Bank.getNumNamedIndices(); i != e; ++i)
111 OS << " " << SubRegIndices[i]->getName() << ",\t// " << i+1 << "\n";
112 OS << " NUM_TARGET_NAMED_SUBREGS\n};\n";
113 if (!Namespace.empty())
117 OS << "} // End llvm namespace \n";
118 OS << "#endif // GET_REGINFO_ENUM\n\n";
121 void RegisterInfoEmitter::
122 EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank,
123 const std::string &ClassName) {
124 unsigned NumRCs = RegBank.getRegClasses().size();
125 unsigned NumSets = RegBank.getNumRegPressureSets();
127 OS << "/// Get the weight in units of pressure for this register class.\n"
128 << "const RegClassWeight &" << ClassName << "::\n"
129 << "getRegClassWeight(const TargetRegisterClass *RC) const {\n"
130 << " static const RegClassWeight RCWeightTable[] = {\n";
131 for (unsigned i = 0, e = NumRCs; i != e; ++i) {
132 const CodeGenRegisterClass &RC = *RegBank.getRegClasses()[i];
133 const CodeGenRegister::Set &Regs = RC.getMembers();
137 std::vector<unsigned> RegUnits;
138 RC.buildRegUnitSet(RegUnits);
139 OS << " {" << (*Regs.begin())->getWeight(RegBank)
140 << ", " << RegBank.getRegUnitSetWeight(RegUnits);
142 OS << "}, \t// " << RC.getName() << "\n";
145 << " return RCWeightTable[RC->getID()];\n"
149 << "// Get the number of dimensions of register pressure.\n"
150 << "unsigned " << ClassName << "::getNumRegPressureSets() const {\n"
151 << " return " << NumSets << ";\n}\n\n";
153 OS << "// Get the register unit pressure limit for this dimension.\n"
154 << "// This limit must be adjusted dynamically for reserved registers.\n"
155 << "unsigned " << ClassName << "::\n"
156 << "getRegPressureSetLimit(unsigned Idx) const {\n"
157 << " static const unsigned PressureLimitTable[] = {\n";
158 for (unsigned i = 0; i < NumSets; ++i ) {
159 const RegUnitSet &RegUnits = RegBank.getRegPressureSet(i);
160 OS << " " << RegBank.getRegUnitSetWeight(RegUnits.Units)
161 << ", \t// " << i << ": " << RegBank.getRegPressureSet(i).Name << "\n";
164 << " return PressureLimitTable[Idx];\n"
167 OS << "/// Get the dimensions of register pressure "
168 << "impacted by this register class.\n"
169 << "/// Returns a -1 terminated array of pressure set IDs\n"
170 << "const int* " << ClassName << "::\n"
171 << "getRegClassPressureSets(const TargetRegisterClass *RC) const {\n"
172 << " static const int RCSetsTable[] = {\n ";
173 std::vector<unsigned> RCSetStarts(NumRCs);
174 for (unsigned i = 0, StartIdx = 0, e = NumRCs; i != e; ++i) {
175 RCSetStarts[i] = StartIdx;
176 ArrayRef<unsigned> PSetIDs = RegBank.getRCPressureSetIDs(i);
177 for (ArrayRef<unsigned>::iterator PSetI = PSetIDs.begin(),
178 PSetE = PSetIDs.end(); PSetI != PSetE; ++PSetI) {
179 OS << *PSetI << ", ";
182 OS << "-1, \t// " << RegBank.getRegClasses()[i]->getName() << "\n ";
186 OS << " static const unsigned RCSetStartTable[] = {\n ";
187 for (unsigned i = 0, e = NumRCs; i != e; ++i) {
188 OS << RCSetStarts[i] << ",";
191 << " unsigned SetListStart = RCSetStartTable[RC->getID()];\n"
192 << " return &RCSetsTable[SetListStart];\n"
197 RegisterInfoEmitter::EmitRegMappingTables(raw_ostream &OS,
198 const std::vector<CodeGenRegister*> &Regs,
200 // Collect all information about dwarf register numbers
201 typedef std::map<Record*, std::vector<int64_t>, LessRecord> DwarfRegNumsMapTy;
202 DwarfRegNumsMapTy DwarfRegNums;
204 // First, just pull all provided information to the map
205 unsigned maxLength = 0;
206 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
207 Record *Reg = Regs[i]->TheDef;
208 std::vector<int64_t> RegNums = Reg->getValueAsListOfInts("DwarfNumbers");
209 maxLength = std::max((size_t)maxLength, RegNums.size());
210 if (DwarfRegNums.count(Reg))
211 errs() << "Warning: DWARF numbers for register " << getQualifiedName(Reg)
212 << "specified multiple times\n";
213 DwarfRegNums[Reg] = RegNums;
219 // Now we know maximal length of number list. Append -1's, where needed
220 for (DwarfRegNumsMapTy::iterator
221 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I)
222 for (unsigned i = I->second.size(), e = maxLength; i != e; ++i)
223 I->second.push_back(-1);
225 std::string Namespace = Regs[0]->TheDef->getValueAsString("Namespace");
227 OS << "// " << Namespace << " Dwarf<->LLVM register mappings.\n";
229 // Emit reverse information about the dwarf register numbers.
230 for (unsigned j = 0; j < 2; ++j) {
231 for (unsigned i = 0, e = maxLength; i != e; ++i) {
232 OS << "extern const MCRegisterInfo::DwarfLLVMRegPair " << Namespace;
233 OS << (j == 0 ? "DwarfFlavour" : "EHFlavour");
234 OS << i << "Dwarf2L[]";
239 // Store the mapping sorted by the LLVM reg num so lookup can be done
240 // with a binary search.
241 std::map<uint64_t, Record*> Dwarf2LMap;
242 for (DwarfRegNumsMapTy::iterator
243 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
244 int DwarfRegNo = I->second[i];
247 Dwarf2LMap[DwarfRegNo] = I->first;
250 for (std::map<uint64_t, Record*>::iterator
251 I = Dwarf2LMap.begin(), E = Dwarf2LMap.end(); I != E; ++I)
252 OS << " { " << I->first << "U, " << getQualifiedName(I->second)
260 // We have to store the size in a const global, it's used in multiple
262 OS << "extern const unsigned " << Namespace
263 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i << "Dwarf2LSize";
265 OS << " = sizeof(" << Namespace
266 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i
267 << "Dwarf2L)/sizeof(MCRegisterInfo::DwarfLLVMRegPair);\n\n";
273 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
274 Record *Reg = Regs[i]->TheDef;
275 const RecordVal *V = Reg->getValue("DwarfAlias");
276 if (!V || !V->getValue())
279 DefInit *DI = dynamic_cast<DefInit*>(V->getValue());
280 Record *Alias = DI->getDef();
281 DwarfRegNums[Reg] = DwarfRegNums[Alias];
284 // Emit information about the dwarf register numbers.
285 for (unsigned j = 0; j < 2; ++j) {
286 for (unsigned i = 0, e = maxLength; i != e; ++i) {
287 OS << "extern const MCRegisterInfo::DwarfLLVMRegPair " << Namespace;
288 OS << (j == 0 ? "DwarfFlavour" : "EHFlavour");
289 OS << i << "L2Dwarf[]";
292 // Store the mapping sorted by the Dwarf reg num so lookup can be done
293 // with a binary search.
294 for (DwarfRegNumsMapTy::iterator
295 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
296 int RegNo = I->second[i];
297 if (RegNo == -1) // -1 is the default value, don't emit a mapping.
300 OS << " { " << getQualifiedName(I->first) << ", " << RegNo
308 // We have to store the size in a const global, it's used in multiple
310 OS << "extern const unsigned " << Namespace
311 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i << "L2DwarfSize";
313 OS << " = sizeof(" << Namespace
314 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i
315 << "L2Dwarf)/sizeof(MCRegisterInfo::DwarfLLVMRegPair);\n\n";
323 RegisterInfoEmitter::EmitRegMapping(raw_ostream &OS,
324 const std::vector<CodeGenRegister*> &Regs,
326 // Emit the initializer so the tables from EmitRegMappingTables get wired up
327 // to the MCRegisterInfo object.
328 unsigned maxLength = 0;
329 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
330 Record *Reg = Regs[i]->TheDef;
331 maxLength = std::max((size_t)maxLength,
332 Reg->getValueAsListOfInts("DwarfNumbers").size());
338 std::string Namespace = Regs[0]->TheDef->getValueAsString("Namespace");
340 // Emit reverse information about the dwarf register numbers.
341 for (unsigned j = 0; j < 2; ++j) {
344 OS << "DwarfFlavour";
349 << " llvm_unreachable(\"Unknown DWARF flavour\");\n";
351 for (unsigned i = 0, e = maxLength; i != e; ++i) {
352 OS << " case " << i << ":\n";
357 raw_string_ostream(Tmp) << Namespace
358 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i
360 OS << "mapDwarfRegsToLLVMRegs(" << Tmp << ", " << Tmp << "Size, ";
371 // Emit information about the dwarf register numbers.
372 for (unsigned j = 0; j < 2; ++j) {
375 OS << "DwarfFlavour";
380 << " llvm_unreachable(\"Unknown DWARF flavour\");\n";
382 for (unsigned i = 0, e = maxLength; i != e; ++i) {
383 OS << " case " << i << ":\n";
388 raw_string_ostream(Tmp) << Namespace
389 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i
391 OS << "mapLLVMRegsToDwarfRegs(" << Tmp << ", " << Tmp << "Size, ";
403 // Print a BitVector as a sequence of hex numbers using a little-endian mapping.
404 // Width is the number of bits per hex number.
405 static void printBitVectorAsHex(raw_ostream &OS,
406 const BitVector &Bits,
408 assert(Width <= 32 && "Width too large");
409 unsigned Digits = (Width + 3) / 4;
410 for (unsigned i = 0, e = Bits.size(); i < e; i += Width) {
412 for (unsigned j = 0; j != Width && i + j != e; ++j)
413 Value |= Bits.test(i + j) << j;
414 OS << format("0x%0*x, ", Digits, Value);
418 // Helper to emit a set of bits into a constant byte array.
419 class BitVectorEmitter {
422 void add(unsigned v) {
423 if (v >= Values.size())
424 Values.resize(((v/8)+1)*8); // Round up to the next byte.
428 void print(raw_ostream &OS) {
429 printBitVectorAsHex(OS, Values, 8);
433 static void printRegister(raw_ostream &OS, const CodeGenRegister *Reg) {
434 OS << getQualifiedName(Reg->TheDef);
437 static void printSimpleValueType(raw_ostream &OS, MVT::SimpleValueType VT) {
438 OS << getEnumName(VT);
442 // runMCDesc - Print out MC register descriptions.
445 RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target,
446 CodeGenRegBank &RegBank) {
447 EmitSourceFileHeader("MC Register Information", OS);
449 OS << "\n#ifdef GET_REGINFO_MC_DESC\n";
450 OS << "#undef GET_REGINFO_MC_DESC\n";
452 const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters();
453 std::map<const CodeGenRegister*, CodeGenRegister::Set> Overlaps;
454 RegBank.computeOverlaps(Overlaps);
456 // The lists of sub-registers, super-registers, and overlaps all go in the
457 // same array. That allows us to share suffixes.
458 typedef std::vector<const CodeGenRegister*> RegVec;
459 SmallVector<RegVec, 4> SubRegLists(Regs.size());
460 SmallVector<RegVec, 4> OverlapLists(Regs.size());
461 SequenceToOffsetTable<RegVec, CodeGenRegister::Less> RegSeqs;
463 // Precompute register lists for the SequenceToOffsetTable.
464 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
465 const CodeGenRegister *Reg = Regs[i];
467 // Compute the ordered sub-register list.
468 SetVector<const CodeGenRegister*> SR;
469 Reg->addSubRegsPreOrder(SR, RegBank);
470 RegVec &SubRegList = SubRegLists[i];
471 SubRegList.assign(SR.begin(), SR.end());
472 RegSeqs.add(SubRegList);
474 // Super-registers are already computed.
475 const RegVec &SuperRegList = Reg->getSuperRegs();
476 RegSeqs.add(SuperRegList);
478 // The list of overlaps doesn't need to have any particular order, except
479 // Reg itself must be the first element. Pick an ordering that has one of
480 // the other lists as a suffix.
481 RegVec &OverlapList = OverlapLists[i];
482 const RegVec &Suffix = SubRegList.size() > SuperRegList.size() ?
483 SubRegList : SuperRegList;
484 CodeGenRegister::Set Omit(Suffix.begin(), Suffix.end());
486 // First element is Reg itself.
487 OverlapList.push_back(Reg);
490 // Any elements not in Suffix.
491 const CodeGenRegister::Set &OSet = Overlaps[Reg];
492 std::set_difference(OSet.begin(), OSet.end(),
493 Omit.begin(), Omit.end(),
494 std::back_inserter(OverlapList),
495 CodeGenRegister::Less());
497 // Finally, Suffix itself.
498 OverlapList.insert(OverlapList.end(), Suffix.begin(), Suffix.end());
499 RegSeqs.add(OverlapList);
502 // Compute the final layout of the sequence table.
505 OS << "namespace llvm {\n\n";
507 const std::string &TargetName = Target.getName();
509 // Emit the shared table of register lists.
510 OS << "extern const uint16_t " << TargetName << "RegLists[] = {\n";
511 RegSeqs.emit(OS, printRegister);
514 OS << "extern const MCRegisterDesc " << TargetName
515 << "RegDesc[] = { // Descriptors\n";
516 OS << " { \"NOREG\", 0, 0, 0 },\n";
518 // Emit the register descriptors now.
519 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
520 const CodeGenRegister *Reg = Regs[i];
521 OS << " { \"" << Reg->getName() << "\", "
522 << RegSeqs.get(OverlapLists[i]) << ", "
523 << RegSeqs.get(SubRegLists[i]) << ", "
524 << RegSeqs.get(Reg->getSuperRegs()) << " },\n";
526 OS << "};\n\n"; // End of register descriptors...
528 ArrayRef<CodeGenRegisterClass*> RegisterClasses = RegBank.getRegClasses();
530 // Loop over all of the register classes... emitting each one.
531 OS << "namespace { // Register classes...\n";
533 // Emit the register enum value arrays for each RegisterClass
534 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
535 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
536 ArrayRef<Record*> Order = RC.getOrder();
538 // Give the register class a legal C name if it's anonymous.
539 std::string Name = RC.getName();
541 // Emit the register list now.
542 OS << " // " << Name << " Register Class...\n"
543 << " const uint16_t " << Name
545 for (unsigned i = 0, e = Order.size(); i != e; ++i) {
546 Record *Reg = Order[i];
547 OS << getQualifiedName(Reg) << ", ";
551 OS << " // " << Name << " Bit set.\n"
552 << " const uint8_t " << Name
554 BitVectorEmitter BVE;
555 for (unsigned i = 0, e = Order.size(); i != e; ++i) {
556 Record *Reg = Order[i];
557 BVE.add(Target.getRegBank().getReg(Reg)->EnumValue);
565 OS << "extern const MCRegisterClass " << TargetName
566 << "MCRegisterClasses[] = {\n";
568 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
569 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
571 // Asserts to make sure values will fit in table assuming types from
573 assert((RC.SpillSize/8) <= 0xffff && "SpillSize too large.");
574 assert((RC.SpillAlignment/8) <= 0xffff && "SpillAlignment too large.");
575 assert(RC.CopyCost >= -128 && RC.CopyCost <= 127 && "Copy cost too large.");
577 OS << " { " << '\"' << RC.getName() << "\", "
578 << RC.getName() << ", " << RC.getName() << "Bits, "
579 << RC.getOrder().size() << ", sizeof(" << RC.getName() << "Bits), "
580 << RC.getQualifiedName() + "RegClassID" << ", "
581 << RC.SpillSize/8 << ", "
582 << RC.SpillAlignment/8 << ", "
583 << RC.CopyCost << ", "
584 << RC.Allocatable << " },\n";
589 // Emit the data table for getSubReg().
590 ArrayRef<CodeGenSubRegIndex*> SubRegIndices = RegBank.getSubRegIndices();
591 if (SubRegIndices.size()) {
592 OS << "const uint16_t " << TargetName << "SubRegTable[]["
593 << SubRegIndices.size() << "] = {\n";
594 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
595 const CodeGenRegister::SubRegMap &SRM = Regs[i]->getSubRegs();
596 OS << " /* " << Regs[i]->TheDef->getName() << " */\n";
602 for (unsigned j = 0, je = SubRegIndices.size(); j != je; ++j) {
603 // FIXME: We really should keep this to 80 columns...
604 CodeGenRegister::SubRegMap::const_iterator SubReg =
605 SRM.find(SubRegIndices[j]);
606 if (SubReg != SRM.end())
607 OS << getQualifiedName(SubReg->second->TheDef);
613 OS << "}" << (i != e ? "," : "") << "\n";
616 OS << "const uint16_t *get" << TargetName
617 << "SubRegTable() {\n return (const uint16_t *)" << TargetName
618 << "SubRegTable;\n}\n\n";
621 EmitRegMappingTables(OS, Regs, false);
623 // MCRegisterInfo initialization routine.
624 OS << "static inline void Init" << TargetName
625 << "MCRegisterInfo(MCRegisterInfo *RI, unsigned RA, "
626 << "unsigned DwarfFlavour = 0, unsigned EHFlavour = 0) {\n";
627 OS << " RI->InitMCRegisterInfo(" << TargetName << "RegDesc, "
628 << Regs.size()+1 << ", RA, " << TargetName << "MCRegisterClasses, "
629 << RegisterClasses.size() << ", " << TargetName << "RegLists, ";
630 if (SubRegIndices.size() != 0)
631 OS << "(uint16_t*)" << TargetName << "SubRegTable, "
632 << SubRegIndices.size() << ");\n\n";
634 OS << "NULL, 0);\n\n";
636 EmitRegMapping(OS, Regs, false);
640 OS << "} // End llvm namespace \n";
641 OS << "#endif // GET_REGINFO_MC_DESC\n\n";
645 RegisterInfoEmitter::runTargetHeader(raw_ostream &OS, CodeGenTarget &Target,
646 CodeGenRegBank &RegBank) {
647 EmitSourceFileHeader("Register Information Header Fragment", OS);
649 OS << "\n#ifdef GET_REGINFO_HEADER\n";
650 OS << "#undef GET_REGINFO_HEADER\n";
652 const std::string &TargetName = Target.getName();
653 std::string ClassName = TargetName + "GenRegisterInfo";
655 OS << "#include \"llvm/Target/TargetRegisterInfo.h\"\n\n";
657 OS << "namespace llvm {\n\n";
659 OS << "struct " << ClassName << " : public TargetRegisterInfo {\n"
660 << " explicit " << ClassName
661 << "(unsigned RA, unsigned D = 0, unsigned E = 0);\n"
662 << " virtual bool needsStackRealignment(const MachineFunction &) const\n"
663 << " { return false; }\n"
664 << " unsigned composeSubRegIndices(unsigned, unsigned) const;\n"
665 << " const TargetRegisterClass *"
666 "getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const;\n"
667 << " const TargetRegisterClass *getMatchingSuperRegClass("
668 "const TargetRegisterClass*, const TargetRegisterClass*, "
670 << " const RegClassWeight &getRegClassWeight("
671 << "const TargetRegisterClass *RC) const;\n"
672 << " unsigned getNumRegPressureSets() const;\n"
673 << " unsigned getRegPressureSetLimit(unsigned Idx) const;\n"
674 << " const int *getRegClassPressureSets("
675 << "const TargetRegisterClass *RC) const;\n"
678 ArrayRef<CodeGenRegisterClass*> RegisterClasses = RegBank.getRegClasses();
680 if (!RegisterClasses.empty()) {
681 OS << "namespace " << RegisterClasses[0]->Namespace
682 << " { // Register classes\n";
684 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
685 const CodeGenRegisterClass &RC = *RegisterClasses[i];
686 const std::string &Name = RC.getName();
688 // Output the extern for the instance.
689 OS << " extern const TargetRegisterClass " << Name << "RegClass;\n";
690 // Output the extern for the pointer to the instance (should remove).
691 OS << " static const TargetRegisterClass * const " << Name
692 << "RegisterClass = &" << Name << "RegClass;\n";
694 OS << "} // end of namespace " << TargetName << "\n\n";
696 OS << "} // End llvm namespace \n";
697 OS << "#endif // GET_REGINFO_HEADER\n\n";
701 // runTargetDesc - Output the target register and register file descriptions.
704 RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
705 CodeGenRegBank &RegBank){
706 EmitSourceFileHeader("Target Register and Register Classes Information", OS);
708 OS << "\n#ifdef GET_REGINFO_TARGET_DESC\n";
709 OS << "#undef GET_REGINFO_TARGET_DESC\n";
711 OS << "namespace llvm {\n\n";
713 // Get access to MCRegisterClass data.
714 OS << "extern const MCRegisterClass " << Target.getName()
715 << "MCRegisterClasses[];\n";
717 // Start out by emitting each of the register classes.
718 ArrayRef<CodeGenRegisterClass*> RegisterClasses = RegBank.getRegClasses();
720 // Collect all registers belonging to any allocatable class.
721 std::set<Record*> AllocatableRegs;
723 // Collect allocatable registers.
724 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
725 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
726 ArrayRef<Record*> Order = RC.getOrder();
729 AllocatableRegs.insert(Order.begin(), Order.end());
732 // Build a shared array of value types.
733 SequenceToOffsetTable<std::vector<MVT::SimpleValueType> > VTSeqs;
734 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc)
735 VTSeqs.add(RegisterClasses[rc]->VTs);
737 OS << "\nstatic const MVT::SimpleValueType VTLists[] = {\n";
738 VTSeqs.emit(OS, printSimpleValueType, "MVT::Other");
741 // Now that all of the structs have been emitted, emit the instances.
742 if (!RegisterClasses.empty()) {
743 std::map<unsigned, std::set<unsigned> > SuperRegClassMap;
745 OS << "\nstatic const TargetRegisterClass *const "
746 << "NullRegClasses[] = { NULL };\n\n";
748 unsigned NumSubRegIndices = RegBank.getSubRegIndices().size();
750 if (NumSubRegIndices) {
751 // Compute the super-register classes for each RegisterClass
752 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
753 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
754 for (DenseMap<Record*,Record*>::const_iterator
755 i = RC.SubRegClasses.begin(),
756 e = RC.SubRegClasses.end(); i != e; ++i) {
757 // Find the register class number of i->second for SuperRegClassMap.
758 const CodeGenRegisterClass *RC2 = RegBank.getRegClass(i->second);
759 assert(RC2 && "Invalid register class in SubRegClasses");
760 SuperRegClassMap[RC2->EnumValue].insert(rc);
764 // Emit the super-register classes for each RegisterClass
765 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
766 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
768 // Give the register class a legal C name if it's anonymous.
769 std::string Name = RC.getName();
772 << " Super-register Classes...\n"
773 << "static const TargetRegisterClass *const "
774 << Name << "SuperRegClasses[] = {\n ";
777 std::map<unsigned, std::set<unsigned> >::iterator I =
778 SuperRegClassMap.find(rc);
779 if (I != SuperRegClassMap.end()) {
780 for (std::set<unsigned>::iterator II = I->second.begin(),
781 EE = I->second.end(); II != EE; ++II) {
782 const CodeGenRegisterClass &RC2 = *RegisterClasses[*II];
785 OS << "&" << RC2.getQualifiedName() << "RegClass";
790 OS << (!Empty ? ", " : "") << "NULL";
795 // Emit the sub-classes array for each RegisterClass
796 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
797 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
799 // Give the register class a legal C name if it's anonymous.
800 std::string Name = RC.getName();
802 OS << "static const uint32_t " << Name << "SubclassMask[] = {\n ";
803 printBitVectorAsHex(OS, RC.getSubClasses(), 32);
807 // Emit NULL terminated super-class lists.
808 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
809 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
810 ArrayRef<CodeGenRegisterClass*> Supers = RC.getSuperClasses();
812 // Skip classes without supers. We can reuse NullRegClasses.
816 OS << "static const TargetRegisterClass *const "
817 << RC.getName() << "Superclasses[] = {\n";
818 for (unsigned i = 0; i != Supers.size(); ++i)
819 OS << " &" << Supers[i]->getQualifiedName() << "RegClass,\n";
820 OS << " NULL\n};\n\n";
824 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
825 const CodeGenRegisterClass &RC = *RegisterClasses[i];
826 if (!RC.AltOrderSelect.empty()) {
827 OS << "\nstatic inline unsigned " << RC.getName()
828 << "AltOrderSelect(const MachineFunction &MF) {"
829 << RC.AltOrderSelect << "}\n\n"
830 << "static ArrayRef<uint16_t> " << RC.getName()
831 << "GetRawAllocationOrder(const MachineFunction &MF) {\n";
832 for (unsigned oi = 1 , oe = RC.getNumOrders(); oi != oe; ++oi) {
833 ArrayRef<Record*> Elems = RC.getOrder(oi);
834 if (!Elems.empty()) {
835 OS << " static const uint16_t AltOrder" << oi << "[] = {";
836 for (unsigned elem = 0; elem != Elems.size(); ++elem)
837 OS << (elem ? ", " : " ") << getQualifiedName(Elems[elem]);
841 OS << " const MCRegisterClass &MCR = " << Target.getName()
842 << "MCRegisterClasses[" << RC.getQualifiedName() + "RegClassID];\n"
843 << " const ArrayRef<uint16_t> Order[] = {\n"
844 << " makeArrayRef(MCR.begin(), MCR.getNumRegs()";
845 for (unsigned oi = 1, oe = RC.getNumOrders(); oi != oe; ++oi)
846 if (RC.getOrder(oi).empty())
847 OS << "),\n ArrayRef<uint16_t>(";
849 OS << "),\n makeArrayRef(AltOrder" << oi;
850 OS << ")\n };\n const unsigned Select = " << RC.getName()
851 << "AltOrderSelect(MF);\n assert(Select < " << RC.getNumOrders()
852 << ");\n return Order[Select];\n}\n";
856 // Now emit the actual value-initialized register class instances.
857 OS << "namespace " << RegisterClasses[0]->Namespace
858 << " { // Register class instances\n";
860 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
861 const CodeGenRegisterClass &RC = *RegisterClasses[i];
862 OS << " extern const TargetRegisterClass "
863 << RegisterClasses[i]->getName() << "RegClass = {\n "
864 << '&' << Target.getName() << "MCRegisterClasses[" << RC.getName()
866 << "VTLists + " << VTSeqs.get(RC.VTs) << ",\n "
867 << RC.getName() << "SubclassMask,\n ";
868 if (RC.getSuperClasses().empty())
869 OS << "NullRegClasses,\n ";
871 OS << RC.getName() << "Superclasses,\n ";
872 OS << (NumSubRegIndices ? RC.getName() + "Super" : std::string("Null"))
874 if (RC.AltOrderSelect.empty())
877 OS << RC.getName() << "GetRawAllocationOrder\n";
884 OS << "\nnamespace {\n";
885 OS << " const TargetRegisterClass* const RegisterClasses[] = {\n";
886 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i)
887 OS << " &" << RegisterClasses[i]->getQualifiedName()
890 OS << "}\n"; // End of anonymous namespace...
892 // Emit extra information about registers.
893 const std::string &TargetName = Target.getName();
894 OS << "\nstatic const TargetRegisterInfoDesc "
895 << TargetName << "RegInfoDesc[] = { // Extra Descriptors\n";
896 OS << " { 0, 0 },\n";
898 const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters();
899 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
900 const CodeGenRegister &Reg = *Regs[i];
902 OS << Reg.CostPerUse << ", "
903 << int(AllocatableRegs.count(Reg.TheDef)) << " },\n";
905 OS << "};\n"; // End of register descriptors...
908 // Calculate the mapping of subregister+index pairs to physical registers.
909 // This will also create further anonymous indices.
910 unsigned NamedIndices = RegBank.getNumNamedIndices();
912 // Emit SubRegIndex names, skipping 0
913 ArrayRef<CodeGenSubRegIndex*> SubRegIndices = RegBank.getSubRegIndices();
914 OS << "\nstatic const char *const " << TargetName
915 << "SubRegIndexTable[] = { \"";
916 for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) {
917 OS << SubRegIndices[i]->getName();
923 // Emit names of the anonymous subreg indices.
924 if (SubRegIndices.size() > NamedIndices) {
926 for (unsigned i = NamedIndices, e = SubRegIndices.size(); i != e; ++i) {
927 OS << "\n " << SubRegIndices[i]->getName() << " = " << i+1;
935 std::string ClassName = Target.getName() + "GenRegisterInfo";
937 // Emit composeSubRegIndices
938 OS << "unsigned " << ClassName
939 << "::composeSubRegIndices(unsigned IdxA, unsigned IdxB) const {\n"
940 << " switch (IdxA) {\n"
941 << " default:\n return IdxB;\n";
942 for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) {
944 for (unsigned j = 0; j != e; ++j) {
945 if (CodeGenSubRegIndex *Comp =
946 SubRegIndices[i]->compose(SubRegIndices[j])) {
948 OS << " case " << SubRegIndices[i]->getQualifiedName()
949 << ": switch(IdxB) {\n default: return IdxB;\n";
952 OS << " case " << SubRegIndices[j]->getQualifiedName()
953 << ": return " << Comp->getQualifiedName() << ";\n";
961 // Emit getSubClassWithSubReg.
962 OS << "const TargetRegisterClass *" << ClassName
963 << "::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx)"
965 if (SubRegIndices.empty()) {
966 OS << " assert(Idx == 0 && \"Target has no sub-registers\");\n"
969 // Use the smallest type that can hold a regclass ID with room for a
971 if (RegisterClasses.size() < UINT8_MAX)
972 OS << " static const uint8_t Table[";
973 else if (RegisterClasses.size() < UINT16_MAX)
974 OS << " static const uint16_t Table[";
976 throw "Too many register classes.";
977 OS << RegisterClasses.size() << "][" << SubRegIndices.size() << "] = {\n";
978 for (unsigned rci = 0, rce = RegisterClasses.size(); rci != rce; ++rci) {
979 const CodeGenRegisterClass &RC = *RegisterClasses[rci];
980 OS << " {\t// " << RC.getName() << "\n";
981 for (unsigned sri = 0, sre = SubRegIndices.size(); sri != sre; ++sri) {
982 CodeGenSubRegIndex *Idx = SubRegIndices[sri];
983 if (CodeGenRegisterClass *SRC = RC.getSubClassWithSubReg(Idx))
984 OS << " " << SRC->EnumValue + 1 << ",\t// " << Idx->getName()
985 << " -> " << SRC->getName() << "\n";
987 OS << " 0,\t// " << Idx->getName() << "\n";
991 OS << " };\n assert(RC && \"Missing regclass\");\n"
992 << " if (!Idx) return RC;\n --Idx;\n"
993 << " assert(Idx < " << SubRegIndices.size() << " && \"Bad subreg\");\n"
994 << " unsigned TV = Table[RC->getID()][Idx];\n"
995 << " return TV ? getRegClass(TV - 1) : 0;\n";
999 // Emit getMatchingSuperRegClass.
1000 OS << "const TargetRegisterClass *" << ClassName
1001 << "::getMatchingSuperRegClass(const TargetRegisterClass *A,"
1002 " const TargetRegisterClass *B, unsigned Idx) const {\n";
1003 if (SubRegIndices.empty()) {
1004 OS << " llvm_unreachable(\"Target has no sub-registers\");\n";
1006 // We need to find the largest sub-class of A such that every register has
1007 // an Idx sub-register in B. Map (B, Idx) to a bit-vector of
1008 // super-register classes that map into B. Then compute the largest common
1009 // sub-class with A by taking advantage of the register class ordering,
1010 // like getCommonSubClass().
1012 // Bitvector table is NumRCs x NumSubIndexes x BVWords, where BVWords is
1013 // the number of 32-bit words required to represent all register classes.
1014 const unsigned BVWords = (RegisterClasses.size()+31)/32;
1015 BitVector BV(RegisterClasses.size());
1017 OS << " static const uint32_t Table[" << RegisterClasses.size()
1018 << "][" << SubRegIndices.size() << "][" << BVWords << "] = {\n";
1019 for (unsigned rci = 0, rce = RegisterClasses.size(); rci != rce; ++rci) {
1020 const CodeGenRegisterClass &RC = *RegisterClasses[rci];
1021 OS << " {\t// " << RC.getName() << "\n";
1022 for (unsigned sri = 0, sre = SubRegIndices.size(); sri != sre; ++sri) {
1023 CodeGenSubRegIndex *Idx = SubRegIndices[sri];
1025 RC.getSuperRegClasses(Idx, BV);
1027 printBitVectorAsHex(OS, BV, 32);
1028 OS << "},\t// " << Idx->getName() << '\n';
1032 OS << " };\n assert(A && B && \"Missing regclass\");\n"
1034 << " assert(Idx < " << SubRegIndices.size() << " && \"Bad subreg\");\n"
1035 << " const uint32_t *TV = Table[B->getID()][Idx];\n"
1036 << " const uint32_t *SC = A->getSubClassMask();\n"
1037 << " for (unsigned i = 0; i != " << BVWords << "; ++i)\n"
1038 << " if (unsigned Common = TV[i] & SC[i])\n"
1039 << " return getRegClass(32*i + CountTrailingZeros_32(Common));\n"
1044 EmitRegUnitPressure(OS, RegBank, ClassName);
1046 // Emit the constructor of the class...
1047 OS << "extern const MCRegisterDesc " << TargetName << "RegDesc[];\n";
1048 OS << "extern const uint16_t " << TargetName << "RegLists[];\n";
1049 if (SubRegIndices.size() != 0)
1050 OS << "extern const uint16_t *get" << TargetName
1051 << "SubRegTable();\n";
1053 EmitRegMappingTables(OS, Regs, true);
1055 OS << ClassName << "::\n" << ClassName
1056 << "(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour)\n"
1057 << " : TargetRegisterInfo(" << TargetName << "RegInfoDesc"
1058 << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n"
1059 << " " << TargetName << "SubRegIndexTable) {\n"
1060 << " InitMCRegisterInfo(" << TargetName << "RegDesc, "
1061 << Regs.size()+1 << ", RA,\n " << TargetName
1062 << "MCRegisterClasses, " << RegisterClasses.size() << ",\n"
1063 << " " << TargetName << "RegLists,\n"
1065 if (SubRegIndices.size() != 0)
1066 OS << "get" << TargetName << "SubRegTable(), "
1067 << SubRegIndices.size() << ");\n\n";
1069 OS << "NULL, 0);\n\n";
1071 EmitRegMapping(OS, Regs, true);
1076 // Emit CalleeSavedRegs information.
1077 std::vector<Record*> CSRSets =
1078 Records.getAllDerivedDefinitions("CalleeSavedRegs");
1079 for (unsigned i = 0, e = CSRSets.size(); i != e; ++i) {
1080 Record *CSRSet = CSRSets[i];
1081 const SetTheory::RecVec *Regs = RegBank.getSets().expand(CSRSet);
1082 assert(Regs && "Cannot expand CalleeSavedRegs instance");
1084 // Emit the *_SaveList list of callee-saved registers.
1085 OS << "static const uint16_t " << CSRSet->getName()
1086 << "_SaveList[] = { ";
1087 for (unsigned r = 0, re = Regs->size(); r != re; ++r)
1088 OS << getQualifiedName((*Regs)[r]) << ", ";
1091 // Emit the *_RegMask bit mask of call-preserved registers.
1092 OS << "static const uint32_t " << CSRSet->getName()
1093 << "_RegMask[] = { ";
1094 printBitVectorAsHex(OS, RegBank.computeCoveredRegisters(*Regs), 32);
1099 OS << "} // End llvm namespace \n";
1100 OS << "#endif // GET_REGINFO_TARGET_DESC\n\n";
1103 void RegisterInfoEmitter::run(raw_ostream &OS) {
1104 CodeGenTarget Target(Records);
1105 CodeGenRegBank &RegBank = Target.getRegBank();
1106 RegBank.computeDerivedInfo();
1108 runEnums(OS, Target, RegBank);
1109 runMCDesc(OS, Target, RegBank);
1110 runTargetHeader(OS, Target, RegBank);
1111 runTargetDesc(OS, Target, RegBank);