1 //===- InstrInfoEmitter.cpp - Generate a Instruction Set Desc. ------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend is responsible for emitting a description of the target
11 // instruction set for the code generator.
13 //===----------------------------------------------------------------------===//
15 #include "InstrInfoEmitter.h"
16 #include "CodeGenTarget.h"
17 #include "llvm/Target/TargetInstrInfo.h"
22 // runEnums - Print out enum values for all of the instructions.
23 void InstrInfoEmitter::runEnums(std::ostream &OS) {
24 EmitSourceFileHeader("Target Instruction Enum Values", OS);
25 OS << "namespace llvm {\n\n";
29 // We must emit the PHI opcode first...
30 std::string Namespace;
31 for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
32 E = Target.inst_end(); II != E; ++II) {
33 if (II->second.Namespace != "TargetInstrInfo") {
34 Namespace = II->second.Namespace;
39 if (Namespace.empty()) {
40 cerr << "No instructions defined!\n";
44 std::vector<const CodeGenInstruction*> NumberedInstructions;
45 Target.getInstructionsByEnumValue(NumberedInstructions);
47 OS << "namespace " << Namespace << " {\n";
49 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
50 OS << " " << NumberedInstructions[i]->TheDef->getName()
51 << "\t= " << i << ",\n";
53 OS << " INSTRUCTION_LIST_END = " << NumberedInstructions.size() << "\n";
55 OS << "} // End llvm namespace \n";
58 void InstrInfoEmitter::printDefList(const std::vector<Record*> &Uses,
59 unsigned Num, std::ostream &OS) const {
60 OS << "static const unsigned ImplicitList" << Num << "[] = { ";
61 for (unsigned i = 0, e = Uses.size(); i != e; ++i)
62 OS << getQualifiedName(Uses[i]) << ", ";
66 std::vector<std::string>
67 InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) {
68 std::vector<std::string> Result;
70 for (unsigned i = 0, e = Inst.OperandList.size(); i != e; ++i) {
71 // Handle aggregate operands and normal operands the same way by expanding
72 // either case into a list of operands for this op.
73 std::vector<CodeGenInstruction::OperandInfo> OperandList;
75 // This might be a multiple operand thing. Targets like X86 have
76 // registers in their multi-operand operands. It may also be an anonymous
77 // operand, which has a single operand, but no declared class for the
79 DagInit *MIOI = Inst.OperandList[i].MIOperandInfo;
81 if (!MIOI || MIOI->getNumArgs() == 0) {
82 // Single, anonymous, operand.
83 OperandList.push_back(Inst.OperandList[i]);
85 for (unsigned j = 0, e = Inst.OperandList[i].MINumOperands; j != e; ++j) {
86 OperandList.push_back(Inst.OperandList[i]);
88 Record *OpR = dynamic_cast<DefInit*>(MIOI->getArg(j))->getDef();
89 OperandList.back().Rec = OpR;
93 for (unsigned j = 0, e = OperandList.size(); j != e; ++j) {
94 Record *OpR = OperandList[j].Rec;
97 if (OpR->isSubClassOf("RegisterClass"))
98 Res += getQualifiedName(OpR) + "RegClassID, ";
101 // Fill in applicable flags.
104 // Ptr value whose register class is resolved via callback.
105 if (OpR->getName() == "ptr_rc")
106 Res += "|M_LOOK_UP_PTR_REG_CLASS";
108 // Predicate operands. Check to see if the original unexpanded operand
109 // was of type PredicateOperand.
110 if (Inst.OperandList[i].Rec->isSubClassOf("PredicateOperand") &&
111 !Inst.OperandList[i].Rec->getValueAsBit("isImmutable"))
112 Res += "|M_PREDICATE_OPERAND";
114 // Fill in constraint info.
115 Res += ", " + Inst.OperandList[i].Constraints[j];
116 Result.push_back(Res);
124 // run - Emit the main instruction description records for the target...
125 void InstrInfoEmitter::run(std::ostream &OS) {
128 EmitSourceFileHeader("Target Instruction Descriptors", OS);
129 OS << "namespace llvm {\n\n";
131 CodeGenTarget Target;
132 const std::string &TargetName = Target.getName();
133 Record *InstrInfo = Target.getInstructionSet();
135 // Keep track of all of the def lists we have emitted already.
136 std::map<std::vector<Record*>, unsigned> EmittedLists;
137 unsigned ListNumber = 0;
139 // Emit all of the instruction's implicit uses and defs.
140 for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
141 E = Target.inst_end(); II != E; ++II) {
142 Record *Inst = II->second.TheDef;
143 std::vector<Record*> Uses = Inst->getValueAsListOfDefs("Uses");
145 unsigned &IL = EmittedLists[Uses];
146 if (!IL) printDefList(Uses, IL = ++ListNumber, OS);
148 std::vector<Record*> Defs = Inst->getValueAsListOfDefs("Defs");
150 unsigned &IL = EmittedLists[Defs];
151 if (!IL) printDefList(Defs, IL = ++ListNumber, OS);
155 std::map<std::vector<std::string>, unsigned> OperandInfosEmitted;
156 unsigned OperandListNum = 0;
157 OperandInfosEmitted[std::vector<std::string>()] = ++OperandListNum;
159 // Emit all of the operand info records.
161 for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
162 E = Target.inst_end(); II != E; ++II) {
163 std::vector<std::string> OperandInfo = GetOperandInfo(II->second);
164 unsigned &N = OperandInfosEmitted[OperandInfo];
166 N = ++OperandListNum;
167 OS << "static const TargetOperandInfo OperandInfo" << N << "[] = { ";
168 for (unsigned i = 0, e = OperandInfo.size(); i != e; ++i)
169 OS << "{ " << OperandInfo[i] << " }, ";
174 // Emit all of the TargetInstrDescriptor records in their ENUM ordering.
176 OS << "\nstatic const TargetInstrDescriptor " << TargetName
178 std::vector<const CodeGenInstruction*> NumberedInstructions;
179 Target.getInstructionsByEnumValue(NumberedInstructions);
181 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i)
182 emitRecord(*NumberedInstructions[i], i, InstrInfo, EmittedLists,
183 OperandInfosEmitted, OS);
185 OS << "} // End llvm namespace \n";
188 void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
190 std::map<std::vector<Record*>, unsigned> &EmittedLists,
191 std::map<std::vector<std::string>, unsigned> &OpInfo,
194 if (!Inst.OperandList.empty())
195 // Each logical operand can be multiple MI operands.
196 MinOperands = Inst.OperandList.back().MIOperandNo +
197 Inst.OperandList.back().MINumOperands;
202 OS << Num << ",\t" << MinOperands << ",\t\"";
204 if (Inst.Name.empty())
205 OS << Inst.TheDef->getName();
209 unsigned ItinClass = !IsItineraries ? 0 :
210 ItinClassNumber(Inst.TheDef->getValueAsDef("Itinerary")->getName());
212 OS << "\",\t" << ItinClass << ", 0";
214 // Try to determine (from the pattern), if the instruction is a store.
215 bool isStore = false;
216 if (dynamic_cast<ListInit*>(Inst.TheDef->getValueInit("Pattern"))) {
217 ListInit *LI = Inst.TheDef->getValueAsListInit("Pattern");
218 if (LI && LI->getSize() > 0) {
219 DagInit *Dag = (DagInit *)LI->getElement(0);
220 DefInit *OpDef = dynamic_cast<DefInit*>(Dag->getOperator());
222 Record *Operator = OpDef->getDef();
223 if (Operator->isSubClassOf("SDNode")) {
224 const std::string Opcode = Operator->getValueAsString("Opcode");
225 if (Opcode == "ISD::STORE" || Opcode == "ISD::TRUNCSTORE")
232 // Emit all of the target indepedent flags...
233 if (Inst.isReturn) OS << "|M_RET_FLAG";
234 if (Inst.isBranch) OS << "|M_BRANCH_FLAG";
235 if (Inst.isBarrier) OS << "|M_BARRIER_FLAG";
236 if (Inst.hasDelaySlot) OS << "|M_DELAY_SLOT_FLAG";
237 if (Inst.isCall) OS << "|M_CALL_FLAG";
238 if (Inst.isLoad) OS << "|M_LOAD_FLAG";
239 if (Inst.isStore || isStore) OS << "|M_STORE_FLAG";
240 if (Inst.isPredicable) OS << "|M_PREDICABLE";
241 if (Inst.isConvertibleToThreeAddress) OS << "|M_CONVERTIBLE_TO_3_ADDR";
242 if (Inst.isCommutable) OS << "|M_COMMUTABLE";
243 if (Inst.isTerminator) OS << "|M_TERMINATOR_FLAG";
244 if (Inst.isReMaterializable) OS << "|M_REMATERIALIZIBLE";
245 if (Inst.clobbersPred) OS << "|M_CLOBBERS_PRED";
246 if (Inst.isNotDuplicable) OS << "|M_NOT_DUPLICABLE";
247 if (Inst.usesCustomDAGSchedInserter)
248 OS << "|M_USES_CUSTOM_DAG_SCHED_INSERTION";
249 if (Inst.hasVariableNumberOfOperands)
250 OS << "|M_VARIABLE_OPS";
253 // Emit all of the target-specific flags...
254 ListInit *LI = InstrInfo->getValueAsListInit("TSFlagsFields");
255 ListInit *Shift = InstrInfo->getValueAsListInit("TSFlagsShifts");
256 if (LI->getSize() != Shift->getSize())
257 throw "Lengths of " + InstrInfo->getName() +
258 ":(TargetInfoFields, TargetInfoPositions) must be equal!";
260 for (unsigned i = 0, e = LI->getSize(); i != e; ++i)
261 emitShiftedValue(Inst.TheDef, dynamic_cast<StringInit*>(LI->getElement(i)),
262 dynamic_cast<IntInit*>(Shift->getElement(i)), OS);
266 // Emit the implicit uses and defs lists...
267 std::vector<Record*> UseList = Inst.TheDef->getValueAsListOfDefs("Uses");
271 OS << "ImplicitList" << EmittedLists[UseList] << ", ";
273 std::vector<Record*> DefList = Inst.TheDef->getValueAsListOfDefs("Defs");
277 OS << "ImplicitList" << EmittedLists[DefList] << ", ";
279 // Emit the operand info.
280 std::vector<std::string> OperandInfo = GetOperandInfo(Inst);
281 if (OperandInfo.empty())
284 OS << "OperandInfo" << OpInfo[OperandInfo];
286 OS << " }, // Inst #" << Num << " = " << Inst.TheDef->getName() << "\n";
290 bool operator()(const Record *Rec1, const Record *Rec2) const {
291 return Rec1->getName() < Rec2->getName();
294 void InstrInfoEmitter::GatherItinClasses() {
295 std::vector<Record*> DefList =
296 Records.getAllDerivedDefinitions("InstrItinClass");
297 IsItineraries = !DefList.empty();
299 if (!IsItineraries) return;
301 std::sort(DefList.begin(), DefList.end(), LessRecord());
303 for (unsigned i = 0, N = DefList.size(); i < N; i++) {
304 Record *Def = DefList[i];
305 ItinClassMap[Def->getName()] = i;
309 unsigned InstrInfoEmitter::ItinClassNumber(std::string ItinName) {
310 return ItinClassMap[ItinName];
313 void InstrInfoEmitter::emitShiftedValue(Record *R, StringInit *Val,
314 IntInit *ShiftInt, std::ostream &OS) {
315 if (Val == 0 || ShiftInt == 0)
316 throw std::string("Illegal value or shift amount in TargetInfo*!");
317 RecordVal *RV = R->getValue(Val->getValue());
318 int Shift = ShiftInt->getValue();
320 if (RV == 0 || RV->getValue() == 0) {
321 // This isn't an error if this is a builtin instruction.
322 if (R->getName() != "PHI" &&
323 R->getName() != "INLINEASM" &&
324 R->getName() != "LABEL")
325 throw R->getName() + " doesn't have a field named '" +
326 Val->getValue() + "'!";
330 Init *Value = RV->getValue();
331 if (BitInit *BI = dynamic_cast<BitInit*>(Value)) {
332 if (BI->getValue()) OS << "|(1<<" << Shift << ")";
334 } else if (BitsInit *BI = dynamic_cast<BitsInit*>(Value)) {
335 // Convert the Bits to an integer to print...
336 Init *I = BI->convertInitializerTo(new IntRecTy());
338 if (IntInit *II = dynamic_cast<IntInit*>(I)) {
339 if (II->getValue()) {
341 OS << "|(" << II->getValue() << "<<" << Shift << ")";
343 OS << "|" << II->getValue();
348 } else if (IntInit *II = dynamic_cast<IntInit*>(Value)) {
349 if (II->getValue()) {
351 OS << "|(" << II->getValue() << "<<" << Shift << ")";
353 OS << II->getValue();
358 cerr << "Unhandled initializer: " << *Val << "\n";
359 throw "In record '" + R->getName() + "' for TSFlag emission.";