1 //===- InstrInfoEmitter.cpp - Generate a Instruction Set Desc. ------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend is responsible for emitting a description of the target
11 // instruction set for the code generator.
13 //===----------------------------------------------------------------------===//
15 #include "InstrInfoEmitter.h"
16 #include "CodeGenTarget.h"
21 // runEnums - Print out enum values for all of the instructions.
22 void InstrInfoEmitter::runEnums(std::ostream &OS) {
23 EmitSourceFileHeader("Target Instruction Enum Values", OS);
24 OS << "namespace llvm {\n\n";
28 // We must emit the PHI opcode first...
29 Record *InstrInfo = Target.getInstructionSet();
31 std::string Namespace = Target.inst_begin()->second.Namespace;
33 if (!Namespace.empty())
34 OS << "namespace " << Namespace << " {\n";
37 std::vector<const CodeGenInstruction*> NumberedInstructions;
38 Target.getInstructionsByEnumValue(NumberedInstructions);
40 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
41 OS << " " << NumberedInstructions[i]->TheDef->getName()
42 << ", \t// " << i << "\n";
44 OS << " INSTRUCTION_LIST_END\n";
46 if (!Namespace.empty())
48 OS << "} // End llvm namespace \n";
51 void InstrInfoEmitter::printDefList(const std::vector<Record*> &Uses,
52 unsigned Num, std::ostream &OS) const {
53 OS << "static const unsigned ImplicitList" << Num << "[] = { ";
54 for (unsigned i = 0, e = Uses.size(); i != e; ++i)
55 OS << getQualifiedName(Uses[i]) << ", ";
59 static std::vector<Record*> GetOperandInfo(const CodeGenInstruction &Inst) {
60 std::vector<Record*> Result;
61 if (Inst.hasVariableNumberOfOperands)
62 return Result; // No info for variable operand instrs.
64 for (unsigned i = 0, e = Inst.OperandList.size(); i != e; ++i) {
65 if (Inst.OperandList[i].Rec->isSubClassOf("RegisterClass")) {
66 Result.push_back(Inst.OperandList[i].Rec);
68 // This might be a multiple operand thing.
69 // Targets like X86 have registers in their multi-operand operands.
70 DagInit *MIOI = Inst.OperandList[i].MIOperandInfo;
71 unsigned NumDefs = MIOI->getNumArgs();
72 for (unsigned j = 0, e = Inst.OperandList[i].MINumOperands; j != e; ++j) {
76 DefInit *Def = dynamic_cast<DefInit*>(MIOI->getArg(j));
77 Result.push_back(Def ? Def->getDef() : 0);
86 // run - Emit the main instruction description records for the target...
87 void InstrInfoEmitter::run(std::ostream &OS) {
90 EmitSourceFileHeader("Target Instruction Descriptors", OS);
91 OS << "namespace llvm {\n\n";
94 const std::string &TargetName = Target.getName();
95 Record *InstrInfo = Target.getInstructionSet();
97 // Emit empty implicit uses and defs lists
98 OS << "static const unsigned EmptyImpList[] = { 0 };\n";
100 // Keep track of all of the def lists we have emitted already.
101 std::map<std::vector<Record*>, unsigned> EmittedLists;
102 unsigned ListNumber = 0;
104 // Emit all of the instruction's implicit uses and defs.
105 for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
106 E = Target.inst_end(); II != E; ++II) {
107 Record *Inst = II->second.TheDef;
108 std::vector<Record*> Uses = Inst->getValueAsListOfDefs("Uses");
110 unsigned &IL = EmittedLists[Uses];
111 if (!IL) printDefList(Uses, IL = ++ListNumber, OS);
113 std::vector<Record*> Defs = Inst->getValueAsListOfDefs("Defs");
115 unsigned &IL = EmittedLists[Defs];
116 if (!IL) printDefList(Defs, IL = ++ListNumber, OS);
120 std::map<std::vector<Record*>, unsigned> OperandInfosEmitted;
121 unsigned OperandListNum = 0;
122 OperandInfosEmitted[std::vector<Record*>()] = ++OperandListNum;
124 // Emit all of the operand info records.
126 for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
127 E = Target.inst_end(); II != E; ++II) {
128 std::vector<Record*> OperandInfo = GetOperandInfo(II->second);
129 unsigned &N = OperandInfosEmitted[OperandInfo];
131 N = ++OperandListNum;
132 OS << "static const TargetOperandInfo OperandInfo" << N << "[] = { ";
133 for (unsigned i = 0, e = OperandInfo.size(); i != e; ++i) {
134 Record *RC = OperandInfo[i];
135 // FIXME: We only care about register operands for now.
136 if (RC && RC->isSubClassOf("RegisterClass")) {
137 OS << "{ &" << getQualifiedName(RC) << "RegClass }, ";
146 // Emit all of the TargetInstrDescriptor records in their ENUM ordering.
148 OS << "\nstatic const TargetInstrDescriptor " << TargetName
150 std::vector<const CodeGenInstruction*> NumberedInstructions;
151 Target.getInstructionsByEnumValue(NumberedInstructions);
153 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i)
154 emitRecord(*NumberedInstructions[i], i, InstrInfo, EmittedLists,
155 OperandInfosEmitted, OS);
157 OS << "} // End llvm namespace \n";
160 void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
162 std::map<std::vector<Record*>, unsigned> &EmittedLists,
163 std::map<std::vector<Record*>, unsigned> &OpInfo,
166 if (Inst.hasVariableNumberOfOperands)
168 else if (!Inst.OperandList.empty())
169 // Each logical operand can be multiple MI operands.
170 NumOperands = Inst.OperandList.back().MIOperandNo +
171 Inst.OperandList.back().MINumOperands;
176 if (Inst.Name.empty())
177 OS << Inst.TheDef->getName();
181 unsigned ItinClass = !IsItineraries ? 0 :
182 ItinClassNumber(Inst.TheDef->getValueAsDef("Itinerary")->getName());
184 OS << "\",\t" << NumOperands << ", " << ItinClass
187 // Try to determine (from the pattern), if the instruction is a store.
188 bool isStore = false;
189 if (dynamic_cast<ListInit*>(Inst.TheDef->getValueInit("Pattern"))) {
190 ListInit *LI = Inst.TheDef->getValueAsListInit("Pattern");
191 if (LI && LI->getSize() > 0) {
192 DagInit *Dag = (DagInit *)LI->getElement(0);
193 DefInit *OpDef = dynamic_cast<DefInit*>(Dag->getOperator());
195 Record *Operator = OpDef->getDef();
196 if (Operator->isSubClassOf("SDNode") &&
197 Operator->getValueAsString("Opcode") == "ISD::STORE")
203 // Emit all of the target indepedent flags...
204 if (Inst.isReturn) OS << "|M_RET_FLAG";
205 if (Inst.isBranch) OS << "|M_BRANCH_FLAG";
206 if (Inst.isBarrier) OS << "|M_BARRIER_FLAG";
207 if (Inst.hasDelaySlot) OS << "|M_DELAY_SLOT_FLAG";
208 if (Inst.isCall) OS << "|M_CALL_FLAG";
209 if (Inst.isLoad) OS << "|M_LOAD_FLAG";
210 if (Inst.isStore || isStore) OS << "|M_STORE_FLAG";
211 if (Inst.isTwoAddress) OS << "|M_2_ADDR_FLAG";
212 if (Inst.isConvertibleToThreeAddress) OS << "|M_CONVERTIBLE_TO_3_ADDR";
213 if (Inst.isCommutable) OS << "|M_COMMUTABLE";
214 if (Inst.isTerminator) OS << "|M_TERMINATOR_FLAG";
215 if (Inst.usesCustomDAGSchedInserter)
216 OS << "|M_USES_CUSTOM_DAG_SCHED_INSERTION";
219 // Emit all of the target-specific flags...
220 ListInit *LI = InstrInfo->getValueAsListInit("TSFlagsFields");
221 ListInit *Shift = InstrInfo->getValueAsListInit("TSFlagsShifts");
222 if (LI->getSize() != Shift->getSize())
223 throw "Lengths of " + InstrInfo->getName() +
224 ":(TargetInfoFields, TargetInfoPositions) must be equal!";
226 for (unsigned i = 0, e = LI->getSize(); i != e; ++i)
227 emitShiftedValue(Inst.TheDef, dynamic_cast<StringInit*>(LI->getElement(i)),
228 dynamic_cast<IntInit*>(Shift->getElement(i)), OS);
232 // Emit the implicit uses and defs lists...
233 std::vector<Record*> UseList = Inst.TheDef->getValueAsListOfDefs("Uses");
235 OS << "EmptyImpList, ";
237 OS << "ImplicitList" << EmittedLists[UseList] << ", ";
239 std::vector<Record*> DefList = Inst.TheDef->getValueAsListOfDefs("Defs");
241 OS << "EmptyImpList, ";
243 OS << "ImplicitList" << EmittedLists[DefList] << ", ";
245 // Emit the operand info.
246 std::vector<Record*> OperandInfo = GetOperandInfo(Inst);
247 if (OperandInfo.empty())
250 OS << "OperandInfo" << OpInfo[OperandInfo];
252 OS << " }, // Inst #" << Num << " = " << Inst.TheDef->getName() << "\n";
256 bool operator()(const Record *Rec1, const Record *Rec2) const {
257 return Rec1->getName() < Rec2->getName();
260 void InstrInfoEmitter::GatherItinClasses() {
261 std::vector<Record*> DefList =
262 Records.getAllDerivedDefinitions("InstrItinClass");
263 IsItineraries = !DefList.empty();
265 if (!IsItineraries) return;
267 std::sort(DefList.begin(), DefList.end(), LessRecord());
269 for (unsigned i = 0, N = DefList.size(); i < N; i++) {
270 Record *Def = DefList[i];
271 ItinClassMap[Def->getName()] = i;
275 unsigned InstrInfoEmitter::ItinClassNumber(std::string ItinName) {
276 return ItinClassMap[ItinName];
279 void InstrInfoEmitter::emitShiftedValue(Record *R, StringInit *Val,
280 IntInit *ShiftInt, std::ostream &OS) {
281 if (Val == 0 || ShiftInt == 0)
282 throw std::string("Illegal value or shift amount in TargetInfo*!");
283 RecordVal *RV = R->getValue(Val->getValue());
284 int Shift = ShiftInt->getValue();
286 if (RV == 0 || RV->getValue() == 0) {
287 // This isn't an error if this is a builtin instruction.
288 if (R->getName() != "PHI" && R->getName() != "INLINEASM")
289 throw R->getName() + " doesn't have a field named '" +
290 Val->getValue() + "'!";
294 Init *Value = RV->getValue();
295 if (BitInit *BI = dynamic_cast<BitInit*>(Value)) {
296 if (BI->getValue()) OS << "|(1<<" << Shift << ")";
298 } else if (BitsInit *BI = dynamic_cast<BitsInit*>(Value)) {
299 // Convert the Bits to an integer to print...
300 Init *I = BI->convertInitializerTo(new IntRecTy());
302 if (IntInit *II = dynamic_cast<IntInit*>(I)) {
303 if (II->getValue()) {
305 OS << "|(" << II->getValue() << "<<" << Shift << ")";
307 OS << "|" << II->getValue();
312 } else if (IntInit *II = dynamic_cast<IntInit*>(Value)) {
313 if (II->getValue()) {
315 OS << "|(" << II->getValue() << "<<" << Shift << ")";
317 OS << II->getValue();
322 std::cerr << "Unhandled initializer: " << *Val << "\n";
323 throw "In record '" + R->getName() + "' for TSFlag emission.";