1 //===- FastISelEmitter.cpp - Generate an instruction selector -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend emits a "fast" instruction selector.
12 // This instruction selection method is designed to emit very poor code
13 // quickly. Also, it is not designed to do much lowering, so most illegal
14 // types (e.g. i64 on 32-bit targets) and operations (e.g. calls) are not
15 // supported and cannot easily be added. Blocks containing operations
16 // that are not supported need to be handled by a more capable selector,
17 // such as the SelectionDAG selector.
19 // The intended use for "fast" instruction selection is "-O0" mode
20 // compilation, where the quality of the generated code is irrelevant when
21 // weighed against the speed at which the code can be generated.
23 // If compile time is so important, you might wonder why we don't just
24 // skip codegen all-together, emit LLVM bytecode files, and execute them
25 // with an interpreter. The answer is that it would complicate linking and
26 // debugging, and also because that isn't how a compiler is expected to
27 // work in some circles.
29 // If you need better generated code or more lowering than what this
30 // instruction selector provides, use the SelectionDAG (DAGISel) instruction
31 // selector instead. If you're looking here because SelectionDAG isn't fast
32 // enough, consider looking into improving the SelectionDAG infastructure
33 // instead. At the time of this writing there remain several major
34 // opportunities for improvement.
36 //===----------------------------------------------------------------------===//
38 #include "FastISelEmitter.h"
40 #include "llvm/Support/Debug.h"
41 #include "llvm/Support/Streams.h"
42 #include "llvm/ADT/VectorExtras.h"
47 /// OperandsSignature - This class holds a description of a list of operand
48 /// types. It has utility methods for emitting text based on the operands.
50 struct OperandsSignature {
51 std::vector<std::string> Operands;
53 bool operator<(const OperandsSignature &O) const {
54 return Operands < O.Operands;
57 bool empty() const { return Operands.empty(); }
59 /// initialize - Examine the given pattern and initialize the contents
60 /// of the Operands array accordingly. Return true if all the operands
61 /// are supported, false otherwise.
63 bool initialize(TreePatternNode *InstPatNode,
64 const CodeGenTarget &Target,
65 MVT::SimpleValueType VT,
66 const CodeGenRegisterClass *DstRC) {
67 for (unsigned i = 0, e = InstPatNode->getNumChildren(); i != e; ++i) {
68 TreePatternNode *Op = InstPatNode->getChild(i);
69 // For now, filter out any operand with a predicate.
70 if (!Op->getPredicateFn().empty())
72 // For now, filter out any operand with multiple values.
73 if (Op->getExtTypes().size() != 1)
75 // For now, all the operands must have the same type.
76 if (Op->getTypeNum(0) != VT)
79 if (Op->getOperator()->getName() == "imm") {
80 Operands.push_back("i");
83 // For now, ignore fpimm and other non-leaf nodes.
86 DefInit *OpDI = dynamic_cast<DefInit*>(Op->getLeafValue());
89 Record *OpLeafRec = OpDI->getDef();
90 // TODO: handle instructions which have physreg operands.
91 if (OpLeafRec->isSubClassOf("Register"))
93 // For now, the only other thing we accept is register operands.
94 if (!OpLeafRec->isSubClassOf("RegisterClass"))
96 // For now, require the register operands' register classes to all
98 const CodeGenRegisterClass *RC = &Target.getRegisterClass(OpLeafRec);
101 // For now, all the operands must have the same register class.
104 Operands.push_back("r");
109 void PrintParameters(std::ostream &OS) const {
110 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
111 if (Operands[i] == "r") {
112 OS << "unsigned Op" << i;
113 } else if (Operands[i] == "i") {
114 OS << "uint64_t imm" << i;
116 assert("Unknown operand kind!");
124 void PrintArguments(std::ostream &OS) const {
125 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
126 if (Operands[i] == "r") {
128 } else if (Operands[i] == "i") {
131 assert("Unknown operand kind!");
139 void PrintManglingSuffix(std::ostream &OS) const {
140 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
146 /// InstructionMemo - This class holds additional information about an
147 /// instruction needed to emit code for it.
149 struct InstructionMemo {
151 const CodeGenRegisterClass *RC;
156 static std::string getOpcodeName(Record *Op, CodeGenDAGPatterns &CGP) {
157 return CGP.getSDNodeInfo(Op).getEnumName();
160 static std::string getLegalCName(std::string OpName) {
161 std::string::size_type pos = OpName.find("::");
162 if (pos != std::string::npos)
163 OpName.replace(pos, 2, "_");
167 void FastISelEmitter::run(std::ostream &OS) {
168 EmitSourceFileHeader("\"Fast\" Instruction Selector for the " +
169 Target.getName() + " target", OS);
171 OS << "#include \"llvm/CodeGen/FastISel.h\"\n";
173 OS << "namespace llvm {\n";
175 OS << "namespace " << InstNS.substr(0, InstNS.size() - 2) << " {\n";
178 typedef std::map<std::string, InstructionMemo> PredMap;
179 typedef std::map<MVT::SimpleValueType, PredMap> TypePredMap;
180 typedef std::map<std::string, TypePredMap> OpcodeTypePredMap;
181 typedef std::map<OperandsSignature, OpcodeTypePredMap> OperandsOpcodeTypePredMap;
182 OperandsOpcodeTypePredMap SimplePatterns;
184 // Scan through all the patterns and record the simple ones.
185 for (CodeGenDAGPatterns::ptm_iterator I = CGP.ptm_begin(),
186 E = CGP.ptm_end(); I != E; ++I) {
187 const PatternToMatch &Pattern = *I;
189 // For now, just look at Instructions, so that we don't have to worry
190 // about emitting multiple instructions for a pattern.
191 TreePatternNode *Dst = Pattern.getDstPattern();
192 if (Dst->isLeaf()) continue;
193 Record *Op = Dst->getOperator();
194 if (!Op->isSubClassOf("Instruction"))
196 CodeGenInstruction &II = CGP.getTargetInfo().getInstruction(Op->getName());
197 if (II.OperandList.empty())
200 // For now, ignore instructions where the first operand is not an
202 Record *Op0Rec = II.OperandList[0].Rec;
203 if (!Op0Rec->isSubClassOf("RegisterClass"))
205 const CodeGenRegisterClass *DstRC = &Target.getRegisterClass(Op0Rec);
209 // Inspect the pattern.
210 TreePatternNode *InstPatNode = Pattern.getSrcPattern();
211 if (!InstPatNode) continue;
212 if (InstPatNode->isLeaf()) continue;
214 Record *InstPatOp = InstPatNode->getOperator();
215 std::string OpcodeName = getOpcodeName(InstPatOp, CGP);
216 MVT::SimpleValueType VT = InstPatNode->getTypeNum(0);
218 // For now, filter out instructions which just set a register to
219 // an Operand or an immediate, like MOV32ri.
220 if (InstPatOp->isSubClassOf("Operand"))
222 if (InstPatOp->getName() == "imm" ||
223 InstPatOp->getName() == "fpimm")
226 // For now, filter out any instructions with predicates.
227 if (!InstPatNode->getPredicateFn().empty())
230 // Check all the operands.
231 OperandsSignature Operands;
232 if (!Operands.initialize(InstPatNode, Target, VT, DstRC))
235 // Get the predicate that guards this pattern.
236 std::string PredicateCheck = Pattern.getPredicateCheck();
238 // Ok, we found a pattern that we can handle. Remember it.
239 InstructionMemo Memo = {
240 Pattern.getDstPattern()->getOperator()->getName(),
243 assert(!SimplePatterns[Operands][OpcodeName][VT].count(PredicateCheck) &&
244 "Duplicate pattern!");
245 SimplePatterns[Operands][OpcodeName][VT][PredicateCheck] = Memo;
248 // Declare the target FastISel class.
249 OS << "class FastISel : public llvm::FastISel {\n";
250 for (OperandsOpcodeTypePredMap::const_iterator OI = SimplePatterns.begin(),
251 OE = SimplePatterns.end(); OI != OE; ++OI) {
252 const OperandsSignature &Operands = OI->first;
253 const OpcodeTypePredMap &OTM = OI->second;
255 for (OpcodeTypePredMap::const_iterator I = OTM.begin(), E = OTM.end();
257 const std::string &Opcode = I->first;
258 const TypePredMap &TM = I->second;
260 for (TypePredMap::const_iterator TI = TM.begin(), TE = TM.end();
262 MVT::SimpleValueType VT = TI->first;
264 OS << " unsigned FastEmit_" << getLegalCName(Opcode)
265 << "_" << getLegalCName(getName(VT)) << "_";
266 Operands.PrintManglingSuffix(OS);
268 Operands.PrintParameters(OS);
272 OS << " unsigned FastEmit_" << getLegalCName(Opcode) << "_";
273 Operands.PrintManglingSuffix(OS);
274 OS << "(MVT::SimpleValueType VT";
275 if (!Operands.empty())
277 Operands.PrintParameters(OS);
281 OS << " unsigned FastEmit_";
282 Operands.PrintManglingSuffix(OS);
283 OS << "(MVT::SimpleValueType VT, ISD::NodeType Opcode";
284 if (!Operands.empty())
286 Operands.PrintParameters(OS);
291 // Declare the Subtarget member, which is used for predicate checks.
292 OS << " const " << InstNS.substr(0, InstNS.size() - 2)
293 << "Subtarget *Subtarget;\n";
296 // Declare the constructor.
298 OS << " explicit FastISel(MachineFunction &mf)\n";
299 OS << " : llvm::FastISel(mf),\n";
300 OS << " Subtarget(&TM.getSubtarget<" << InstNS.substr(0, InstNS.size() - 2)
301 << "Subtarget>()) {}\n";
305 // Define the target FastISel creation function.
306 OS << "llvm::FastISel *createFastISel(MachineFunction &mf) {\n";
307 OS << " return new FastISel(mf);\n";
311 // Now emit code for all the patterns that we collected.
312 for (OperandsOpcodeTypePredMap::const_iterator OI = SimplePatterns.begin(),
313 OE = SimplePatterns.end(); OI != OE; ++OI) {
314 const OperandsSignature &Operands = OI->first;
315 const OpcodeTypePredMap &OTM = OI->second;
317 for (OpcodeTypePredMap::const_iterator I = OTM.begin(), E = OTM.end();
319 const std::string &Opcode = I->first;
320 const TypePredMap &TM = I->second;
322 OS << "// FastEmit functions for " << Opcode << ".\n";
325 // Emit one function for each opcode,type pair.
326 for (TypePredMap::const_iterator TI = TM.begin(), TE = TM.end();
328 MVT::SimpleValueType VT = TI->first;
329 const PredMap &PM = TI->second;
330 bool HasPred = false;
332 OS << "unsigned FastISel::FastEmit_"
333 << getLegalCName(Opcode)
334 << "_" << getLegalCName(getName(VT)) << "_";
335 Operands.PrintManglingSuffix(OS);
337 Operands.PrintParameters(OS);
340 // Emit code for each possible instruction. There may be
341 // multiple if there are subtarget concerns.
342 for (PredMap::const_iterator PI = PM.begin(), PE = PM.end();
344 std::string PredicateCheck = PI->first;
345 const InstructionMemo &Memo = PI->second;
347 if (PredicateCheck.empty()) {
348 assert(!HasPred && "Multiple instructions match, at least one has "
349 "a predicate and at least one doesn't!");
351 OS << " if (" + PredicateCheck + ")\n";
355 OS << " return FastEmitInst_";
356 Operands.PrintManglingSuffix(OS);
357 OS << "(" << InstNS << Memo.Name << ", ";
358 OS << InstNS << Memo.RC->getName() << "RegisterClass";
359 if (!Operands.empty())
361 Operands.PrintArguments(OS);
364 // Return 0 if none of the predicates were satisfied.
366 OS << " return 0;\n";
371 // Emit one function for the opcode that demultiplexes based on the type.
372 OS << "unsigned FastISel::FastEmit_"
373 << getLegalCName(Opcode) << "_";
374 Operands.PrintManglingSuffix(OS);
375 OS << "(MVT::SimpleValueType VT";
376 if (!Operands.empty())
378 Operands.PrintParameters(OS);
380 OS << " switch (VT) {\n";
381 for (TypePredMap::const_iterator TI = TM.begin(), TE = TM.end();
383 MVT::SimpleValueType VT = TI->first;
384 std::string TypeName = getName(VT);
385 OS << " case " << TypeName << ": return FastEmit_"
386 << getLegalCName(Opcode) << "_" << getLegalCName(TypeName) << "_";
387 Operands.PrintManglingSuffix(OS);
389 Operands.PrintArguments(OS);
392 OS << " default: return 0;\n";
398 OS << "// Top-level FastEmit function.\n";
401 // Emit one function for the operand signature that demultiplexes based
402 // on opcode and type.
403 OS << "unsigned FastISel::FastEmit_";
404 Operands.PrintManglingSuffix(OS);
405 OS << "(MVT::SimpleValueType VT, ISD::NodeType Opcode";
406 if (!Operands.empty())
408 Operands.PrintParameters(OS);
410 OS << " switch (Opcode) {\n";
411 for (OpcodeTypePredMap::const_iterator I = OTM.begin(), E = OTM.end();
413 const std::string &Opcode = I->first;
415 OS << " case " << Opcode << ": return FastEmit_"
416 << getLegalCName(Opcode) << "_";
417 Operands.PrintManglingSuffix(OS);
419 if (!Operands.empty())
421 Operands.PrintArguments(OS);
424 OS << " default: return 0;\n";
430 OS << "} // namespace X86\n";
432 OS << "} // namespace llvm\n";
435 FastISelEmitter::FastISelEmitter(RecordKeeper &R)
438 Target(CGP.getTargetInfo()),
439 InstNS(Target.getInstNamespace() + "::") {
441 assert(InstNS.size() > 2 && "Can't determine target-specific namespace!");