1 //===- EDEmitter.cpp - Generate instruction descriptions for ED -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend is responsible for emitting a description of each
11 // instruction in a format that the enhanced disassembler can use to tokenize
12 // and parse instructions.
14 //===----------------------------------------------------------------------===//
16 #include "EDEmitter.h"
18 #include "AsmWriterInst.h"
19 #include "CodeGenTarget.h"
22 #include "llvm/MC/EDInstInfo.h"
23 #include "llvm/Support/ErrorHandling.h"
24 #include "llvm/Support/Format.h"
25 #include "llvm/Support/raw_ostream.h"
32 ///////////////////////////////////////////////////////////
33 // Support classes for emitting nested C data structures //
34 ///////////////////////////////////////////////////////////
41 std::vector<std::string> Entries;
43 EnumEmitter(const char *N) : Name(N) {
45 int addEntry(const char *e) {
46 Entries.push_back(std::string(e));
47 return Entries.size() - 1;
49 void emit(raw_ostream &o, unsigned int &i) {
50 o.indent(i) << "enum " << Name.c_str() << " {" << "\n";
53 unsigned int index = 0;
54 unsigned int numEntries = Entries.size();
55 for (index = 0; index < numEntries; ++index) {
56 o.indent(i) << Entries[index];
57 if (index < (numEntries - 1))
63 o.indent(i) << "};" << "\n";
66 void emitAsFlags(raw_ostream &o, unsigned int &i) {
67 o.indent(i) << "enum " << Name.c_str() << " {" << "\n";
70 unsigned int index = 0;
71 unsigned int numEntries = Entries.size();
72 unsigned int flag = 1;
73 for (index = 0; index < numEntries; ++index) {
74 o.indent(i) << Entries[index] << " = " << format("0x%x", flag);
75 if (index < (numEntries - 1))
82 o.indent(i) << "};" << "\n";
86 class ConstantEmitter {
88 virtual ~ConstantEmitter() { }
89 virtual void emit(raw_ostream &o, unsigned int &i) = 0;
92 class LiteralConstantEmitter : public ConstantEmitter {
100 LiteralConstantEmitter(int number = 0) :
104 void set(const char *string) {
109 bool is(const char *string) {
110 return !strcmp(String, string);
112 void emit(raw_ostream &o, unsigned int &i) {
120 class CompoundConstantEmitter : public ConstantEmitter {
122 unsigned int Padding;
123 std::vector<ConstantEmitter *> Entries;
125 CompoundConstantEmitter(unsigned int padding = 0) : Padding(padding) {
127 CompoundConstantEmitter &addEntry(ConstantEmitter *e) {
128 Entries.push_back(e);
132 ~CompoundConstantEmitter() {
133 while (Entries.size()) {
134 ConstantEmitter *entry = Entries.back();
139 void emit(raw_ostream &o, unsigned int &i) {
144 unsigned int numEntries = Entries.size();
146 unsigned int numToPrint;
149 if (numEntries > Padding) {
150 fprintf(stderr, "%u entries but %u padding\n", numEntries, Padding);
151 llvm_unreachable("More entries than padding");
153 numToPrint = Padding;
155 numToPrint = numEntries;
158 for (index = 0; index < numToPrint; ++index) {
160 if (index < numEntries)
161 Entries[index]->emit(o, i);
165 if (index < (numToPrint - 1))
175 class FlagsConstantEmitter : public ConstantEmitter {
177 std::vector<std::string> Flags;
179 FlagsConstantEmitter() {
181 FlagsConstantEmitter &addEntry(const char *f) {
182 Flags.push_back(std::string(f));
185 void emit(raw_ostream &o, unsigned int &i) {
187 unsigned int numFlags = Flags.size();
191 for (index = 0; index < numFlags; ++index) {
192 o << Flags[index].c_str();
193 if (index < (numFlags - 1))
200 EDEmitter::EDEmitter(RecordKeeper &R) : Records(R) {
203 /// populateOperandOrder - Accepts a CodeGenInstruction and generates its
204 /// AsmWriterInst for the desired assembly syntax, giving an ordered list of
205 /// operands in the order they appear in the printed instruction. Then, for
206 /// each entry in that list, determines the index of the same operand in the
207 /// CodeGenInstruction, and emits the resulting mapping into an array, filling
208 /// in unused slots with -1.
210 /// @arg operandOrder - The array that will be populated with the operand
211 /// mapping. Each entry will contain -1 (invalid index
212 /// into the operands present in the AsmString) or a number
213 /// representing an index in the operand descriptor array.
214 /// @arg inst - The instruction to use when looking up the operands
215 /// @arg syntax - The syntax to use, according to LLVM's enumeration
216 void populateOperandOrder(CompoundConstantEmitter *operandOrder,
217 const CodeGenInstruction &inst,
219 unsigned int numArgs = 0;
221 AsmWriterInst awInst(inst, syntax, -1, -1);
223 std::vector<AsmWriterOperand>::iterator operandIterator;
225 for (operandIterator = awInst.Operands.begin();
226 operandIterator != awInst.Operands.end();
228 if (operandIterator->OperandType ==
229 AsmWriterOperand::isMachineInstrOperand) {
230 operandOrder->addEntry(
231 new LiteralConstantEmitter(operandIterator->CGIOpNo));
237 /////////////////////////////////////////////////////
238 // Support functions for handling X86 instructions //
239 /////////////////////////////////////////////////////
241 #define SET(flag) { type->set(flag); return 0; }
243 #define REG(str) if (name == str) SET("kOperandTypeRegister");
244 #define MEM(str) if (name == str) SET("kOperandTypeX86Memory");
245 #define LEA(str) if (name == str) SET("kOperandTypeX86EffectiveAddress");
246 #define IMM(str) if (name == str) SET("kOperandTypeImmediate");
247 #define PCR(str) if (name == str) SET("kOperandTypeX86PCRelative");
249 /// X86TypeFromOpName - Processes the name of a single X86 operand (which is
250 /// actually its type) and translates it into an operand type
252 /// @arg flags - The type object to set
253 /// @arg name - The name of the operand
254 static int X86TypeFromOpName(LiteralConstantEmitter *type,
255 const std::string &name) {
318 PCR("i64i32imm_pcrel");
325 PCR("uncondbrtarget");
328 // all I, ARM mode only, conditional/unconditional
342 /// X86PopulateOperands - Handles all the operands in an X86 instruction, adding
343 /// the appropriate flags to their descriptors
345 /// @operandFlags - A reference the array of operand flag objects
346 /// @inst - The instruction to use as a source of information
347 static void X86PopulateOperands(
348 LiteralConstantEmitter *(&operandTypes)[EDIS_MAX_OPERANDS],
349 const CodeGenInstruction &inst) {
350 if (!inst.TheDef->isSubClassOf("X86Inst"))
354 unsigned int numOperands = inst.Operands.size();
356 for (index = 0; index < numOperands; ++index) {
357 const CGIOperandList::OperandInfo &operandInfo = inst.Operands[index];
358 Record &rec = *operandInfo.Rec;
360 if (X86TypeFromOpName(operandTypes[index], rec.getName()) &&
361 !rec.isSubClassOf("PointerLikeRegClass")) {
362 errs() << "Operand type: " << rec.getName().c_str() << "\n";
363 errs() << "Operand name: " << operandInfo.Name.c_str() << "\n";
364 errs() << "Instruction name: " << inst.TheDef->getName().c_str() << "\n";
365 llvm_unreachable("Unhandled type");
370 /// decorate1 - Decorates a named operand with a new flag
372 /// @operandFlags - The array of operand flag objects, which don't have names
373 /// @inst - The CodeGenInstruction, which provides a way to translate
374 /// between names and operand indices
375 /// @opName - The name of the operand
376 /// @flag - The name of the flag to add
377 static inline void decorate1(
378 FlagsConstantEmitter *(&operandFlags)[EDIS_MAX_OPERANDS],
379 const CodeGenInstruction &inst,
381 const char *opFlag) {
384 opIndex = inst.Operands.getOperandNamed(std::string(opName));
386 operandFlags[opIndex]->addEntry(opFlag);
389 #define DECORATE1(opName, opFlag) decorate1(operandFlags, inst, opName, opFlag)
391 #define MOV(source, target) { \
392 instType.set("kInstructionTypeMove"); \
393 DECORATE1(source, "kOperandFlagSource"); \
394 DECORATE1(target, "kOperandFlagTarget"); \
397 #define BRANCH(target) { \
398 instType.set("kInstructionTypeBranch"); \
399 DECORATE1(target, "kOperandFlagTarget"); \
402 #define PUSH(source) { \
403 instType.set("kInstructionTypePush"); \
404 DECORATE1(source, "kOperandFlagSource"); \
407 #define POP(target) { \
408 instType.set("kInstructionTypePop"); \
409 DECORATE1(target, "kOperandFlagTarget"); \
412 #define CALL(target) { \
413 instType.set("kInstructionTypeCall"); \
414 DECORATE1(target, "kOperandFlagTarget"); \
418 instType.set("kInstructionTypeReturn"); \
421 /// X86ExtractSemantics - Performs various checks on the name of an X86
422 /// instruction to determine what sort of an instruction it is and then adds
423 /// the appropriate flags to the instruction and its operands
425 /// @arg instType - A reference to the type for the instruction as a whole
426 /// @arg operandFlags - A reference to the array of operand flag object pointers
427 /// @arg inst - A reference to the original instruction
428 static void X86ExtractSemantics(
429 LiteralConstantEmitter &instType,
430 FlagsConstantEmitter *(&operandFlags)[EDIS_MAX_OPERANDS],
431 const CodeGenInstruction &inst) {
432 const std::string &name = inst.TheDef->getName();
434 if (name.find("MOV") != name.npos) {
435 if (name.find("MOV_V") != name.npos) {
436 // ignore (this is a pseudoinstruction)
437 } else if (name.find("MASK") != name.npos) {
438 // ignore (this is a masking move)
439 } else if (name.find("r0") != name.npos) {
440 // ignore (this is a pseudoinstruction)
441 } else if (name.find("PS") != name.npos ||
442 name.find("PD") != name.npos) {
443 // ignore (this is a shuffling move)
444 } else if (name.find("MOVS") != name.npos) {
445 // ignore (this is a string move)
446 } else if (name.find("_F") != name.npos) {
447 // TODO handle _F moves to ST(0)
448 } else if (name.find("a") != name.npos) {
449 // TODO handle moves to/from %ax
450 } else if (name.find("CMOV") != name.npos) {
452 } else if (name.find("PC") != name.npos) {
459 if (name.find("JMP") != name.npos ||
460 name.find("J") == 0) {
461 if (name.find("FAR") != name.npos && name.find("i") != name.npos) {
468 if (name.find("PUSH") != name.npos) {
469 if (name.find("CS") != name.npos ||
470 name.find("DS") != name.npos ||
471 name.find("ES") != name.npos ||
472 name.find("FS") != name.npos ||
473 name.find("GS") != name.npos ||
474 name.find("SS") != name.npos) {
475 instType.set("kInstructionTypePush");
476 // TODO add support for fixed operands
477 } else if (name.find("F") != name.npos) {
478 // ignore (this pushes onto the FP stack)
479 } else if (name.find("A") != name.npos) {
480 // ignore (pushes all GP registoers onto the stack)
481 } else if (name[name.length() - 1] == 'm') {
483 } else if (name.find("i") != name.npos) {
490 if (name.find("POP") != name.npos) {
491 if (name.find("POPCNT") != name.npos) {
492 // ignore (not a real pop)
493 } else if (name.find("CS") != name.npos ||
494 name.find("DS") != name.npos ||
495 name.find("ES") != name.npos ||
496 name.find("FS") != name.npos ||
497 name.find("GS") != name.npos ||
498 name.find("SS") != name.npos) {
499 instType.set("kInstructionTypePop");
500 // TODO add support for fixed operands
501 } else if (name.find("F") != name.npos) {
502 // ignore (this pops from the FP stack)
503 } else if (name.find("A") != name.npos) {
504 // ignore (pushes all GP registoers onto the stack)
505 } else if (name[name.length() - 1] == 'm') {
512 if (name.find("CALL") != name.npos) {
513 if (name.find("ADJ") != name.npos) {
514 // ignore (not a call)
515 } else if (name.find("SYSCALL") != name.npos) {
516 // ignore (doesn't go anywhere we know about)
517 } else if (name.find("VMCALL") != name.npos) {
518 // ignore (rather different semantics than a regular call)
519 } else if (name.find("FAR") != name.npos && name.find("i") != name.npos) {
526 if (name.find("RET") != name.npos) {
538 /////////////////////////////////////////////////////
539 // Support functions for handling ARM instructions //
540 /////////////////////////////////////////////////////
542 #define SET(flag) { type->set(flag); return 0; }
544 #define REG(str) if (name == str) SET("kOperandTypeRegister");
545 #define IMM(str) if (name == str) SET("kOperandTypeImmediate");
547 #define MISC(str, type) if (name == str) SET(type);
549 /// ARMFlagFromOpName - Processes the name of a single ARM operand (which is
550 /// actually its type) and translates it into an operand type
552 /// @arg type - The type object to set
553 /// @arg name - The name of the operand
554 static int ARMFlagFromOpName(LiteralConstantEmitter *type,
555 const std::string &name) {
573 IMM("i32imm_hilo16");
574 IMM("bf_inv_mask_imm");
577 IMM("jtblock_operand");
583 IMM("cpinst_operand");
601 IMM("imm0_65535_expr");
605 IMM("jt2block_operand");
606 IMM("t_imm0_1020s4");
613 IMM("neon_vcvt_imm32");
620 IMM("postidx_imm8s4");
624 MISC("brtarget", "kOperandTypeARMBranchTarget"); // ?
625 MISC("uncondbrtarget", "kOperandTypeARMBranchTarget"); // ?
626 MISC("t_brtarget", "kOperandTypeARMBranchTarget"); // ?
627 MISC("t_bcctarget", "kOperandTypeARMBranchTarget"); // ?
628 MISC("t_cbtarget", "kOperandTypeARMBranchTarget"); // ?
629 MISC("bltarget", "kOperandTypeARMBranchTarget"); // ?
631 MISC("br_target", "kOperandTypeARMBranchTarget"); // ?
632 MISC("bl_target", "kOperandTypeARMBranchTarget"); // ?
633 MISC("blx_target", "kOperandTypeARMBranchTarget"); // ?
635 MISC("t_bltarget", "kOperandTypeARMBranchTarget"); // ?
636 MISC("t_blxtarget", "kOperandTypeARMBranchTarget"); // ?
637 MISC("so_reg_imm", "kOperandTypeARMSoRegReg"); // R, R, I
638 MISC("so_reg_reg", "kOperandTypeARMSoRegImm"); // R, R, I
639 MISC("shift_so_reg_reg", "kOperandTypeARMSoRegReg"); // R, R, I
640 MISC("shift_so_reg_imm", "kOperandTypeARMSoRegImm"); // R, R, I
641 MISC("t2_so_reg", "kOperandTypeThumb2SoReg"); // R, I
642 MISC("so_imm", "kOperandTypeARMSoImm"); // I
643 MISC("rot_imm", "kOperandTypeARMRotImm"); // I
644 MISC("t2_so_imm", "kOperandTypeThumb2SoImm"); // I
645 MISC("so_imm2part", "kOperandTypeARMSoImm2Part"); // I
646 MISC("pred", "kOperandTypeARMPredicate"); // I, R
647 MISC("it_pred", "kOperandTypeARMPredicate"); // I
648 MISC("addrmode_imm12", "kOperandTypeAddrModeImm12"); // R, I
649 MISC("ldst_so_reg", "kOperandTypeLdStSOReg"); // R, R, I
650 MISC("postidx_reg", "kOperandTypeARMAddrMode3Offset"); // R, I
651 MISC("addrmode2", "kOperandTypeARMAddrMode2"); // R, R, I
652 MISC("am2offset_reg", "kOperandTypeARMAddrMode2Offset"); // R, I
653 MISC("am2offset_imm", "kOperandTypeARMAddrMode2Offset"); // R, I
654 MISC("addrmode3", "kOperandTypeARMAddrMode3"); // R, R, I
655 MISC("am3offset", "kOperandTypeARMAddrMode3Offset"); // R, I
656 MISC("ldstm_mode", "kOperandTypeARMLdStmMode"); // I
657 MISC("addrmode5", "kOperandTypeARMAddrMode5"); // R, I
658 MISC("addrmode6", "kOperandTypeARMAddrMode6"); // R, R, I, I
659 MISC("am6offset", "kOperandTypeARMAddrMode6Offset"); // R, I, I
660 MISC("addrmode6dup", "kOperandTypeARMAddrMode6"); // R, R, I, I
661 MISC("addrmode6oneL32", "kOperandTypeARMAddrMode6"); // R, R, I, I
662 MISC("addrmodepc", "kOperandTypeARMAddrModePC"); // R, I
663 MISC("addr_offset_none", "kOperandTypeARMAddrMode7"); // R
664 MISC("reglist", "kOperandTypeARMRegisterList"); // I, R, ...
665 MISC("dpr_reglist", "kOperandTypeARMDPRRegisterList"); // I, R, ...
666 MISC("spr_reglist", "kOperandTypeARMSPRRegisterList"); // I, R, ...
667 MISC("it_mask", "kOperandTypeThumbITMask"); // I
668 MISC("t2addrmode_reg", "kOperandTypeThumb2AddrModeReg"); // R
669 MISC("t2addrmode_imm8", "kOperandTypeThumb2AddrModeImm8"); // R, I
670 MISC("t2am_imm8_offset", "kOperandTypeThumb2AddrModeImm8Offset");//I
671 MISC("t2addrmode_imm12", "kOperandTypeThumb2AddrModeImm12"); // R, I
672 MISC("t2addrmode_so_reg", "kOperandTypeThumb2AddrModeSoReg"); // R, R, I
673 MISC("t2addrmode_imm8s4", "kOperandTypeThumb2AddrModeImm8s4"); // R, I
674 MISC("t2am_imm8s4_offset", "kOperandTypeThumb2AddrModeImm8s4Offset");
676 MISC("tb_addrmode", "kOperandTypeARMTBAddrMode"); // I
677 MISC("t_addrmode_rrs1", "kOperandTypeThumbAddrModeRegS1"); // R, R
678 MISC("t_addrmode_rrs2", "kOperandTypeThumbAddrModeRegS2"); // R, R
679 MISC("t_addrmode_rrs4", "kOperandTypeThumbAddrModeRegS4"); // R, R
680 MISC("t_addrmode_is1", "kOperandTypeThumbAddrModeImmS1"); // R, I
681 MISC("t_addrmode_is2", "kOperandTypeThumbAddrModeImmS2"); // R, I
682 MISC("t_addrmode_is4", "kOperandTypeThumbAddrModeImmS4"); // R, I
683 MISC("t_addrmode_rr", "kOperandTypeThumbAddrModeRR"); // R, R
684 MISC("t_addrmode_sp", "kOperandTypeThumbAddrModeSP"); // R, I
685 MISC("t_addrmode_pc", "kOperandTypeThumbAddrModePC"); // R, I
696 /// ARMPopulateOperands - Handles all the operands in an ARM instruction, adding
697 /// the appropriate flags to their descriptors
699 /// @operandFlags - A reference the array of operand flag objects
700 /// @inst - The instruction to use as a source of information
701 static void ARMPopulateOperands(
702 LiteralConstantEmitter *(&operandTypes)[EDIS_MAX_OPERANDS],
703 const CodeGenInstruction &inst) {
704 if (!inst.TheDef->isSubClassOf("InstARM") &&
705 !inst.TheDef->isSubClassOf("InstThumb"))
709 unsigned int numOperands = inst.Operands.size();
711 if (numOperands > EDIS_MAX_OPERANDS) {
712 errs() << "numOperands == " << numOperands << " > " <<
713 EDIS_MAX_OPERANDS << '\n';
714 llvm_unreachable("Too many operands");
717 for (index = 0; index < numOperands; ++index) {
718 const CGIOperandList::OperandInfo &operandInfo = inst.Operands[index];
719 Record &rec = *operandInfo.Rec;
721 if (ARMFlagFromOpName(operandTypes[index], rec.getName())) {
722 errs() << "Operand type: " << rec.getName() << '\n';
723 errs() << "Operand name: " << operandInfo.Name << '\n';
724 errs() << "Instruction name: " << inst.TheDef->getName() << '\n';
725 llvm_unreachable("Unhandled type");
730 #define BRANCH(target) { \
731 instType.set("kInstructionTypeBranch"); \
732 DECORATE1(target, "kOperandFlagTarget"); \
735 /// ARMExtractSemantics - Performs various checks on the name of an ARM
736 /// instruction to determine what sort of an instruction it is and then adds
737 /// the appropriate flags to the instruction and its operands
739 /// @arg instType - A reference to the type for the instruction as a whole
740 /// @arg operandTypes - A reference to the array of operand type object pointers
741 /// @arg operandFlags - A reference to the array of operand flag object pointers
742 /// @arg inst - A reference to the original instruction
743 static void ARMExtractSemantics(
744 LiteralConstantEmitter &instType,
745 LiteralConstantEmitter *(&operandTypes)[EDIS_MAX_OPERANDS],
746 FlagsConstantEmitter *(&operandFlags)[EDIS_MAX_OPERANDS],
747 const CodeGenInstruction &inst) {
748 const std::string &name = inst.TheDef->getName();
750 if (name == "tBcc" ||
759 if (name == "tBLr9" ||
760 name == "BLr9_pred" ||
761 name == "tBLXi_r9" ||
762 name == "tBLXr_r9" ||
769 opIndex = inst.Operands.getOperandNamed("func");
770 if (operandTypes[opIndex]->is("kOperandTypeImmediate"))
771 operandTypes[opIndex]->set("kOperandTypeARMBranchTarget");
777 /// populateInstInfo - Fills an array of InstInfos with information about each
778 /// instruction in a target
780 /// @arg infoArray - The array of InstInfo objects to populate
781 /// @arg target - The CodeGenTarget to use as a source of instructions
782 static void populateInstInfo(CompoundConstantEmitter &infoArray,
783 CodeGenTarget &target) {
784 const std::vector<const CodeGenInstruction*> &numberedInstructions =
785 target.getInstructionsByEnumValue();
788 unsigned int numInstructions = numberedInstructions.size();
790 for (index = 0; index < numInstructions; ++index) {
791 const CodeGenInstruction& inst = *numberedInstructions[index];
793 // We don't need to do anything for pseudo-instructions, as we'll never
794 // see them here. We'll only see real instructions.
798 CompoundConstantEmitter *infoStruct = new CompoundConstantEmitter;
799 infoArray.addEntry(infoStruct);
801 LiteralConstantEmitter *instType = new LiteralConstantEmitter;
802 infoStruct->addEntry(instType);
804 LiteralConstantEmitter *numOperandsEmitter =
805 new LiteralConstantEmitter(inst.Operands.size());
806 infoStruct->addEntry(numOperandsEmitter);
808 CompoundConstantEmitter *operandTypeArray = new CompoundConstantEmitter;
809 infoStruct->addEntry(operandTypeArray);
811 LiteralConstantEmitter *operandTypes[EDIS_MAX_OPERANDS];
813 CompoundConstantEmitter *operandFlagArray = new CompoundConstantEmitter;
814 infoStruct->addEntry(operandFlagArray);
816 FlagsConstantEmitter *operandFlags[EDIS_MAX_OPERANDS];
818 for (unsigned operandIndex = 0;
819 operandIndex < EDIS_MAX_OPERANDS;
821 operandTypes[operandIndex] = new LiteralConstantEmitter;
822 operandTypeArray->addEntry(operandTypes[operandIndex]);
824 operandFlags[operandIndex] = new FlagsConstantEmitter;
825 operandFlagArray->addEntry(operandFlags[operandIndex]);
828 unsigned numSyntaxes = 0;
830 if (target.getName() == "X86") {
831 X86PopulateOperands(operandTypes, inst);
832 X86ExtractSemantics(*instType, operandFlags, inst);
835 else if (target.getName() == "ARM") {
836 ARMPopulateOperands(operandTypes, inst);
837 ARMExtractSemantics(*instType, operandTypes, operandFlags, inst);
841 CompoundConstantEmitter *operandOrderArray = new CompoundConstantEmitter;
843 infoStruct->addEntry(operandOrderArray);
845 for (unsigned syntaxIndex = 0;
846 syntaxIndex < EDIS_MAX_SYNTAXES;
848 CompoundConstantEmitter *operandOrder =
849 new CompoundConstantEmitter(EDIS_MAX_OPERANDS);
851 operandOrderArray->addEntry(operandOrder);
853 if (syntaxIndex < numSyntaxes) {
854 populateOperandOrder(operandOrder, inst, syntaxIndex);
862 static void emitCommonEnums(raw_ostream &o, unsigned int &i) {
863 EnumEmitter operandTypes("OperandTypes");
864 operandTypes.addEntry("kOperandTypeNone");
865 operandTypes.addEntry("kOperandTypeImmediate");
866 operandTypes.addEntry("kOperandTypeRegister");
867 operandTypes.addEntry("kOperandTypeX86Memory");
868 operandTypes.addEntry("kOperandTypeX86EffectiveAddress");
869 operandTypes.addEntry("kOperandTypeX86PCRelative");
870 operandTypes.addEntry("kOperandTypeARMBranchTarget");
871 operandTypes.addEntry("kOperandTypeARMSoRegReg");
872 operandTypes.addEntry("kOperandTypeARMSoRegImm");
873 operandTypes.addEntry("kOperandTypeARMSoImm");
874 operandTypes.addEntry("kOperandTypeARMRotImm");
875 operandTypes.addEntry("kOperandTypeARMSoImm2Part");
876 operandTypes.addEntry("kOperandTypeARMPredicate");
877 operandTypes.addEntry("kOperandTypeAddrModeImm12");
878 operandTypes.addEntry("kOperandTypeLdStSOReg");
879 operandTypes.addEntry("kOperandTypeARMAddrMode2");
880 operandTypes.addEntry("kOperandTypeARMAddrMode2Offset");
881 operandTypes.addEntry("kOperandTypeARMAddrMode3");
882 operandTypes.addEntry("kOperandTypeARMAddrMode3Offset");
883 operandTypes.addEntry("kOperandTypeARMLdStmMode");
884 operandTypes.addEntry("kOperandTypeARMAddrMode5");
885 operandTypes.addEntry("kOperandTypeARMAddrMode6");
886 operandTypes.addEntry("kOperandTypeARMAddrMode6Offset");
887 operandTypes.addEntry("kOperandTypeARMAddrMode7");
888 operandTypes.addEntry("kOperandTypeARMAddrModePC");
889 operandTypes.addEntry("kOperandTypeARMRegisterList");
890 operandTypes.addEntry("kOperandTypeARMDPRRegisterList");
891 operandTypes.addEntry("kOperandTypeARMSPRRegisterList");
892 operandTypes.addEntry("kOperandTypeARMTBAddrMode");
893 operandTypes.addEntry("kOperandTypeThumbITMask");
894 operandTypes.addEntry("kOperandTypeThumbAddrModeImmS1");
895 operandTypes.addEntry("kOperandTypeThumbAddrModeImmS2");
896 operandTypes.addEntry("kOperandTypeThumbAddrModeImmS4");
897 operandTypes.addEntry("kOperandTypeThumbAddrModeRegS1");
898 operandTypes.addEntry("kOperandTypeThumbAddrModeRegS2");
899 operandTypes.addEntry("kOperandTypeThumbAddrModeRegS4");
900 operandTypes.addEntry("kOperandTypeThumbAddrModeRR");
901 operandTypes.addEntry("kOperandTypeThumbAddrModeSP");
902 operandTypes.addEntry("kOperandTypeThumbAddrModePC");
903 operandTypes.addEntry("kOperandTypeThumb2AddrModeReg");
904 operandTypes.addEntry("kOperandTypeThumb2SoReg");
905 operandTypes.addEntry("kOperandTypeThumb2SoImm");
906 operandTypes.addEntry("kOperandTypeThumb2AddrModeImm8");
907 operandTypes.addEntry("kOperandTypeThumb2AddrModeImm8Offset");
908 operandTypes.addEntry("kOperandTypeThumb2AddrModeImm12");
909 operandTypes.addEntry("kOperandTypeThumb2AddrModeSoReg");
910 operandTypes.addEntry("kOperandTypeThumb2AddrModeImm8s4");
911 operandTypes.addEntry("kOperandTypeThumb2AddrModeImm8s4Offset");
912 operandTypes.emit(o, i);
916 EnumEmitter operandFlags("OperandFlags");
917 operandFlags.addEntry("kOperandFlagSource");
918 operandFlags.addEntry("kOperandFlagTarget");
919 operandFlags.emitAsFlags(o, i);
923 EnumEmitter instructionTypes("InstructionTypes");
924 instructionTypes.addEntry("kInstructionTypeNone");
925 instructionTypes.addEntry("kInstructionTypeMove");
926 instructionTypes.addEntry("kInstructionTypeBranch");
927 instructionTypes.addEntry("kInstructionTypePush");
928 instructionTypes.addEntry("kInstructionTypePop");
929 instructionTypes.addEntry("kInstructionTypeCall");
930 instructionTypes.addEntry("kInstructionTypeReturn");
931 instructionTypes.emit(o, i);
936 void EDEmitter::run(raw_ostream &o) {
939 CompoundConstantEmitter infoArray;
940 CodeGenTarget target(Records);
942 populateInstInfo(infoArray, target);
944 emitCommonEnums(o, i);
946 o << "namespace {\n";
948 o << "llvm::EDInstInfo instInfo" << target.getName().c_str() << "[] = ";
949 infoArray.emit(o, i);