1 //===- DAGISelMatcherGen.cpp - Matcher generator --------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "DAGISelMatcher.h"
11 #include "CodeGenDAGPatterns.h"
13 #include "llvm/ADT/SmallVector.h"
14 #include "llvm/ADT/StringMap.h"
19 /// getRegisterValueType - Look up and return the ValueType of the specified
20 /// register. If the register is a member of multiple register classes which
21 /// have different associated types, return MVT::Other.
22 static MVT::SimpleValueType getRegisterValueType(Record *R,
23 const CodeGenTarget &T) {
25 MVT::SimpleValueType VT = MVT::Other;
26 const std::vector<CodeGenRegisterClass> &RCs = T.getRegisterClasses();
27 std::vector<Record*>::const_iterator Element;
29 for (unsigned rc = 0, e = RCs.size(); rc != e; ++rc) {
30 const CodeGenRegisterClass &RC = RCs[rc];
31 if (!std::count(RC.Elements.begin(), RC.Elements.end(), R))
36 VT = RC.getValueTypeNum(0);
40 // In multiple RC's. If the Types of the RC's do not agree, return
41 // MVT::Other. The target is responsible for handling this.
42 if (VT != RC.getValueTypeNum(0))
43 // FIXME2: when does this happen? Abort?
52 const PatternToMatch &Pattern;
53 const CodeGenDAGPatterns &CGP;
55 /// PatWithNoTypes - This is a clone of Pattern.getSrcPattern() that starts
56 /// out with all of the types removed. This allows us to insert type checks
57 /// as we scan the tree.
58 TreePatternNode *PatWithNoTypes;
60 /// VariableMap - A map from variable names ('$dst') to the recorded operand
61 /// number that they were captured as. These are biased by 1 to make
63 StringMap<unsigned> VariableMap;
65 /// NextRecordedOperandNo - As we emit opcodes to record matched values in
66 /// the RecordedNodes array, this keeps track of which slot will be next to
68 unsigned NextRecordedOperandNo;
70 /// MatchedChainNodes - This maintains the position in the recorded nodes
71 /// array of all of the recorded input nodes that have chains.
72 SmallVector<unsigned, 2> MatchedChainNodes;
74 /// MatchedFlagResultNodes - This maintains the position in the recorded
75 /// nodes array of all of the recorded input nodes that have flag results.
76 SmallVector<unsigned, 2> MatchedFlagResultNodes;
78 /// PhysRegInputs - List list has an entry for each explicitly specified
79 /// physreg input to the pattern. The first elt is the Register node, the
80 /// second is the recorded slot number the input pattern match saved it in.
81 SmallVector<std::pair<Record*, unsigned>, 2> PhysRegInputs;
83 /// EmittedMergeInputChains - For nodes that match patterns involving
84 /// chains, is set to true if we emitted the "MergeInputChains" operation.
85 bool EmittedMergeInputChains;
87 /// Matcher - This is the top level of the generated matcher, the result.
90 /// CurPredicate - As we emit matcher nodes, this points to the latest check
91 /// which should have future checks stuck into its Next position.
92 Matcher *CurPredicate;
94 MatcherGen(const PatternToMatch &pattern, const CodeGenDAGPatterns &cgp);
97 delete PatWithNoTypes;
100 bool EmitMatcherCode(unsigned Variant);
101 void EmitResultCode();
103 Matcher *GetMatcher() const { return TheMatcher; }
104 Matcher *GetCurPredicate() const { return CurPredicate; }
106 void AddMatcher(Matcher *NewNode);
107 void InferPossibleTypes();
109 // Matcher Generation.
110 void EmitMatchCode(const TreePatternNode *N, TreePatternNode *NodeNoTypes);
111 void EmitLeafMatchCode(const TreePatternNode *N);
112 void EmitOperatorMatchCode(const TreePatternNode *N,
113 TreePatternNode *NodeNoTypes);
115 // Result Code Generation.
116 unsigned getNamedArgumentSlot(StringRef Name) {
117 unsigned VarMapEntry = VariableMap[Name];
118 assert(VarMapEntry != 0 &&
119 "Variable referenced but not defined and not caught earlier!");
120 return VarMapEntry-1;
123 /// GetInstPatternNode - Get the pattern for an instruction.
124 const TreePatternNode *GetInstPatternNode(const DAGInstruction &Ins,
125 const TreePatternNode *N);
127 void EmitResultOperand(const TreePatternNode *N,
128 SmallVectorImpl<unsigned> &ResultOps);
129 void EmitResultOfNamedOperand(const TreePatternNode *N,
130 SmallVectorImpl<unsigned> &ResultOps);
131 void EmitResultLeafAsOperand(const TreePatternNode *N,
132 SmallVectorImpl<unsigned> &ResultOps);
133 void EmitResultInstructionAsOperand(const TreePatternNode *N,
134 SmallVectorImpl<unsigned> &ResultOps);
135 void EmitResultSDNodeXFormAsOperand(const TreePatternNode *N,
136 SmallVectorImpl<unsigned> &ResultOps);
139 } // end anon namespace.
141 MatcherGen::MatcherGen(const PatternToMatch &pattern,
142 const CodeGenDAGPatterns &cgp)
143 : Pattern(pattern), CGP(cgp), NextRecordedOperandNo(0),
144 EmittedMergeInputChains(false), TheMatcher(0), CurPredicate(0) {
145 // We need to produce the matcher tree for the patterns source pattern. To do
146 // this we need to match the structure as well as the types. To do the type
147 // matching, we want to figure out the fewest number of type checks we need to
148 // emit. For example, if there is only one integer type supported by a
149 // target, there should be no type comparisons at all for integer patterns!
151 // To figure out the fewest number of type checks needed, clone the pattern,
152 // remove the types, then perform type inference on the pattern as a whole.
153 // If there are unresolved types, emit an explicit check for those types,
154 // apply the type to the tree, then rerun type inference. Iterate until all
155 // types are resolved.
157 PatWithNoTypes = Pattern.getSrcPattern()->clone();
158 PatWithNoTypes->RemoveAllTypes();
160 // If there are types that are manifestly known, infer them.
161 InferPossibleTypes();
164 /// InferPossibleTypes - As we emit the pattern, we end up generating type
165 /// checks and applying them to the 'PatWithNoTypes' tree. As we do this, we
166 /// want to propagate implied types as far throughout the tree as possible so
167 /// that we avoid doing redundant type checks. This does the type propagation.
168 void MatcherGen::InferPossibleTypes() {
169 // TP - Get *SOME* tree pattern, we don't care which. It is only used for
170 // diagnostics, which we know are impossible at this point.
171 TreePattern &TP = *CGP.pf_begin()->second;
174 bool MadeChange = true;
176 MadeChange = PatWithNoTypes->ApplyTypeConstraints(TP,
177 true/*Ignore reg constraints*/);
179 errs() << "Type constraint application shouldn't fail!";
185 /// AddMatcher - Add a matcher node to the current graph we're building.
186 void MatcherGen::AddMatcher(Matcher *NewNode) {
187 if (CurPredicate != 0)
188 CurPredicate->setNext(NewNode);
190 TheMatcher = NewNode;
191 CurPredicate = NewNode;
195 //===----------------------------------------------------------------------===//
196 // Pattern Match Generation
197 //===----------------------------------------------------------------------===//
199 /// EmitLeafMatchCode - Generate matching code for leaf nodes.
200 void MatcherGen::EmitLeafMatchCode(const TreePatternNode *N) {
201 assert(N->isLeaf() && "Not a leaf?");
203 // If there are node predicates for this node, generate their checks.
204 for (unsigned i = 0, e = N->getPredicateFns().size(); i != e; ++i)
205 AddMatcher(new CheckPredicateMatcher(N->getPredicateFns()[i]));
207 // Direct match against an integer constant.
208 if (IntInit *II = dynamic_cast<IntInit*>(N->getLeafValue()))
209 return AddMatcher(new CheckIntegerMatcher(II->getValue()));
211 DefInit *DI = dynamic_cast<DefInit*>(N->getLeafValue());
213 errs() << "Unknown leaf kind: " << *DI << "\n";
217 Record *LeafRec = DI->getDef();
218 if (// Handle register references. Nothing to do here, they always match.
219 LeafRec->isSubClassOf("RegisterClass") ||
220 LeafRec->isSubClassOf("PointerLikeRegClass") ||
221 // Place holder for SRCVALUE nodes. Nothing to do here.
222 LeafRec->getName() == "srcvalue")
225 // If we have a physreg reference like (mul gpr:$src, EAX) then we need to
226 // record the register
227 if (LeafRec->isSubClassOf("Register")) {
228 AddMatcher(new RecordMatcher("physreg input "+LeafRec->getName(),
229 NextRecordedOperandNo));
230 PhysRegInputs.push_back(std::make_pair(LeafRec, NextRecordedOperandNo++));
234 if (LeafRec->isSubClassOf("ValueType"))
235 return AddMatcher(new CheckValueTypeMatcher(LeafRec->getName()));
237 if (LeafRec->isSubClassOf("CondCode"))
238 return AddMatcher(new CheckCondCodeMatcher(LeafRec->getName()));
240 if (LeafRec->isSubClassOf("ComplexPattern")) {
241 // We can't model ComplexPattern uses that don't have their name taken yet.
242 // The OPC_CheckComplexPattern operation implicitly records the results.
243 if (N->getName().empty()) {
244 errs() << "We expect complex pattern uses to have names: " << *N << "\n";
248 // Handle complex pattern.
249 const ComplexPattern &CP = CGP.getComplexPattern(LeafRec);
251 // Emit a CheckComplexPat operation, which does the match (aborting if it
252 // fails) and pushes the matched operands onto the recorded nodes list.
253 AddMatcher(new CheckComplexPatMatcher(CP));
255 // Record the right number of operands.
256 NextRecordedOperandNo += CP.getNumOperands();
257 if (CP.hasProperty(SDNPHasChain))
258 ++NextRecordedOperandNo; // Chained node operand.
260 // If the complex pattern has a chain, then we need to keep track of the
261 // fact that we just recorded a chain input. The chain input will be
262 // matched as the last operand of the predicate if it was successful.
263 if (CP.hasProperty(SDNPHasChain)) {
264 // It is the last operand recorded.
265 assert(NextRecordedOperandNo > 1 &&
266 "Should have recorded input/result chains at least!");
267 MatchedChainNodes.push_back(NextRecordedOperandNo-1);
269 // If we need to check chains, do so, see comment for
270 // "NodeHasProperty(SDNPHasChain" below.
271 if (MatchedChainNodes.size() > 1) {
272 // FIXME2: This is broken, we should eliminate this nonsense completely,
273 // but we want to produce the same selections that the old matcher does
275 unsigned PrevOp = MatchedChainNodes[MatchedChainNodes.size()-2];
276 AddMatcher(new CheckChainCompatibleMatcher(PrevOp));
280 // TODO: Complex patterns can't have output flags, if they did, we'd want
285 errs() << "Unknown leaf kind: " << *N << "\n";
289 void MatcherGen::EmitOperatorMatchCode(const TreePatternNode *N,
290 TreePatternNode *NodeNoTypes) {
291 assert(!N->isLeaf() && "Not an operator?");
292 const SDNodeInfo &CInfo = CGP.getSDNodeInfo(N->getOperator());
294 // If this is an 'and R, 1234' where the operation is AND/OR and the RHS is
295 // a constant without a predicate fn that has more that one bit set, handle
296 // this as a special case. This is usually for targets that have special
297 // handling of certain large constants (e.g. alpha with it's 8/16/32-bit
298 // handling stuff). Using these instructions is often far more efficient
299 // than materializing the constant. Unfortunately, both the instcombiner
300 // and the dag combiner can often infer that bits are dead, and thus drop
301 // them from the mask in the dag. For example, it might turn 'AND X, 255'
302 // into 'AND X, 254' if it knows the low bit is set. Emit code that checks
304 if ((N->getOperator()->getName() == "and" ||
305 N->getOperator()->getName() == "or") &&
306 N->getChild(1)->isLeaf() && N->getChild(1)->getPredicateFns().empty() &&
307 N->getPredicateFns().empty()) {
308 if (IntInit *II = dynamic_cast<IntInit*>(N->getChild(1)->getLeafValue())) {
309 if (!isPowerOf2_32(II->getValue())) { // Don't bother with single bits.
310 // If this is at the root of the pattern, we emit a redundant
311 // CheckOpcode so that the following checks get factored properly under
312 // a single opcode check.
313 if (N == Pattern.getSrcPattern())
314 AddMatcher(new CheckOpcodeMatcher(CInfo));
316 // Emit the CheckAndImm/CheckOrImm node.
317 if (N->getOperator()->getName() == "and")
318 AddMatcher(new CheckAndImmMatcher(II->getValue()));
320 AddMatcher(new CheckOrImmMatcher(II->getValue()));
322 // Match the LHS of the AND as appropriate.
323 AddMatcher(new MoveChildMatcher(0));
324 EmitMatchCode(N->getChild(0), NodeNoTypes->getChild(0));
325 AddMatcher(new MoveParentMatcher());
331 // Check that the current opcode lines up.
332 AddMatcher(new CheckOpcodeMatcher(CInfo));
334 // If there are node predicates for this node, generate their checks.
335 for (unsigned i = 0, e = N->getPredicateFns().size(); i != e; ++i)
336 AddMatcher(new CheckPredicateMatcher(N->getPredicateFns()[i]));
339 // If this node has memory references (i.e. is a load or store), tell the
340 // interpreter to capture them in the memref array.
341 if (N->NodeHasProperty(SDNPMemOperand, CGP))
342 AddMatcher(new RecordMemRefMatcher());
344 // If this node has a chain, then the chain is operand #0 is the SDNode, and
345 // the child numbers of the node are all offset by one.
347 if (N->NodeHasProperty(SDNPHasChain, CGP)) {
348 // Record the node and remember it in our chained nodes list.
349 AddMatcher(new RecordMatcher("'" + N->getOperator()->getName() +
351 NextRecordedOperandNo));
352 // Remember all of the input chains our pattern will match.
353 MatchedChainNodes.push_back(NextRecordedOperandNo++);
355 // If this is the second (e.g. indbr(load) or store(add(load))) or third
356 // input chain (e.g. (store (add (load, load))) from msp430) we need to make
357 // sure that folding the chain won't induce cycles in the DAG. This could
358 // happen if there were an intermediate node between the indbr and load, for
360 if (MatchedChainNodes.size() > 1) {
361 // FIXME2: This is broken, we should eliminate this nonsense completely,
362 // but we want to produce the same selections that the old matcher does
364 unsigned PrevOp = MatchedChainNodes[MatchedChainNodes.size()-2];
365 AddMatcher(new CheckChainCompatibleMatcher(PrevOp));
368 // Don't look at the input chain when matching the tree pattern to the
372 // If this node is not the root and the subtree underneath it produces a
373 // chain, then the result of matching the node is also produce a chain.
374 // Beyond that, this means that we're also folding (at least) the root node
375 // into the node that produce the chain (for example, matching
376 // "(add reg, (load ptr))" as a add_with_memory on X86). This is
377 // problematic, if the 'reg' node also uses the load (say, its chain).
382 // | \ DAG's like cheese.
388 // It would be invalid to fold XX and LD. In this case, folding the two
389 // nodes together would induce a cycle in the DAG, making it a 'cyclic DAG'
390 // To prevent this, we emit a dynamic check for legality before allowing
391 // this to be folded.
393 const TreePatternNode *Root = Pattern.getSrcPattern();
394 if (N != Root) { // Not the root of the pattern.
395 // If there is a node between the root and this node, then we definitely
396 // need to emit the check.
397 bool NeedCheck = !Root->hasChild(N);
399 // If it *is* an immediate child of the root, we can still need a check if
400 // the root SDNode has multiple inputs. For us, this means that it is an
401 // intrinsic, has multiple operands, or has other inputs like chain or
404 const SDNodeInfo &PInfo = CGP.getSDNodeInfo(Root->getOperator());
406 Root->getOperator() == CGP.get_intrinsic_void_sdnode() ||
407 Root->getOperator() == CGP.get_intrinsic_w_chain_sdnode() ||
408 Root->getOperator() == CGP.get_intrinsic_wo_chain_sdnode() ||
409 PInfo.getNumOperands() > 1 ||
410 PInfo.hasProperty(SDNPHasChain) ||
411 PInfo.hasProperty(SDNPInFlag) ||
412 PInfo.hasProperty(SDNPOptInFlag);
416 AddMatcher(new CheckFoldableChainNodeMatcher());
420 // If this node has an output flag and isn't the root, remember it.
421 if (N->NodeHasProperty(SDNPOutFlag, CGP) &&
422 N != Pattern.getSrcPattern()) {
423 // TODO: This redundantly records nodes with both flags and chains.
425 // Record the node and remember it in our chained nodes list.
426 AddMatcher(new RecordMatcher("'" + N->getOperator()->getName() +
427 "' flag output node",
428 NextRecordedOperandNo));
429 // Remember all of the nodes with output flags our pattern will match.
430 MatchedFlagResultNodes.push_back(NextRecordedOperandNo++);
433 // If this node is known to have an input flag or if it *might* have an input
434 // flag, capture it as the flag input of the pattern.
435 if (N->NodeHasProperty(SDNPOptInFlag, CGP) ||
436 N->NodeHasProperty(SDNPInFlag, CGP))
437 AddMatcher(new CaptureFlagInputMatcher());
439 for (unsigned i = 0, e = N->getNumChildren(); i != e; ++i, ++OpNo) {
440 // Get the code suitable for matching this child. Move to the child, check
441 // it then move back to the parent.
442 AddMatcher(new MoveChildMatcher(OpNo));
443 EmitMatchCode(N->getChild(i), NodeNoTypes->getChild(i));
444 AddMatcher(new MoveParentMatcher());
449 void MatcherGen::EmitMatchCode(const TreePatternNode *N,
450 TreePatternNode *NodeNoTypes) {
451 // If N and NodeNoTypes don't agree on a type, then this is a case where we
452 // need to do a type check. Emit the check, apply the tyep to NodeNoTypes and
453 // reinfer any correlated types.
454 if (NodeNoTypes->getExtTypes() != N->getExtTypes()) {
455 AddMatcher(new CheckTypeMatcher(N->getTypeNum(0)));
456 NodeNoTypes->setTypes(N->getExtTypes());
457 InferPossibleTypes();
460 // If this node has a name associated with it, capture it in VariableMap. If
461 // we already saw this in the pattern, emit code to verify dagness.
462 if (!N->getName().empty()) {
463 unsigned &VarMapEntry = VariableMap[N->getName()];
464 if (VarMapEntry == 0) {
465 // If it is a named node, we must emit a 'Record' opcode.
466 AddMatcher(new RecordMatcher("$" + N->getName(), NextRecordedOperandNo));
467 VarMapEntry = ++NextRecordedOperandNo;
469 // If we get here, this is a second reference to a specific name. Since
470 // we already have checked that the first reference is valid, we don't
471 // have to recursively match it, just check that it's the same as the
472 // previously named thing.
473 AddMatcher(new CheckSameMatcher(VarMapEntry-1));
479 EmitLeafMatchCode(N);
481 EmitOperatorMatchCode(N, NodeNoTypes);
484 /// EmitMatcherCode - Generate the code that matches the predicate of this
485 /// pattern for the specified Variant. If the variant is invalid this returns
486 /// true and does not generate code, if it is valid, it returns false.
487 bool MatcherGen::EmitMatcherCode(unsigned Variant) {
488 // If the root of the pattern is a ComplexPattern and if it is specified to
489 // match some number of root opcodes, these are considered to be our variants.
490 // Depending on which variant we're generating code for, emit the root opcode
492 if (const ComplexPattern *CP =
493 Pattern.getSrcPattern()->getComplexPatternInfo(CGP)) {
495 const std::vector<Record*> &OpNodes = CP->getRootNodes();
496 if (OpNodes.empty()) {
497 // FIXME: Empty OpNodes runs on everything, is this even valid?
498 if (Variant != 0) return true;
500 if (Variant >= OpNodes.size()) return true;
502 AddMatcher(new CheckOpcodeMatcher(CGP.getSDNodeInfo(OpNodes[Variant])));
505 if (Variant != 0) return true;
508 // If the pattern has a predicate on it (e.g. only enabled when a subtarget
509 // feature is around, do the check).
510 // FIXME: This should get emitted after the match code below to encourage
511 // sharing. This can't happen until we get an X86ISD::AddrMode node made by
512 // dag combine, eliminating the horrible side-effect-full stuff from
513 // X86's MatchAddress.
514 if (!Pattern.getPredicateCheck().empty())
515 AddMatcher(new CheckPatternPredicateMatcher(Pattern.getPredicateCheck()));
517 // Emit the matcher for the pattern structure and types.
518 EmitMatchCode(Pattern.getSrcPattern(), PatWithNoTypes);
523 //===----------------------------------------------------------------------===//
524 // Node Result Generation
525 //===----------------------------------------------------------------------===//
527 void MatcherGen::EmitResultOfNamedOperand(const TreePatternNode *N,
528 SmallVectorImpl<unsigned> &ResultOps){
529 assert(!N->getName().empty() && "Operand not named!");
531 unsigned SlotNo = getNamedArgumentSlot(N->getName());
533 // A reference to a complex pattern gets all of the results of the complex
535 if (const ComplexPattern *CP = N->getComplexPatternInfo(CGP)) {
536 // The first slot entry is the node itself, the subsequent entries are the
538 for (unsigned i = 0, e = CP->getNumOperands(); i != e; ++i)
539 ResultOps.push_back(SlotNo+i+1);
543 // If this is an 'imm' or 'fpimm' node, make sure to convert it to the target
544 // version of the immediate so that it doesn't get selected due to some other
547 StringRef OperatorName = N->getOperator()->getName();
548 if (OperatorName == "imm" || OperatorName == "fpimm") {
549 AddMatcher(new EmitConvertToTargetMatcher(SlotNo));
550 ResultOps.push_back(NextRecordedOperandNo++);
555 ResultOps.push_back(SlotNo);
558 void MatcherGen::EmitResultLeafAsOperand(const TreePatternNode *N,
559 SmallVectorImpl<unsigned> &ResultOps) {
560 assert(N->isLeaf() && "Must be a leaf");
562 if (IntInit *II = dynamic_cast<IntInit*>(N->getLeafValue())) {
563 AddMatcher(new EmitIntegerMatcher(II->getValue(),N->getTypeNum(0)));
564 ResultOps.push_back(NextRecordedOperandNo++);
568 // If this is an explicit register reference, handle it.
569 if (DefInit *DI = dynamic_cast<DefInit*>(N->getLeafValue())) {
570 if (DI->getDef()->isSubClassOf("Register")) {
571 AddMatcher(new EmitRegisterMatcher(DI->getDef(),
573 ResultOps.push_back(NextRecordedOperandNo++);
577 if (DI->getDef()->getName() == "zero_reg") {
578 AddMatcher(new EmitRegisterMatcher(0, N->getTypeNum(0)));
579 ResultOps.push_back(NextRecordedOperandNo++);
583 // Handle a reference to a register class. This is used
584 // in COPY_TO_SUBREG instructions.
585 if (DI->getDef()->isSubClassOf("RegisterClass")) {
586 std::string Value = getQualifiedName(DI->getDef()) + "RegClassID";
587 AddMatcher(new EmitStringIntegerMatcher(Value, MVT::i32));
588 ResultOps.push_back(NextRecordedOperandNo++);
593 errs() << "unhandled leaf node: \n";
597 /// GetInstPatternNode - Get the pattern for an instruction.
599 const TreePatternNode *MatcherGen::
600 GetInstPatternNode(const DAGInstruction &Inst, const TreePatternNode *N) {
601 const TreePattern *InstPat = Inst.getPattern();
603 // FIXME2?: Assume actual pattern comes before "implicit".
604 TreePatternNode *InstPatNode;
606 InstPatNode = InstPat->getTree(0);
607 else if (/*isRoot*/ N == Pattern.getDstPattern())
608 InstPatNode = Pattern.getSrcPattern();
612 if (InstPatNode && !InstPatNode->isLeaf() &&
613 InstPatNode->getOperator()->getName() == "set")
614 InstPatNode = InstPatNode->getChild(InstPatNode->getNumChildren()-1);
620 EmitResultInstructionAsOperand(const TreePatternNode *N,
621 SmallVectorImpl<unsigned> &OutputOps) {
622 Record *Op = N->getOperator();
623 const CodeGenTarget &CGT = CGP.getTargetInfo();
624 CodeGenInstruction &II = CGT.getInstruction(Op->getName());
625 const DAGInstruction &Inst = CGP.getInstruction(Op);
627 // If we can, get the pattern for the instruction we're generating. We derive
628 // a variety of information from this pattern, such as whether it has a chain.
630 // FIXME2: This is extremely dubious for several reasons, not the least of
631 // which it gives special status to instructions with patterns that Pat<>
632 // nodes can't duplicate.
633 const TreePatternNode *InstPatNode = GetInstPatternNode(Inst, N);
635 // NodeHasChain - Whether the instruction node we're creating takes chains.
636 bool NodeHasChain = InstPatNode &&
637 InstPatNode->TreeHasProperty(SDNPHasChain, CGP);
639 bool isRoot = N == Pattern.getDstPattern();
641 // TreeHasOutFlag - True if this tree has a flag.
642 bool TreeHasInFlag = false, TreeHasOutFlag = false;
644 const TreePatternNode *SrcPat = Pattern.getSrcPattern();
645 TreeHasInFlag = SrcPat->TreeHasProperty(SDNPOptInFlag, CGP) ||
646 SrcPat->TreeHasProperty(SDNPInFlag, CGP);
648 // FIXME2: this is checking the entire pattern, not just the node in
649 // question, doing this just for the root seems like a total hack.
650 TreeHasOutFlag = SrcPat->TreeHasProperty(SDNPOutFlag, CGP);
653 // NumResults - This is the number of results produced by the instruction in
655 unsigned NumResults = Inst.getNumResults();
657 // Loop over all of the operands of the instruction pattern, emitting code
658 // to fill them all in. The node 'N' usually has number children equal to
659 // the number of input operands of the instruction. However, in cases
660 // where there are predicate operands for an instruction, we need to fill
661 // in the 'execute always' values. Match up the node operands to the
662 // instruction operands to do this.
663 SmallVector<unsigned, 8> InstOps;
664 for (unsigned ChildNo = 0, InstOpNo = NumResults, e = II.OperandList.size();
665 InstOpNo != e; ++InstOpNo) {
667 // Determine what to emit for this operand.
668 Record *OperandNode = II.OperandList[InstOpNo].Rec;
669 if ((OperandNode->isSubClassOf("PredicateOperand") ||
670 OperandNode->isSubClassOf("OptionalDefOperand")) &&
671 !CGP.getDefaultOperand(OperandNode).DefaultOps.empty()) {
672 // This is a predicate or optional def operand; emit the
673 // 'default ops' operands.
674 const DAGDefaultOperand &DefaultOp =
675 CGP.getDefaultOperand(II.OperandList[InstOpNo].Rec);
676 for (unsigned i = 0, e = DefaultOp.DefaultOps.size(); i != e; ++i)
677 EmitResultOperand(DefaultOp.DefaultOps[i], InstOps);
681 // Otherwise this is a normal operand or a predicate operand without
682 // 'execute always'; emit it.
683 EmitResultOperand(N->getChild(ChildNo), InstOps);
687 // Nodes that match patterns with (potentially multiple) chain inputs have to
688 // merge them together into a token factor.
689 if (NodeHasChain && !EmittedMergeInputChains) {
690 // FIXME2: Move this out of emitresult to a top level place.
691 assert(!MatchedChainNodes.empty() &&
692 "How can this node have chain if no inputs do?");
693 // Otherwise, we have to emit an operation to merge the input chains and
694 // set this as the current input chain.
695 AddMatcher(new EmitMergeInputChainsMatcher
696 (MatchedChainNodes.data(), MatchedChainNodes.size()));
697 EmittedMergeInputChains = true;
700 // If this node has an input flag or explicitly specified input physregs, we
701 // need to add chained and flagged copyfromreg nodes and materialize the flag
703 if (isRoot && !PhysRegInputs.empty()) {
704 // Emit all of the CopyToReg nodes for the input physical registers. These
705 // occur in patterns like (mul:i8 AL:i8, GR8:i8:$src).
706 for (unsigned i = 0, e = PhysRegInputs.size(); i != e; ++i)
707 AddMatcher(new EmitCopyToRegMatcher(PhysRegInputs[i].second,
708 PhysRegInputs[i].first));
709 // Even if the node has no other flag inputs, the resultant node must be
710 // flagged to the CopyFromReg nodes we just generated.
711 TreeHasInFlag = true;
714 // Result order: node results, chain, flags
716 // Determine the result types.
717 SmallVector<MVT::SimpleValueType, 4> ResultVTs;
718 if (NumResults != 0 && N->getTypeNum(0) != MVT::isVoid) {
719 // FIXME2: If the node has multiple results, we should add them. For now,
720 // preserve existing behavior?!
721 ResultVTs.push_back(N->getTypeNum(0));
725 // If this is the root instruction of a pattern that has physical registers in
726 // its result pattern, add output VTs for them. For example, X86 has:
727 // (set AL, (mul ...))
728 // This also handles implicit results like:
730 if (isRoot && Pattern.getDstRegs().size() != 0) {
731 for (unsigned i = 0; i != Pattern.getDstRegs().size(); ++i)
732 if (Pattern.getDstRegs()[i]->isSubClassOf("Register"))
733 ResultVTs.push_back(getRegisterValueType(Pattern.getDstRegs()[i], CGT));
736 // FIXME2: Instead of using the isVariadic flag on the instruction, we should
737 // have an SDNP that indicates variadicism. The TargetInstrInfo isVariadic
738 // property should be inferred from this when an instruction has a pattern.
739 int NumFixedArityOperands = -1;
740 if (isRoot && II.isVariadic)
741 NumFixedArityOperands = Pattern.getSrcPattern()->getNumChildren();
743 // If this is the root node and any of the nodes matched nodes in the input
744 // pattern have MemRefs in them, have the interpreter collect them and plop
745 // them onto this node.
747 // FIXME3: This is actively incorrect for result patterns where the root of
748 // the pattern is not the memory reference and is also incorrect when the
749 // result pattern has multiple memory-referencing instructions. For example,
750 // in the X86 backend, this pattern causes the memrefs to get attached to the
751 // CVTSS2SDrr instead of the MOVSSrm:
753 // def : Pat<(extloadf32 addr:$src),
754 // (CVTSS2SDrr (MOVSSrm addr:$src))>;
756 bool NodeHasMemRefs =
757 isRoot && Pattern.getSrcPattern()->TreeHasProperty(SDNPMemOperand, CGP);
759 AddMatcher(new EmitNodeMatcher(II.Namespace+"::"+II.TheDef->getName(),
760 ResultVTs.data(), ResultVTs.size(),
761 InstOps.data(), InstOps.size(),
762 NodeHasChain, TreeHasInFlag, TreeHasOutFlag,
763 NodeHasMemRefs, NumFixedArityOperands,
764 NextRecordedOperandNo));
766 // The non-chain and non-flag results of the newly emitted node get recorded.
767 for (unsigned i = 0, e = ResultVTs.size(); i != e; ++i) {
768 if (ResultVTs[i] == MVT::Other || ResultVTs[i] == MVT::Flag) break;
769 OutputOps.push_back(NextRecordedOperandNo++);
774 EmitResultSDNodeXFormAsOperand(const TreePatternNode *N,
775 SmallVectorImpl<unsigned> &ResultOps) {
776 assert(N->getOperator()->isSubClassOf("SDNodeXForm") && "Not SDNodeXForm?");
779 SmallVector<unsigned, 8> InputOps;
781 // FIXME2: Could easily generalize this to support multiple inputs and outputs
782 // to the SDNodeXForm. For now we just support one input and one output like
783 // the old instruction selector.
784 assert(N->getNumChildren() == 1);
785 EmitResultOperand(N->getChild(0), InputOps);
787 // The input currently must have produced exactly one result.
788 assert(InputOps.size() == 1 && "Unexpected input to SDNodeXForm");
790 AddMatcher(new EmitNodeXFormMatcher(InputOps[0], N->getOperator()));
791 ResultOps.push_back(NextRecordedOperandNo++);
794 void MatcherGen::EmitResultOperand(const TreePatternNode *N,
795 SmallVectorImpl<unsigned> &ResultOps) {
796 // This is something selected from the pattern we matched.
797 if (!N->getName().empty())
798 return EmitResultOfNamedOperand(N, ResultOps);
801 return EmitResultLeafAsOperand(N, ResultOps);
803 Record *OpRec = N->getOperator();
804 if (OpRec->isSubClassOf("Instruction"))
805 return EmitResultInstructionAsOperand(N, ResultOps);
806 if (OpRec->isSubClassOf("SDNodeXForm"))
807 return EmitResultSDNodeXFormAsOperand(N, ResultOps);
808 errs() << "Unknown result node to emit code for: " << *N << '\n';
809 throw std::string("Unknown node in result pattern!");
812 void MatcherGen::EmitResultCode() {
813 // Codegen the root of the result pattern, capturing the resulting values.
814 SmallVector<unsigned, 8> Ops;
815 EmitResultOperand(Pattern.getDstPattern(), Ops);
817 // At this point, we have however many values the result pattern produces.
818 // However, the input pattern might not need all of these. If there are
819 // excess values at the end (such as condition codes etc) just lop them off.
820 // This doesn't need to worry about flags or chains, just explicit results.
822 // FIXME2: This doesn't work because there is currently no way to get an
823 // accurate count of the # results the source pattern sets. This is because
824 // of the "parallel" construct in X86 land, which looks like this:
826 //def : Pat<(parallel (X86and_flag GR8:$src1, GR8:$src2),
827 // (implicit EFLAGS)),
828 // (AND8rr GR8:$src1, GR8:$src2)>;
830 // This idiom means to match the two-result node X86and_flag (which is
831 // declared as returning a single result, because we can't match multi-result
832 // nodes yet). In this case, we would have to know that the input has two
833 // results. However, mul8r is modelled exactly the same way, but without
834 // implicit defs included. The fix is to support multiple results directly
835 // and eliminate 'parallel'.
837 // FIXME2: When this is fixed, we should revert the terrible hack in the
838 // OPC_EmitNode code in the interpreter.
840 const TreePatternNode *Src = Pattern.getSrcPattern();
841 unsigned NumSrcResults = Src->getTypeNum(0) != MVT::isVoid ? 1 : 0;
842 NumSrcResults += Pattern.getDstRegs().size();
843 assert(Ops.size() >= NumSrcResults && "Didn't provide enough results");
844 Ops.resize(NumSrcResults);
847 // If the matched pattern covers nodes which define a flag result, emit a node
848 // that tells the matcher about them so that it can update their results.
849 if (!MatchedFlagResultNodes.empty())
850 AddMatcher(new MarkFlagResultsMatcher(MatchedFlagResultNodes.data(),
851 MatchedFlagResultNodes.size()));
854 // We know that the resulting pattern has exactly one result/
855 // FIXME2: why? what about something like (set a,b,c, (complexpat))
856 // FIXME2: Implicit results should be pushed here I guess?
857 AddMatcher(new CompleteMatchMatcher(Ops.data(), Ops.size(), Pattern));
861 /// ConvertPatternToMatcher - Create the matcher for the specified pattern with
862 /// the specified variant. If the variant number is invalid, this returns null.
863 Matcher *llvm::ConvertPatternToMatcher(const PatternToMatch &Pattern,
865 const CodeGenDAGPatterns &CGP) {
866 MatcherGen Gen(Pattern, CGP);
868 // Generate the code for the matcher.
869 if (Gen.EmitMatcherCode(Variant))
872 // FIXME2: Kill extra MoveParent commands at the end of the matcher sequence.
873 // FIXME2: Split result code out to another table, and make the matcher end
874 // with an "Emit <index>" command. This allows result generation stuff to be
875 // shared and factored?
877 // If the match succeeds, then we generate Pattern.
878 Gen.EmitResultCode();
880 // Unconditional match.
881 return Gen.GetMatcher();