1 //===- CodeGenTarget.h - Target Class Wrapper -------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines wrappers for the Target class and related global
11 // functionality. This makes it easier to access the data and provides a single
12 // place that needs to check it for validity. All of these classes throw
13 // exceptions on error conditions.
15 //===----------------------------------------------------------------------===//
17 #ifndef CODEGEN_TARGET_H
18 #define CODEGEN_TARGET_H
20 #include "CodeGenRegisters.h"
21 #include "CodeGenInstruction.h"
29 struct CodeGenRegister;
32 /// getValueType - Return the MVT::ValueType that the specified TableGen record
34 MVT::ValueType getValueType(Record *Rec, const CodeGenTarget *CGT = 0);
36 std::ostream &operator<<(std::ostream &OS, MVT::ValueType T);
37 std::string getName(MVT::ValueType T);
38 std::string getEnumName(MVT::ValueType T);
41 /// CodeGenTarget - This class corresponds to the Target class in the .td files.
46 mutable std::map<std::string, CodeGenInstruction> Instructions;
47 mutable std::vector<CodeGenRegister> Registers;
48 mutable std::vector<CodeGenRegisterClass> RegisterClasses;
49 mutable std::vector<MVT::ValueType> LegalValueTypes;
50 void ReadRegisters() const;
51 void ReadRegisterClasses() const;
52 void ReadInstructions() const;
53 void ReadLegalValueTypes() const;
57 Record *getTargetRecord() const { return TargetRec; }
58 const std::string &getName() const;
60 /// getInstructionSet - Return the InstructionSet object.
62 Record *getInstructionSet() const;
64 /// getAsmWriter - Return the AssemblyWriter definition for this target.
66 Record *getAsmWriter() const;
68 const std::vector<CodeGenRegister> &getRegisters() const {
69 if (Registers.empty()) ReadRegisters();
73 const std::vector<CodeGenRegisterClass> &getRegisterClasses() const {
74 if (RegisterClasses.empty()) ReadRegisterClasses();
75 return RegisterClasses;
78 const CodeGenRegisterClass &getRegisterClass(Record *R) const {
79 const std::vector<CodeGenRegisterClass> &RC = getRegisterClasses();
80 for (unsigned i = 0, e = RC.size(); i != e; ++i)
81 if (RC[i].TheDef == R)
83 assert(0 && "Didn't find the register class");
87 /// getRegisterClassForRegister - Find the register class that contains the
88 /// specified physical register. If there register exists in multiple
89 /// register classes or is not in a register class, return null.
90 const CodeGenRegisterClass *getRegisterClassForRegister(Record *R) const {
91 const std::vector<CodeGenRegisterClass> &RCs = getRegisterClasses();
92 const CodeGenRegisterClass *FoundRC = 0;
93 for (unsigned i = 0, e = RCs.size(); i != e; ++i) {
94 const CodeGenRegisterClass &RC = RegisterClasses[i];
95 for (unsigned ei = 0, ee = RC.Elements.size(); ei != ee; ++ei) {
96 if (R == RC.Elements[ei]) {
97 if (FoundRC) return 0; // In multiple RC's
106 /// getRegisterVTs - Find the union of all possible ValueTypes for the
107 /// specified physical register.
108 std::vector<unsigned char> getRegisterVTs(Record *R) const;
110 const std::vector<MVT::ValueType> &getLegalValueTypes() const {
111 if (LegalValueTypes.empty()) ReadLegalValueTypes();
112 return LegalValueTypes;
115 /// isLegalValueType - Return true if the specified value type is natively
116 /// supported by the target (i.e. there are registers that directly hold it).
117 bool isLegalValueType(MVT::ValueType VT) const {
118 const std::vector<MVT::ValueType> &LegalVTs = getLegalValueTypes();
119 for (unsigned i = 0, e = LegalVTs.size(); i != e; ++i)
120 if (LegalVTs[i] == VT) return true;
124 /// getInstructions - Return all of the instructions defined for this target.
126 const std::map<std::string, CodeGenInstruction> &getInstructions() const {
127 if (Instructions.empty()) ReadInstructions();
131 CodeGenInstruction &getInstruction(const std::string &Name) const {
132 const std::map<std::string, CodeGenInstruction> &Insts = getInstructions();
133 assert(Insts.count(Name) && "Not an instruction!");
134 return const_cast<CodeGenInstruction&>(Insts.find(Name)->second);
137 typedef std::map<std::string,
138 CodeGenInstruction>::const_iterator inst_iterator;
139 inst_iterator inst_begin() const { return getInstructions().begin(); }
140 inst_iterator inst_end() const { return Instructions.end(); }
142 /// getInstructionsByEnumValue - Return all of the instructions defined by the
143 /// target, ordered by their enum value.
144 void getInstructionsByEnumValue(std::vector<const CodeGenInstruction*>
145 &NumberedInstructions);
148 /// isLittleEndianEncoding - are instruction bit patterns defined as [0..n]?
150 bool isLittleEndianEncoding() const;
153 /// ComplexPattern - ComplexPattern info, corresponding to the ComplexPattern
154 /// tablegen class in TargetSelectionDAG.td
155 class ComplexPattern {
157 unsigned NumOperands;
158 std::string SelectFunc;
159 std::vector<Record*> RootNodes;
161 ComplexPattern() : NumOperands(0) {};
162 ComplexPattern(Record *R);
164 MVT::ValueType getValueType() const { return Ty; }
165 unsigned getNumOperands() const { return NumOperands; }
166 const std::string &getSelectFunc() const { return SelectFunc; }
167 const std::vector<Record*> &getRootNodes() const {
172 } // End llvm namespace