1 //===- CodeGenRegisters.h - Register and RegisterClass Info -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines structures to encapsulate information gleaned from the
11 // target register and register class definitions.
13 //===----------------------------------------------------------------------===//
15 #ifndef CODEGEN_REGISTERS_H
16 #define CODEGEN_REGISTERS_H
19 #include "SetTheory.h"
20 #include "llvm/CodeGen/ValueTypes.h"
21 #include "llvm/ADT/ArrayRef.h"
22 #include "llvm/ADT/DenseMap.h"
23 #include "llvm/ADT/SetVector.h"
33 /// CodeGenRegister - Represents a register definition.
34 struct CodeGenRegister {
39 // Map SubRegIndex -> Register.
40 typedef std::map<Record*, CodeGenRegister*, LessRecord> SubRegMap;
42 CodeGenRegister(Record *R, unsigned Enum);
44 const std::string &getName() const;
46 // Get a map of sub-registers computed lazily.
47 // This includes unique entries for all sub-sub-registers.
48 const SubRegMap &getSubRegs(CodeGenRegBank&);
50 const SubRegMap &getSubRegs() const {
51 assert(SubRegsComplete && "Must precompute sub-registers");
55 // Add sub-registers to OSet following a pre-order defined by the .td file.
56 void addSubRegsPreOrder(SetVector<CodeGenRegister*> &OSet) const;
58 // List of super-registers in topological order, small to large.
59 typedef std::vector<CodeGenRegister*> SuperRegList;
61 // Get the list of super-registers.
62 // This is only valid after computeDerivedInfo has visited all registers.
63 const SuperRegList &getSuperRegs() const {
64 assert(SubRegsComplete && "Must precompute sub-registers");
68 // Order CodeGenRegister pointers by EnumValue.
70 bool operator()(const CodeGenRegister *A,
71 const CodeGenRegister *B) const {
72 return A->EnumValue < B->EnumValue;
76 // Canonically ordered set.
77 typedef std::set<const CodeGenRegister*, Less> Set;
82 SuperRegList SuperRegs;
86 class CodeGenRegisterClass {
87 CodeGenRegister::Set Members;
88 const std::vector<Record*> *Elements;
91 std::string Namespace;
92 std::vector<MVT::SimpleValueType> VTs;
94 unsigned SpillAlignment;
97 // Map SubRegIndex -> RegisterClass
98 DenseMap<Record*,Record*> SubRegClasses;
99 std::string MethodProtos, MethodBodies;
101 const std::string &getName() const;
102 const std::vector<MVT::SimpleValueType> &getValueTypes() const {return VTs;}
103 unsigned getNumValueTypes() const { return VTs.size(); }
105 MVT::SimpleValueType getValueTypeNum(unsigned VTNum) const {
106 if (VTNum < VTs.size())
108 assert(0 && "VTNum greater than number of ValueTypes in RegClass!");
112 // Return true if this this class contains the register.
113 bool contains(const CodeGenRegister*) const;
115 // Returns true if RC is a subclass.
116 // RC is a sub-class of this class if it is a valid replacement for any
117 // instruction operand where a register of this classis required. It must
118 // satisfy these conditions:
120 // 1. All RC registers are also in this.
121 // 2. The RC spill size must not be smaller than our spill size.
122 // 3. RC spill alignment must be compatible with ours.
124 bool hasSubClass(const CodeGenRegisterClass *RC) const;
126 // Returns an ordered list of class members.
127 // The order of registers is the same as in the .td file.
128 ArrayRef<Record*> getOrder() const {
132 CodeGenRegisterClass(CodeGenRegBank&, Record *R);
135 // CodeGenRegBank - Represent a target's registers and the relations between
137 class CodeGenRegBank {
138 RecordKeeper &Records;
141 std::vector<Record*> SubRegIndices;
142 unsigned NumNamedIndices;
143 std::vector<CodeGenRegister> Registers;
144 DenseMap<Record*, CodeGenRegister*> Def2Reg;
146 std::vector<CodeGenRegisterClass> RegClasses;
147 DenseMap<Record*, CodeGenRegisterClass*> Def2RC;
149 // Composite SubRegIndex instances.
150 // Map (SubRegIndex, SubRegIndex) -> SubRegIndex.
151 typedef DenseMap<std::pair<Record*, Record*>, Record*> CompositeMap;
152 CompositeMap Composite;
154 // Populate the Composite map from sub-register relationships.
155 void computeComposites();
158 CodeGenRegBank(RecordKeeper&);
160 SetTheory &getSets() { return Sets; }
162 // Sub-register indices. The first NumNamedIndices are defined by the user
163 // in the .td files. The rest are synthesized such that all sub-registers
164 // have a unique name.
165 const std::vector<Record*> &getSubRegIndices() { return SubRegIndices; }
166 unsigned getNumNamedIndices() { return NumNamedIndices; }
168 // Map a SubRegIndex Record to its enum value.
169 unsigned getSubRegIndexNo(Record *idx);
171 // Find or create a sub-register index representing the A+B composition.
172 Record *getCompositeSubRegIndex(Record *A, Record *B, bool create = false);
174 const std::vector<CodeGenRegister> &getRegisters() { return Registers; }
176 // Find a register from its Record def.
177 CodeGenRegister *getReg(Record*);
179 const std::vector<CodeGenRegisterClass> &getRegClasses() {
183 // Find a register class from its def.
184 CodeGenRegisterClass *getRegClass(Record*);
186 /// getRegisterClassForRegister - Find the register class that contains the
187 /// specified physical register. If the register is not in a register
188 /// class, return null. If the register is in multiple classes, and the
189 /// classes have a superset-subset relationship and the same set of types,
190 /// return the superclass. Otherwise return null.
191 const CodeGenRegisterClass* getRegClassForRegister(Record *R);
193 // Computed derived records such as missing sub-register indices.
194 void computeDerivedInfo();
196 // Compute full overlap sets for every register. These sets include the
197 // rarely used aliases that are neither sub nor super-registers.
199 // Map[R1].count(R2) is reflexive and symmetric, but not transitive.
201 // If R1 is a sub-register of R2, Map[R1] is a subset of Map[R2].
202 void computeOverlaps(std::map<const CodeGenRegister*,
203 CodeGenRegister::Set> &Map);