1 //===- CodeGenRegisters.h - Register and RegisterClass Info -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines structures to encapsulate information gleaned from the
11 // target register and register class definitions.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_UTILS_TABLEGEN_CODEGENREGISTERS_H
16 #define LLVM_UTILS_TABLEGEN_CODEGENREGISTERS_H
18 #include "llvm/ADT/ArrayRef.h"
19 #include "llvm/ADT/BitVector.h"
20 #include "llvm/ADT/DenseMap.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/SetVector.h"
23 #include "llvm/ADT/SparseBitVector.h"
24 #include "llvm/CodeGen/MachineValueType.h"
25 #include "llvm/Support/ErrorHandling.h"
26 #include "llvm/TableGen/Record.h"
27 #include "llvm/TableGen/SetTheory.h"
39 /// Used to encode a step in a register lane mask transformation.
40 /// Mask the bits specified in Mask, then rotate them Rol bits to the left
41 /// assuming a wraparound at 32bits.
45 bool operator==(const MaskRolPair Other) const {
46 return Mask == Other.Mask && RotateLeft == Other.RotateLeft;
48 bool operator!=(const MaskRolPair Other) const {
49 return Mask != Other.Mask || RotateLeft != Other.RotateLeft;
53 /// CodeGenSubRegIndex - Represents a sub-register index.
54 class CodeGenSubRegIndex {
57 std::string Namespace;
62 const unsigned EnumValue;
63 mutable unsigned LaneMask;
64 mutable SmallVector<MaskRolPair,1> CompositionLaneMaskTransform;
66 // Are all super-registers containing this SubRegIndex covered by their
68 bool AllSuperRegsCovered;
70 CodeGenSubRegIndex(Record *R, unsigned Enum);
71 CodeGenSubRegIndex(StringRef N, StringRef Nspace, unsigned Enum);
73 const std::string &getName() const { return Name; }
74 const std::string &getNamespace() const { return Namespace; }
75 std::string getQualifiedName() const;
77 // Map of composite subreg indices.
78 typedef DenseMap<CodeGenSubRegIndex *, CodeGenSubRegIndex *> CompMap;
80 // Returns the subreg index that results from composing this with Idx.
81 // Returns NULL if this and Idx don't compose.
82 CodeGenSubRegIndex *compose(CodeGenSubRegIndex *Idx) const {
83 CompMap::const_iterator I = Composed.find(Idx);
84 return I == Composed.end() ? nullptr : I->second;
87 // Add a composite subreg index: this+A = B.
88 // Return a conflicting composite, or NULL
89 CodeGenSubRegIndex *addComposite(CodeGenSubRegIndex *A,
90 CodeGenSubRegIndex *B) {
92 std::pair<CompMap::iterator, bool> Ins =
93 Composed.insert(std::make_pair(A, B));
94 // Synthetic subreg indices that aren't contiguous (for instance ARM
95 // register tuples) don't have a bit range, so it's OK to let
96 // B->Offset == -1. For the other cases, accumulate the offset and set
97 // the size here. Only do so if there is no offset yet though.
98 if ((Offset != (uint16_t)-1 && A->Offset != (uint16_t)-1) &&
99 (B->Offset == (uint16_t)-1)) {
100 B->Offset = Offset + A->Offset;
103 return (Ins.second || Ins.first->second == B) ? nullptr
107 // Update the composite maps of components specified in 'ComposedOf'.
108 void updateComponents(CodeGenRegBank&);
110 // Return the map of composites.
111 const CompMap &getComposites() const { return Composed; }
113 // Compute LaneMask from Composed. Return LaneMask.
114 unsigned computeLaneMask() const;
120 inline bool operator<(const CodeGenSubRegIndex &A,
121 const CodeGenSubRegIndex &B) {
122 return A.EnumValue < B.EnumValue;
125 /// CodeGenRegister - Represents a register definition.
126 struct CodeGenRegister {
130 bool CoveredBySubRegs;
132 // Map SubRegIndex -> Register.
133 typedef std::map<CodeGenSubRegIndex *, CodeGenRegister *, deref<llvm::less>>
136 CodeGenRegister(Record *R, unsigned Enum);
138 const std::string &getName() const;
140 // Extract more information from TheDef. This is used to build an object
141 // graph after all CodeGenRegister objects have been created.
142 void buildObjectGraph(CodeGenRegBank&);
144 // Lazily compute a map of all sub-registers.
145 // This includes unique entries for all sub-sub-registers.
146 const SubRegMap &computeSubRegs(CodeGenRegBank&);
148 // Compute extra sub-registers by combining the existing sub-registers.
149 void computeSecondarySubRegs(CodeGenRegBank&);
151 // Add this as a super-register to all sub-registers after the sub-register
152 // graph has been built.
153 void computeSuperRegs(CodeGenRegBank&);
155 const SubRegMap &getSubRegs() const {
156 assert(SubRegsComplete && "Must precompute sub-registers");
160 // Add sub-registers to OSet following a pre-order defined by the .td file.
161 void addSubRegsPreOrder(SetVector<const CodeGenRegister*> &OSet,
162 CodeGenRegBank&) const;
164 // Return the sub-register index naming Reg as a sub-register of this
165 // register. Returns NULL if Reg is not a sub-register.
166 CodeGenSubRegIndex *getSubRegIndex(const CodeGenRegister *Reg) const {
167 return SubReg2Idx.lookup(Reg);
170 typedef std::vector<const CodeGenRegister*> SuperRegList;
172 // Get the list of super-registers in topological order, small to large.
173 // This is valid after computeSubRegs visits all registers during RegBank
175 const SuperRegList &getSuperRegs() const {
176 assert(SubRegsComplete && "Must precompute sub-registers");
180 // Get the list of ad hoc aliases. The graph is symmetric, so the list
181 // contains all registers in 'Aliases', and all registers that mention this
182 // register in 'Aliases'.
183 ArrayRef<CodeGenRegister*> getExplicitAliases() const {
184 return ExplicitAliases;
187 // Get the topological signature of this register. This is a small integer
188 // less than RegBank.getNumTopoSigs(). Registers with the same TopoSig have
189 // identical sub-register structure. That is, they support the same set of
190 // sub-register indices mapping to the same kind of sub-registers
192 unsigned getTopoSig() const {
193 assert(SuperRegsComplete && "TopoSigs haven't been computed yet.");
197 // List of register units in ascending order.
198 typedef SparseBitVector<> RegUnitList;
199 typedef SmallVector<unsigned, 16> RegUnitLaneMaskList;
201 // How many entries in RegUnitList are native?
202 RegUnitList NativeRegUnits;
204 // Get the list of register units.
205 // This is only valid after computeSubRegs() completes.
206 const RegUnitList &getRegUnits() const { return RegUnits; }
208 ArrayRef<unsigned> getRegUnitLaneMasks() const {
209 return makeArrayRef(RegUnitLaneMasks).slice(0, NativeRegUnits.count());
212 // Get the native register units. This is a prefix of getRegUnits().
213 RegUnitList getNativeRegUnits() const {
214 return NativeRegUnits;
217 void setRegUnitLaneMasks(const RegUnitLaneMaskList &LaneMasks) {
218 RegUnitLaneMasks = LaneMasks;
221 // Inherit register units from subregisters.
222 // Return true if the RegUnits changed.
223 bool inheritRegUnits(CodeGenRegBank &RegBank);
225 // Adopt a register unit for pressure tracking.
226 // A unit is adopted iff its unit number is >= NativeRegUnits.count().
227 void adoptRegUnit(unsigned RUID) { RegUnits.set(RUID); }
229 // Get the sum of this register's register unit weights.
230 unsigned getWeight(const CodeGenRegBank &RegBank) const;
232 // Canonically ordered set.
233 typedef std::vector<const CodeGenRegister*> Vec;
236 bool SubRegsComplete;
237 bool SuperRegsComplete;
240 // The sub-registers explicit in the .td file form a tree.
241 SmallVector<CodeGenSubRegIndex*, 8> ExplicitSubRegIndices;
242 SmallVector<CodeGenRegister*, 8> ExplicitSubRegs;
244 // Explicit ad hoc aliases, symmetrized to form an undirected graph.
245 SmallVector<CodeGenRegister*, 8> ExplicitAliases;
247 // Super-registers where this is the first explicit sub-register.
248 SuperRegList LeadingSuperRegs;
251 SuperRegList SuperRegs;
252 DenseMap<const CodeGenRegister*, CodeGenSubRegIndex*> SubReg2Idx;
253 RegUnitList RegUnits;
254 RegUnitLaneMaskList RegUnitLaneMasks;
257 inline bool operator<(const CodeGenRegister &A, const CodeGenRegister &B) {
258 return A.EnumValue < B.EnumValue;
261 inline bool operator==(const CodeGenRegister &A, const CodeGenRegister &B) {
262 return A.EnumValue == B.EnumValue;
265 class CodeGenRegisterClass {
266 CodeGenRegister::Vec Members;
267 // Allocation orders. Order[0] always contains all registers in Members.
268 std::vector<SmallVector<Record*, 16> > Orders;
269 // Bit mask of sub-classes including this, indexed by their EnumValue.
270 BitVector SubClasses;
271 // List of super-classes, topologocally ordered to have the larger classes
272 // first. This is the same as sorting by EnumValue.
273 SmallVector<CodeGenRegisterClass*, 4> SuperClasses;
277 // For a synthesized class, inherit missing properties from the nearest
279 void inheritProperties(CodeGenRegBank&);
281 // Map SubRegIndex -> sub-class. This is the largest sub-class where all
282 // registers have a SubRegIndex sub-register.
283 DenseMap<const CodeGenSubRegIndex *, CodeGenRegisterClass *>
286 // Map SubRegIndex -> set of super-reg classes. This is all register
287 // classes SuperRC such that:
289 // R:SubRegIndex in this RC for all R in SuperRC.
291 DenseMap<const CodeGenSubRegIndex *, SmallPtrSet<CodeGenRegisterClass *, 8>>
294 // Bit vector of TopoSigs for the registers in this class. This will be
295 // very sparse on regular architectures.
300 std::string Namespace;
301 SmallVector<MVT::SimpleValueType, 4> VTs;
303 unsigned SpillAlignment;
306 std::string AltOrderSelect;
307 /// Contains the combination of the lane masks of all subregisters.
310 // Return the Record that defined this class, or NULL if the class was
311 // created by TableGen.
312 Record *getDef() const { return TheDef; }
314 const std::string &getName() const { return Name; }
315 std::string getQualifiedName() const;
316 ArrayRef<MVT::SimpleValueType> getValueTypes() const {return VTs;}
317 unsigned getNumValueTypes() const { return VTs.size(); }
319 MVT::SimpleValueType getValueTypeNum(unsigned VTNum) const {
320 if (VTNum < VTs.size())
322 llvm_unreachable("VTNum greater than number of ValueTypes in RegClass!");
325 // Return true if this this class contains the register.
326 bool contains(const CodeGenRegister*) const;
328 // Returns true if RC is a subclass.
329 // RC is a sub-class of this class if it is a valid replacement for any
330 // instruction operand where a register of this classis required. It must
331 // satisfy these conditions:
333 // 1. All RC registers are also in this.
334 // 2. The RC spill size must not be smaller than our spill size.
335 // 3. RC spill alignment must be compatible with ours.
337 bool hasSubClass(const CodeGenRegisterClass *RC) const {
338 return SubClasses.test(RC->EnumValue);
341 // getSubClassWithSubReg - Returns the largest sub-class where all
342 // registers have a SubIdx sub-register.
343 CodeGenRegisterClass *
344 getSubClassWithSubReg(const CodeGenSubRegIndex *SubIdx) const {
345 return SubClassWithSubReg.lookup(SubIdx);
348 void setSubClassWithSubReg(const CodeGenSubRegIndex *SubIdx,
349 CodeGenRegisterClass *SubRC) {
350 SubClassWithSubReg[SubIdx] = SubRC;
353 // getSuperRegClasses - Returns a bit vector of all register classes
354 // containing only SubIdx super-registers of this class.
355 void getSuperRegClasses(const CodeGenSubRegIndex *SubIdx,
356 BitVector &Out) const;
358 // addSuperRegClass - Add a class containing only SudIdx super-registers.
359 void addSuperRegClass(CodeGenSubRegIndex *SubIdx,
360 CodeGenRegisterClass *SuperRC) {
361 SuperRegClasses[SubIdx].insert(SuperRC);
364 // getSubClasses - Returns a constant BitVector of subclasses indexed by
366 // The SubClasses vector includes an entry for this class.
367 const BitVector &getSubClasses() const { return SubClasses; }
369 // getSuperClasses - Returns a list of super classes ordered by EnumValue.
370 // The array does not include an entry for this class.
371 ArrayRef<CodeGenRegisterClass*> getSuperClasses() const {
375 // Returns an ordered list of class members.
376 // The order of registers is the same as in the .td file.
377 // No = 0 is the default allocation order, No = 1 is the first alternative.
378 ArrayRef<Record*> getOrder(unsigned No = 0) const {
382 // Return the total number of allocation orders available.
383 unsigned getNumOrders() const { return Orders.size(); }
385 // Get the set of registers. This set contains the same registers as
387 const CodeGenRegister::Vec &getMembers() const { return Members; }
389 // Get a bit vector of TopoSigs present in this register class.
390 const BitVector &getTopoSigs() const { return TopoSigs; }
392 // Populate a unique sorted list of units from a register set.
393 void buildRegUnitSet(std::vector<unsigned> &RegUnits) const;
395 CodeGenRegisterClass(CodeGenRegBank&, Record *R);
397 // A key representing the parts of a register class used for forming
398 // sub-classes. Note the ordering provided by this key is not the same as
399 // the topological order used for the EnumValues.
401 const CodeGenRegister::Vec *Members;
403 unsigned SpillAlignment;
405 Key(const CodeGenRegister::Vec *M, unsigned S = 0, unsigned A = 0)
406 : Members(M), SpillSize(S), SpillAlignment(A) {}
408 Key(const CodeGenRegisterClass &RC)
409 : Members(&RC.getMembers()),
410 SpillSize(RC.SpillSize),
411 SpillAlignment(RC.SpillAlignment) {}
413 // Lexicographical order of (Members, SpillSize, SpillAlignment).
414 bool operator<(const Key&) const;
417 // Create a non-user defined register class.
418 CodeGenRegisterClass(CodeGenRegBank&, StringRef Name, Key Props);
420 // Called by CodeGenRegBank::CodeGenRegBank().
421 static void computeSubClasses(CodeGenRegBank&);
424 // Register units are used to model interference and register pressure.
425 // Every register is assigned one or more register units such that two
426 // registers overlap if and only if they have a register unit in common.
428 // Normally, one register unit is created per leaf register. Non-leaf
429 // registers inherit the units of their sub-registers.
431 // Weight assigned to this RegUnit for estimating register pressure.
432 // This is useful when equalizing weights in register classes with mixed
433 // register topologies.
436 // Each native RegUnit corresponds to one or two root registers. The full
437 // set of registers containing this unit can be computed as the union of
438 // these two registers and their super-registers.
439 const CodeGenRegister *Roots[2];
441 // Index into RegClassUnitSets where we can find the list of UnitSets that
442 // contain this unit.
443 unsigned RegClassUnitSetsIdx;
445 RegUnit() : Weight(0), RegClassUnitSetsIdx(0) {
446 Roots[0] = Roots[1] = nullptr;
449 ArrayRef<const CodeGenRegister*> getRoots() const {
450 assert(!(Roots[1] && !Roots[0]) && "Invalid roots array");
451 return makeArrayRef(Roots, !!Roots[0] + !!Roots[1]);
455 // Each RegUnitSet is a sorted vector with a name.
457 typedef std::vector<unsigned>::const_iterator iterator;
460 std::vector<unsigned> Units;
461 unsigned Weight; // Cache the sum of all unit weights.
462 unsigned Order; // Cache the sort key.
464 RegUnitSet() : Weight(0), Order(0) {}
467 // Base vector for identifying TopoSigs. The contents uniquely identify a
468 // TopoSig, only computeSuperRegs needs to know how.
469 typedef SmallVector<unsigned, 16> TopoSigId;
471 // CodeGenRegBank - Represent a target's registers and the relations between
473 class CodeGenRegBank {
476 std::deque<CodeGenSubRegIndex> SubRegIndices;
477 DenseMap<Record*, CodeGenSubRegIndex*> Def2SubRegIdx;
479 CodeGenSubRegIndex *createSubRegIndex(StringRef Name, StringRef NameSpace);
481 typedef std::map<SmallVector<CodeGenSubRegIndex*, 8>,
482 CodeGenSubRegIndex*> ConcatIdxMap;
483 ConcatIdxMap ConcatIdx;
486 std::deque<CodeGenRegister> Registers;
487 StringMap<CodeGenRegister*> RegistersByName;
488 DenseMap<Record*, CodeGenRegister*> Def2Reg;
489 unsigned NumNativeRegUnits;
491 std::map<TopoSigId, unsigned> TopoSigs;
493 // Includes native (0..NumNativeRegUnits-1) and adopted register units.
494 SmallVector<RegUnit, 8> RegUnits;
497 std::list<CodeGenRegisterClass> RegClasses;
498 DenseMap<Record*, CodeGenRegisterClass*> Def2RC;
499 typedef std::map<CodeGenRegisterClass::Key, CodeGenRegisterClass*> RCKeyMap;
502 // Remember each unique set of register units. Initially, this contains a
503 // unique set for each register class. Simliar sets are coalesced with
504 // pruneUnitSets and new supersets are inferred during computeRegUnitSets.
505 std::vector<RegUnitSet> RegUnitSets;
507 // Map RegisterClass index to the index of the RegUnitSet that contains the
508 // class's units and any inferred RegUnit supersets.
510 // NOTE: This could grow beyond the number of register classes when we map
511 // register units to lists of unit sets. If the list of unit sets does not
512 // already exist for a register class, we create a new entry in this vector.
513 std::vector<std::vector<unsigned> > RegClassUnitSets;
515 // Give each register unit set an order based on sorting criteria.
516 std::vector<unsigned> RegUnitSetOrder;
518 // Add RC to *2RC maps.
519 void addToMaps(CodeGenRegisterClass*);
521 // Create a synthetic sub-class if it is missing.
522 CodeGenRegisterClass *getOrCreateSubClass(const CodeGenRegisterClass *RC,
523 const CodeGenRegister::Vec *Membs,
526 // Infer missing register classes.
527 void computeInferredRegisterClasses();
528 void inferCommonSubClass(CodeGenRegisterClass *RC);
529 void inferSubClassWithSubReg(CodeGenRegisterClass *RC);
530 void inferMatchingSuperRegClass(CodeGenRegisterClass *RC) {
531 inferMatchingSuperRegClass(RC, RegClasses.begin());
534 void inferMatchingSuperRegClass(
535 CodeGenRegisterClass *RC,
536 std::list<CodeGenRegisterClass>::iterator FirstSubRegRC);
538 // Iteratively prune unit sets.
539 void pruneUnitSets();
541 // Compute a weight for each register unit created during getSubRegs.
542 void computeRegUnitWeights();
544 // Create a RegUnitSet for each RegClass and infer superclasses.
545 void computeRegUnitSets();
547 // Populate the Composite map from sub-register relationships.
548 void computeComposites();
550 // Compute a lane mask for each sub-register index.
551 void computeSubRegLaneMasks();
553 /// Computes a lane mask for each register unit enumerated by a physical
555 void computeRegUnitLaneMasks();
558 CodeGenRegBank(RecordKeeper&);
560 SetTheory &getSets() { return Sets; }
562 // Sub-register indices. The first NumNamedIndices are defined by the user
563 // in the .td files. The rest are synthesized such that all sub-registers
564 // have a unique name.
565 const std::deque<CodeGenSubRegIndex> &getSubRegIndices() const {
566 return SubRegIndices;
569 // Find a SubRegIndex form its Record def.
570 CodeGenSubRegIndex *getSubRegIdx(Record*);
572 // Find or create a sub-register index representing the A+B composition.
573 CodeGenSubRegIndex *getCompositeSubRegIndex(CodeGenSubRegIndex *A,
574 CodeGenSubRegIndex *B);
576 // Find or create a sub-register index representing the concatenation of
577 // non-overlapping sibling indices.
579 getConcatSubRegIndex(const SmallVector<CodeGenSubRegIndex *, 8>&);
582 addConcatSubRegIndex(const SmallVector<CodeGenSubRegIndex *, 8> &Parts,
583 CodeGenSubRegIndex *Idx) {
584 ConcatIdx.insert(std::make_pair(Parts, Idx));
587 const std::deque<CodeGenRegister> &getRegisters() { return Registers; }
588 const StringMap<CodeGenRegister*> &getRegistersByName() {
589 return RegistersByName;
592 // Find a register from its Record def.
593 CodeGenRegister *getReg(Record*);
595 // Get a Register's index into the Registers array.
596 unsigned getRegIndex(const CodeGenRegister *Reg) const {
597 return Reg->EnumValue - 1;
600 // Return the number of allocated TopoSigs. The first TopoSig representing
601 // leaf registers is allocated number 0.
602 unsigned getNumTopoSigs() const {
603 return TopoSigs.size();
606 // Find or create a TopoSig for the given TopoSigId.
607 // This function is only for use by CodeGenRegister::computeSuperRegs().
608 // Others should simply use Reg->getTopoSig().
609 unsigned getTopoSig(const TopoSigId &Id) {
610 return TopoSigs.insert(std::make_pair(Id, TopoSigs.size())).first->second;
613 // Create a native register unit that is associated with one or two root
615 unsigned newRegUnit(CodeGenRegister *R0, CodeGenRegister *R1 = nullptr) {
616 RegUnits.resize(RegUnits.size() + 1);
617 RegUnits.back().Roots[0] = R0;
618 RegUnits.back().Roots[1] = R1;
619 return RegUnits.size() - 1;
622 // Create a new non-native register unit that can be adopted by a register
623 // to increase its pressure. Note that NumNativeRegUnits is not increased.
624 unsigned newRegUnit(unsigned Weight) {
625 RegUnits.resize(RegUnits.size() + 1);
626 RegUnits.back().Weight = Weight;
627 return RegUnits.size() - 1;
630 // Native units are the singular unit of a leaf register. Register aliasing
631 // is completely characterized by native units. Adopted units exist to give
632 // register additional weight but don't affect aliasing.
633 bool isNativeUnit(unsigned RUID) {
634 return RUID < NumNativeRegUnits;
637 unsigned getNumNativeRegUnits() const {
638 return NumNativeRegUnits;
641 RegUnit &getRegUnit(unsigned RUID) { return RegUnits[RUID]; }
642 const RegUnit &getRegUnit(unsigned RUID) const { return RegUnits[RUID]; }
644 std::list<CodeGenRegisterClass> &getRegClasses() { return RegClasses; }
646 const std::list<CodeGenRegisterClass> &getRegClasses() const {
650 // Find a register class from its def.
651 CodeGenRegisterClass *getRegClass(Record*);
653 /// getRegisterClassForRegister - Find the register class that contains the
654 /// specified physical register. If the register is not in a register
655 /// class, return null. If the register is in multiple classes, and the
656 /// classes have a superset-subset relationship and the same set of types,
657 /// return the superclass. Otherwise return null.
658 const CodeGenRegisterClass* getRegClassForRegister(Record *R);
660 // Get the sum of unit weights.
661 unsigned getRegUnitSetWeight(const std::vector<unsigned> &Units) const {
663 for (std::vector<unsigned>::const_iterator
664 I = Units.begin(), E = Units.end(); I != E; ++I)
665 Weight += getRegUnit(*I).Weight;
669 unsigned getRegSetIDAt(unsigned Order) const {
670 return RegUnitSetOrder[Order];
672 const RegUnitSet &getRegSetAt(unsigned Order) const {
673 return RegUnitSets[RegUnitSetOrder[Order]];
676 // Increase a RegUnitWeight.
677 void increaseRegUnitWeight(unsigned RUID, unsigned Inc) {
678 getRegUnit(RUID).Weight += Inc;
681 // Get the number of register pressure dimensions.
682 unsigned getNumRegPressureSets() const { return RegUnitSets.size(); }
684 // Get a set of register unit IDs for a given dimension of pressure.
685 const RegUnitSet &getRegPressureSet(unsigned Idx) const {
686 return RegUnitSets[Idx];
689 // The number of pressure set lists may be larget than the number of
690 // register classes if some register units appeared in a list of sets that
691 // did not correspond to an existing register class.
692 unsigned getNumRegClassPressureSetLists() const {
693 return RegClassUnitSets.size();
696 // Get a list of pressure set IDs for a register class. Liveness of a
697 // register in this class impacts each pressure set in this list by the
698 // weight of the register. An exact solution requires all registers in a
699 // class to have the same class, but it is not strictly guaranteed.
700 ArrayRef<unsigned> getRCPressureSetIDs(unsigned RCIdx) const {
701 return RegClassUnitSets[RCIdx];
704 // Computed derived records such as missing sub-register indices.
705 void computeDerivedInfo();
707 // Compute the set of registers completely covered by the registers in Regs.
708 // The returned BitVector will have a bit set for each register in Regs,
709 // all sub-registers, and all super-registers that are covered by the
710 // registers in Regs.
712 // This is used to compute the mask of call-preserved registers from a list
714 BitVector computeCoveredRegisters(ArrayRef<Record*> Regs);
716 // Bit mask of lanes that cover their registers. A sub-register index whose
717 // LaneMask is contained in CoveringLanes will be completely covered by
718 // another sub-register with the same or larger lane mask.
719 unsigned CoveringLanes;