1 //===- CodeGenRegisters.cpp - Register and RegisterClass Info -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines structures to encapsulate information gleaned from the
11 // target register and register class definitions.
13 //===----------------------------------------------------------------------===//
15 #include "CodeGenRegisters.h"
16 #include "CodeGenTarget.h"
17 #include "llvm/ADT/SmallVector.h"
18 #include "llvm/ADT/StringExtras.h"
22 //===----------------------------------------------------------------------===//
24 //===----------------------------------------------------------------------===//
26 CodeGenRegister::CodeGenRegister(Record *R, unsigned Enum)
29 CostPerUse(R->getValueAsInt("CostPerUse")),
30 SubRegsComplete(false)
33 const std::string &CodeGenRegister::getName() const {
34 return TheDef->getName();
39 CodeGenRegister *SubReg;
40 Record *First, *Second;
41 Orphan(CodeGenRegister *r, Record *a, Record *b)
42 : SubReg(r), First(a), Second(b) {}
46 const CodeGenRegister::SubRegMap &
47 CodeGenRegister::getSubRegs(CodeGenRegBank &RegBank) {
48 // Only compute this map once.
51 SubRegsComplete = true;
53 std::vector<Record*> SubList = TheDef->getValueAsListOfDefs("SubRegs");
54 std::vector<Record*> Indices = TheDef->getValueAsListOfDefs("SubRegIndices");
55 if (SubList.size() != Indices.size())
56 throw TGError(TheDef->getLoc(), "Register " + getName() +
57 " SubRegIndices doesn't match SubRegs");
59 // First insert the direct subregs and make sure they are fully indexed.
60 for (unsigned i = 0, e = SubList.size(); i != e; ++i) {
61 CodeGenRegister *SR = RegBank.getReg(SubList[i]);
62 if (!SubRegs.insert(std::make_pair(Indices[i], SR)).second)
63 throw TGError(TheDef->getLoc(), "SubRegIndex " + Indices[i]->getName() +
64 " appears twice in Register " + getName());
67 // Keep track of inherited subregs and how they can be reached.
68 SmallVector<Orphan, 8> Orphans;
70 // Clone inherited subregs and place duplicate entries on Orphans.
71 // Here the order is important - earlier subregs take precedence.
72 for (unsigned i = 0, e = SubList.size(); i != e; ++i) {
73 CodeGenRegister *SR = RegBank.getReg(SubList[i]);
74 const SubRegMap &Map = SR->getSubRegs(RegBank);
76 // Add this as a super-register of SR now all sub-registers are in the list.
77 // This creates a topological ordering, the exact order depends on the
78 // order getSubRegs is called on all registers.
79 SR->SuperRegs.push_back(this);
81 for (SubRegMap::const_iterator SI = Map.begin(), SE = Map.end(); SI != SE;
83 if (!SubRegs.insert(*SI).second)
84 Orphans.push_back(Orphan(SI->second, Indices[i], SI->first));
86 // Noop sub-register indexes are possible, so avoid duplicates.
88 SI->second->SuperRegs.push_back(this);
92 // Process the composites.
93 ListInit *Comps = TheDef->getValueAsListInit("CompositeIndices");
94 for (unsigned i = 0, e = Comps->size(); i != e; ++i) {
95 DagInit *Pat = dynamic_cast<DagInit*>(Comps->getElement(i));
97 throw TGError(TheDef->getLoc(), "Invalid dag '" +
98 Comps->getElement(i)->getAsString() +
99 "' in CompositeIndices");
100 DefInit *BaseIdxInit = dynamic_cast<DefInit*>(Pat->getOperator());
101 if (!BaseIdxInit || !BaseIdxInit->getDef()->isSubClassOf("SubRegIndex"))
102 throw TGError(TheDef->getLoc(), "Invalid SubClassIndex in " +
105 // Resolve list of subreg indices into R2.
106 CodeGenRegister *R2 = this;
107 for (DagInit::const_arg_iterator di = Pat->arg_begin(),
108 de = Pat->arg_end(); di != de; ++di) {
109 DefInit *IdxInit = dynamic_cast<DefInit*>(*di);
110 if (!IdxInit || !IdxInit->getDef()->isSubClassOf("SubRegIndex"))
111 throw TGError(TheDef->getLoc(), "Invalid SubClassIndex in " +
113 const SubRegMap &R2Subs = R2->getSubRegs(RegBank);
114 SubRegMap::const_iterator ni = R2Subs.find(IdxInit->getDef());
115 if (ni == R2Subs.end())
116 throw TGError(TheDef->getLoc(), "Composite " + Pat->getAsString() +
117 " refers to bad index in " + R2->getName());
121 // Insert composite index. Allow overriding inherited indices etc.
122 SubRegs[BaseIdxInit->getDef()] = R2;
124 // R2 is no longer an orphan.
125 for (unsigned j = 0, je = Orphans.size(); j != je; ++j)
126 if (Orphans[j].SubReg == R2)
127 Orphans[j].SubReg = 0;
130 // Now Orphans contains the inherited subregisters without a direct index.
131 // Create inferred indexes for all missing entries.
132 for (unsigned i = 0, e = Orphans.size(); i != e; ++i) {
133 Orphan &O = Orphans[i];
136 SubRegs[RegBank.getCompositeSubRegIndex(O.First, O.Second, true)] =
143 CodeGenRegister::addSubRegsPreOrder(SetVector<CodeGenRegister*> &OSet) const {
144 assert(SubRegsComplete && "Must precompute sub-registers");
145 std::vector<Record*> Indices = TheDef->getValueAsListOfDefs("SubRegIndices");
146 for (unsigned i = 0, e = Indices.size(); i != e; ++i) {
147 CodeGenRegister *SR = SubRegs.find(Indices[i])->second;
149 SR->addSubRegsPreOrder(OSet);
153 //===----------------------------------------------------------------------===//
154 // CodeGenRegisterClass
155 //===----------------------------------------------------------------------===//
157 CodeGenRegisterClass::CodeGenRegisterClass(Record *R) : TheDef(R) {
158 // Rename anonymous register classes.
159 if (R->getName().size() > 9 && R->getName()[9] == '.') {
160 static unsigned AnonCounter = 0;
161 R->setName("AnonRegClass_"+utostr(AnonCounter++));
164 std::vector<Record*> TypeList = R->getValueAsListOfDefs("RegTypes");
165 for (unsigned i = 0, e = TypeList.size(); i != e; ++i) {
166 Record *Type = TypeList[i];
167 if (!Type->isSubClassOf("ValueType"))
168 throw "RegTypes list member '" + Type->getName() +
169 "' does not derive from the ValueType class!";
170 VTs.push_back(getValueType(Type));
172 assert(!VTs.empty() && "RegisterClass must contain at least one ValueType!");
174 std::vector<Record*> RegList = R->getValueAsListOfDefs("MemberList");
175 for (unsigned i = 0, e = RegList.size(); i != e; ++i) {
176 Record *Reg = RegList[i];
177 if (!Reg->isSubClassOf("Register"))
178 throw "Register Class member '" + Reg->getName() +
179 "' does not derive from the Register class!";
180 Elements.push_back(Reg);
183 // SubRegClasses is a list<dag> containing (RC, subregindex, ...) dags.
184 ListInit *SRC = R->getValueAsListInit("SubRegClasses");
185 for (ListInit::const_iterator i = SRC->begin(), e = SRC->end(); i != e; ++i) {
186 DagInit *DAG = dynamic_cast<DagInit*>(*i);
187 if (!DAG) throw "SubRegClasses must contain DAGs";
188 DefInit *DAGOp = dynamic_cast<DefInit*>(DAG->getOperator());
190 if (!DAGOp || !(RCRec = DAGOp->getDef())->isSubClassOf("RegisterClass"))
191 throw "Operator '" + DAG->getOperator()->getAsString() +
192 "' in SubRegClasses is not a RegisterClass";
193 // Iterate over args, all SubRegIndex instances.
194 for (DagInit::const_arg_iterator ai = DAG->arg_begin(), ae = DAG->arg_end();
196 DefInit *Idx = dynamic_cast<DefInit*>(*ai);
198 if (!Idx || !(IdxRec = Idx->getDef())->isSubClassOf("SubRegIndex"))
199 throw "Argument '" + (*ai)->getAsString() +
200 "' in SubRegClasses is not a SubRegIndex";
201 if (!SubRegClasses.insert(std::make_pair(IdxRec, RCRec)).second)
202 throw "SubRegIndex '" + IdxRec->getName() + "' mentioned twice";
206 // Allow targets to override the size in bits of the RegisterClass.
207 unsigned Size = R->getValueAsInt("Size");
209 Namespace = R->getValueAsString("Namespace");
210 SpillSize = Size ? Size : EVT(VTs[0]).getSizeInBits();
211 SpillAlignment = R->getValueAsInt("Alignment");
212 CopyCost = R->getValueAsInt("CopyCost");
213 Allocatable = R->getValueAsBit("isAllocatable");
214 MethodBodies = R->getValueAsCode("MethodBodies");
215 MethodProtos = R->getValueAsCode("MethodProtos");
218 const std::string &CodeGenRegisterClass::getName() const {
219 return TheDef->getName();
222 //===----------------------------------------------------------------------===//
224 //===----------------------------------------------------------------------===//
226 CodeGenRegBank::CodeGenRegBank(RecordKeeper &Records) : Records(Records) {
227 // Read in the user-defined (named) sub-register indices.
228 // More indices will be synthesized later.
229 SubRegIndices = Records.getAllDerivedDefinitions("SubRegIndex");
230 std::sort(SubRegIndices.begin(), SubRegIndices.end(), LessRecord());
231 NumNamedIndices = SubRegIndices.size();
233 // Read in the register definitions.
234 std::vector<Record*> Regs = Records.getAllDerivedDefinitions("Register");
235 std::sort(Regs.begin(), Regs.end(), LessRecord());
236 Registers.reserve(Regs.size());
237 // Assign the enumeration values.
238 for (unsigned i = 0, e = Regs.size(); i != e; ++i)
239 Registers.push_back(CodeGenRegister(Regs[i], i + 1));
242 CodeGenRegister *CodeGenRegBank::getReg(Record *Def) {
244 for (unsigned i = 0, e = Registers.size(); i != e; ++i)
245 Def2Reg[Registers[i].TheDef] = &Registers[i];
247 if (CodeGenRegister *Reg = Def2Reg[Def])
250 throw TGError(Def->getLoc(), "Not a known Register!");
253 Record *CodeGenRegBank::getCompositeSubRegIndex(Record *A, Record *B,
255 // Look for an existing entry.
256 Record *&Comp = Composite[std::make_pair(A, B)];
260 // None exists, synthesize one.
261 std::string Name = A->getName() + "_then_" + B->getName();
262 Comp = new Record(Name, SMLoc(), Records);
263 Records.addDef(Comp);
264 SubRegIndices.push_back(Comp);
268 unsigned CodeGenRegBank::getSubRegIndexNo(Record *idx) {
269 std::vector<Record*>::const_iterator i =
270 std::find(SubRegIndices.begin(), SubRegIndices.end(), idx);
271 assert(i != SubRegIndices.end() && "Not a SubRegIndex");
272 return (i - SubRegIndices.begin()) + 1;
275 void CodeGenRegBank::computeComposites() {
276 // Precompute all sub-register maps. This will create Composite entries for
277 // all inferred sub-register indices.
278 for (unsigned i = 0, e = Registers.size(); i != e; ++i)
279 Registers[i].getSubRegs(*this);
281 for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
282 CodeGenRegister *Reg1 = &Registers[i];
283 const CodeGenRegister::SubRegMap &SRM1 = Reg1->getSubRegs();
284 for (CodeGenRegister::SubRegMap::const_iterator i1 = SRM1.begin(),
285 e1 = SRM1.end(); i1 != e1; ++i1) {
286 Record *Idx1 = i1->first;
287 CodeGenRegister *Reg2 = i1->second;
288 // Ignore identity compositions.
291 const CodeGenRegister::SubRegMap &SRM2 = Reg2->getSubRegs();
292 // Try composing Idx1 with another SubRegIndex.
293 for (CodeGenRegister::SubRegMap::const_iterator i2 = SRM2.begin(),
294 e2 = SRM2.end(); i2 != e2; ++i2) {
295 std::pair<Record*, Record*> IdxPair(Idx1, i2->first);
296 CodeGenRegister *Reg3 = i2->second;
297 // Ignore identity compositions.
300 // OK Reg1:IdxPair == Reg3. Find the index with Reg:Idx == Reg3.
301 for (CodeGenRegister::SubRegMap::const_iterator i1d = SRM1.begin(),
302 e1d = SRM1.end(); i1d != e1d; ++i1d) {
303 if (i1d->second == Reg3) {
304 std::pair<CompositeMap::iterator, bool> Ins =
305 Composite.insert(std::make_pair(IdxPair, i1d->first));
306 // Conflicting composition? Emit a warning but allow it.
307 if (!Ins.second && Ins.first->second != i1d->first) {
308 errs() << "Warning: SubRegIndex " << getQualifiedName(Idx1)
309 << " and " << getQualifiedName(IdxPair.second)
310 << " compose ambiguously as "
311 << getQualifiedName(Ins.first->second) << " or "
312 << getQualifiedName(i1d->first) << "\n";
320 // We don't care about the difference between (Idx1, Idx2) -> Idx2 and invalid
321 // compositions, so remove any mappings of that form.
322 for (CompositeMap::iterator i = Composite.begin(), e = Composite.end();
324 CompositeMap::iterator j = i;
326 if (j->first.second == j->second)
331 // Compute sets of overlapping registers.
333 // The standard set is all super-registers and all sub-registers, but the
334 // target description can add arbitrary overlapping registers via the 'Aliases'
335 // field. This complicates things, but we can compute overlapping sets using
336 // the following rules:
338 // 1. The relation overlap(A, B) is reflexive and symmetric but not transitive.
340 // 2. overlap(A, B) implies overlap(A, S) for all S in supers(B).
344 // overlap(A, B) iff there exists:
345 // A' in { A, subregs(A) } and B' in { B, subregs(B) } such that:
346 // A' = B' or A' in aliases(B') or B' in aliases(A').
348 // Here subregs(A) is the full flattened sub-register set returned by
349 // A.getSubRegs() while aliases(A) is simply the special 'Aliases' field in the
350 // description of register A.
352 // This also implies that registers with a common sub-register are considered
353 // overlapping. This can happen when forming register pairs:
359 // In this case, we will infer an overlap between P0 and P1 because of the
360 // shared sub-register R1. There is no overlap between P0 and P2.
362 void CodeGenRegBank::
363 computeOverlaps(std::map<const CodeGenRegister*, CodeGenRegister::Set> &Map) {
366 // Collect overlaps that don't follow from rule 2.
367 for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
368 CodeGenRegister *Reg = &Registers[i];
369 CodeGenRegister::Set &Overlaps = Map[Reg];
371 // Reg overlaps itself.
372 Overlaps.insert(Reg);
374 // All super-registers overlap.
375 const CodeGenRegister::SuperRegList &Supers = Reg->getSuperRegs();
376 Overlaps.insert(Supers.begin(), Supers.end());
378 // Form symmetrical relations from the special Aliases[] lists.
379 std::vector<Record*> RegList = Reg->TheDef->getValueAsListOfDefs("Aliases");
380 for (unsigned i2 = 0, e2 = RegList.size(); i2 != e2; ++i2) {
381 CodeGenRegister *Reg2 = getReg(RegList[i2]);
382 CodeGenRegister::Set &Overlaps2 = Map[Reg2];
383 const CodeGenRegister::SuperRegList &Supers2 = Reg2->getSuperRegs();
384 // Reg overlaps Reg2 which implies it overlaps supers(Reg2).
385 Overlaps.insert(Reg2);
386 Overlaps.insert(Supers2.begin(), Supers2.end());
387 Overlaps2.insert(Reg);
388 Overlaps2.insert(Supers.begin(), Supers.end());
392 // Apply rule 2. and inherit all sub-register overlaps.
393 for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
394 CodeGenRegister *Reg = &Registers[i];
395 CodeGenRegister::Set &Overlaps = Map[Reg];
396 const CodeGenRegister::SubRegMap &SRM = Reg->getSubRegs();
397 for (CodeGenRegister::SubRegMap::const_iterator i2 = SRM.begin(),
398 e2 = SRM.end(); i2 != e2; ++i2) {
399 CodeGenRegister::Set &Overlaps2 = Map[i2->second];
400 Overlaps.insert(Overlaps2.begin(), Overlaps2.end());
405 void CodeGenRegBank::computeDerivedInfo() {