1 //===- CodeGenRegisters.cpp - Register and RegisterClass Info -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines structures to encapsulate information gleaned from the
11 // target register and register class definitions.
13 //===----------------------------------------------------------------------===//
15 #include "CodeGenRegisters.h"
16 #include "CodeGenTarget.h"
17 #include "llvm/ADT/SmallVector.h"
18 #include "llvm/ADT/StringExtras.h"
22 //===----------------------------------------------------------------------===//
24 //===----------------------------------------------------------------------===//
26 CodeGenRegister::CodeGenRegister(Record *R, unsigned Enum)
29 CostPerUse(R->getValueAsInt("CostPerUse")),
30 SubRegsComplete(false)
33 const std::string &CodeGenRegister::getName() const {
34 return TheDef->getName();
39 CodeGenRegister *SubReg;
40 Record *First, *Second;
41 Orphan(CodeGenRegister *r, Record *a, Record *b)
42 : SubReg(r), First(a), Second(b) {}
46 const CodeGenRegister::SubRegMap &
47 CodeGenRegister::getSubRegs(CodeGenRegBank &RegBank) {
48 // Only compute this map once.
51 SubRegsComplete = true;
53 std::vector<Record*> SubList = TheDef->getValueAsListOfDefs("SubRegs");
54 std::vector<Record*> Indices = TheDef->getValueAsListOfDefs("SubRegIndices");
55 if (SubList.size() != Indices.size())
56 throw TGError(TheDef->getLoc(), "Register " + getName() +
57 " SubRegIndices doesn't match SubRegs");
59 // First insert the direct subregs and make sure they are fully indexed.
60 for (unsigned i = 0, e = SubList.size(); i != e; ++i) {
61 CodeGenRegister *SR = RegBank.getReg(SubList[i]);
62 if (!SubRegs.insert(std::make_pair(Indices[i], SR)).second)
63 throw TGError(TheDef->getLoc(), "SubRegIndex " + Indices[i]->getName() +
64 " appears twice in Register " + getName());
67 // Keep track of inherited subregs and how they can be reached.
68 SmallVector<Orphan, 8> Orphans;
70 // Clone inherited subregs and place duplicate entries on Orphans.
71 // Here the order is important - earlier subregs take precedence.
72 for (unsigned i = 0, e = SubList.size(); i != e; ++i) {
73 CodeGenRegister *SR = RegBank.getReg(SubList[i]);
74 const SubRegMap &Map = SR->getSubRegs(RegBank);
76 // Add this as a super-register of SR now all sub-registers are in the list.
77 // This creates a topological ordering, the exact order depends on the
78 // order getSubRegs is called on all registers.
79 SR->SuperRegs.push_back(this);
81 for (SubRegMap::const_iterator SI = Map.begin(), SE = Map.end(); SI != SE;
83 if (!SubRegs.insert(*SI).second)
84 Orphans.push_back(Orphan(SI->second, Indices[i], SI->first));
86 // Noop sub-register indexes are possible, so avoid duplicates.
88 SI->second->SuperRegs.push_back(this);
92 // Process the composites.
93 ListInit *Comps = TheDef->getValueAsListInit("CompositeIndices");
94 for (unsigned i = 0, e = Comps->size(); i != e; ++i) {
95 DagInit *Pat = dynamic_cast<DagInit*>(Comps->getElement(i));
97 throw TGError(TheDef->getLoc(), "Invalid dag '" +
98 Comps->getElement(i)->getAsString() +
99 "' in CompositeIndices");
100 DefInit *BaseIdxInit = dynamic_cast<DefInit*>(Pat->getOperator());
101 if (!BaseIdxInit || !BaseIdxInit->getDef()->isSubClassOf("SubRegIndex"))
102 throw TGError(TheDef->getLoc(), "Invalid SubClassIndex in " +
105 // Resolve list of subreg indices into R2.
106 CodeGenRegister *R2 = this;
107 for (DagInit::const_arg_iterator di = Pat->arg_begin(),
108 de = Pat->arg_end(); di != de; ++di) {
109 DefInit *IdxInit = dynamic_cast<DefInit*>(*di);
110 if (!IdxInit || !IdxInit->getDef()->isSubClassOf("SubRegIndex"))
111 throw TGError(TheDef->getLoc(), "Invalid SubClassIndex in " +
113 const SubRegMap &R2Subs = R2->getSubRegs(RegBank);
114 SubRegMap::const_iterator ni = R2Subs.find(IdxInit->getDef());
115 if (ni == R2Subs.end())
116 throw TGError(TheDef->getLoc(), "Composite " + Pat->getAsString() +
117 " refers to bad index in " + R2->getName());
121 // Insert composite index. Allow overriding inherited indices etc.
122 SubRegs[BaseIdxInit->getDef()] = R2;
124 // R2 is no longer an orphan.
125 for (unsigned j = 0, je = Orphans.size(); j != je; ++j)
126 if (Orphans[j].SubReg == R2)
127 Orphans[j].SubReg = 0;
130 // Now Orphans contains the inherited subregisters without a direct index.
131 // Create inferred indexes for all missing entries.
132 for (unsigned i = 0, e = Orphans.size(); i != e; ++i) {
133 Orphan &O = Orphans[i];
136 SubRegs[RegBank.getCompositeSubRegIndex(O.First, O.Second, true)] =
143 CodeGenRegister::addSubRegsPreOrder(SetVector<CodeGenRegister*> &OSet) const {
144 assert(SubRegsComplete && "Must precompute sub-registers");
145 std::vector<Record*> Indices = TheDef->getValueAsListOfDefs("SubRegIndices");
146 for (unsigned i = 0, e = Indices.size(); i != e; ++i) {
147 CodeGenRegister *SR = SubRegs.find(Indices[i])->second;
149 SR->addSubRegsPreOrder(OSet);
153 //===----------------------------------------------------------------------===//
155 //===----------------------------------------------------------------------===//
157 // A RegisterTuples def is used to generate pseudo-registers from lists of
158 // sub-registers. We provide a SetTheory expander class that returns the new
161 struct TupleExpander : SetTheory::Expander {
162 void expand(SetTheory &ST, Record *Def, SetTheory::RecSet &Elts) {
163 std::vector<Record*> Indices = Def->getValueAsListOfDefs("SubRegIndices");
164 unsigned Dim = Indices.size();
165 ListInit *SubRegs = Def->getValueAsListInit("SubRegs");
166 if (Dim != SubRegs->getSize())
167 throw TGError(Def->getLoc(), "SubRegIndices and SubRegs size mismatch");
169 throw TGError(Def->getLoc(), "Tuples must have at least 2 sub-registers");
171 // Evaluate the sub-register lists to be zipped.
172 unsigned Length = ~0u;
173 SmallVector<SetTheory::RecSet, 4> Lists(Dim);
174 for (unsigned i = 0; i != Dim; ++i) {
175 ST.evaluate(SubRegs->getElement(i), Lists[i]);
176 Length = std::min(Length, unsigned(Lists[i].size()));
182 // Precompute some types.
183 Record *RegisterCl = Def->getRecords().getClass("Register");
184 RecTy *RegisterRecTy = new RecordRecTy(RegisterCl);
185 StringInit *BlankName = new StringInit("");
188 for (unsigned n = 0; n != Length; ++n) {
190 Record *Proto = Lists[0][n];
191 std::vector<Init*> Tuple;
192 unsigned CostPerUse = 0;
193 for (unsigned i = 0; i != Dim; ++i) {
194 Record *Reg = Lists[i][n];
196 Name += Reg->getName();
197 Tuple.push_back(new DefInit(Reg));
198 CostPerUse = std::max(CostPerUse,
199 unsigned(Reg->getValueAsInt("CostPerUse")));
202 // Create a new Record representing the synthesized register. This record
203 // is only for consumption by CodeGenRegister, it is not added to the
205 Record *NewReg = new Record(Name, Def->getLoc(), Def->getRecords());
208 // Copy Proto super-classes.
209 for (unsigned i = 0, e = Proto->getSuperClasses().size(); i != e; ++i)
210 NewReg->addSuperClass(Proto->getSuperClasses()[i]);
212 // Copy Proto fields.
213 for (unsigned i = 0, e = Proto->getValues().size(); i != e; ++i) {
214 RecordVal RV = Proto->getValues()[i];
216 // Replace the sub-register list with Tuple.
217 if (RV.getName() == "SubRegs")
218 RV.setValue(new ListInit(Tuple, RegisterRecTy));
220 // Provide a blank AsmName. MC hacks are required anyway.
221 if (RV.getName() == "AsmName")
222 RV.setValue(BlankName);
224 // CostPerUse is aggregated from all Tuple members.
225 if (RV.getName() == "CostPerUse")
226 RV.setValue(new IntInit(CostPerUse));
228 // Copy fields from the RegisterTuples def.
229 if (RV.getName() == "SubRegIndices" ||
230 RV.getName() == "CompositeIndices") {
231 NewReg->addValue(*Def->getValue(RV.getName()));
235 // Some fields get their default uninitialized value.
236 if (RV.getName() == "DwarfNumbers" ||
237 RV.getName() == "DwarfAlias" ||
238 RV.getName() == "Aliases") {
239 if (const RecordVal *DefRV = RegisterCl->getValue(RV.getName()))
240 NewReg->addValue(*DefRV);
244 // Everything else is copied from Proto.
245 NewReg->addValue(RV);
252 //===----------------------------------------------------------------------===//
253 // CodeGenRegisterClass
254 //===----------------------------------------------------------------------===//
256 CodeGenRegisterClass::CodeGenRegisterClass(CodeGenRegBank &RegBank, Record *R)
258 // Rename anonymous register classes.
259 if (R->getName().size() > 9 && R->getName()[9] == '.') {
260 static unsigned AnonCounter = 0;
261 R->setName("AnonRegClass_"+utostr(AnonCounter++));
264 std::vector<Record*> TypeList = R->getValueAsListOfDefs("RegTypes");
265 for (unsigned i = 0, e = TypeList.size(); i != e; ++i) {
266 Record *Type = TypeList[i];
267 if (!Type->isSubClassOf("ValueType"))
268 throw "RegTypes list member '" + Type->getName() +
269 "' does not derive from the ValueType class!";
270 VTs.push_back(getValueType(Type));
272 assert(!VTs.empty() && "RegisterClass must contain at least one ValueType!");
274 // Default allocation order always contains all registers.
275 Elements = RegBank.getSets().expand(R);
276 for (unsigned i = 0, e = Elements->size(); i != e; ++i)
277 Members.insert(RegBank.getReg((*Elements)[i]));
279 // Alternative allocation orders may be subsets.
280 ListInit *Alts = R->getValueAsListInit("AltOrders");
281 AltOrders.resize(Alts->size());
282 SetTheory::RecSet Order;
283 for (unsigned i = 0, e = Alts->size(); i != e; ++i) {
284 RegBank.getSets().evaluate(Alts->getElement(i), Order);
285 AltOrders[i].append(Order.begin(), Order.end());
286 // Verify that all altorder members are regclass members.
287 while (!Order.empty()) {
288 CodeGenRegister *Reg = RegBank.getReg(Order.back());
291 throw TGError(R->getLoc(), " AltOrder register " + Reg->getName() +
292 " is not a class member");
296 // SubRegClasses is a list<dag> containing (RC, subregindex, ...) dags.
297 ListInit *SRC = R->getValueAsListInit("SubRegClasses");
298 for (ListInit::const_iterator i = SRC->begin(), e = SRC->end(); i != e; ++i) {
299 DagInit *DAG = dynamic_cast<DagInit*>(*i);
300 if (!DAG) throw "SubRegClasses must contain DAGs";
301 DefInit *DAGOp = dynamic_cast<DefInit*>(DAG->getOperator());
303 if (!DAGOp || !(RCRec = DAGOp->getDef())->isSubClassOf("RegisterClass"))
304 throw "Operator '" + DAG->getOperator()->getAsString() +
305 "' in SubRegClasses is not a RegisterClass";
306 // Iterate over args, all SubRegIndex instances.
307 for (DagInit::const_arg_iterator ai = DAG->arg_begin(), ae = DAG->arg_end();
309 DefInit *Idx = dynamic_cast<DefInit*>(*ai);
311 if (!Idx || !(IdxRec = Idx->getDef())->isSubClassOf("SubRegIndex"))
312 throw "Argument '" + (*ai)->getAsString() +
313 "' in SubRegClasses is not a SubRegIndex";
314 if (!SubRegClasses.insert(std::make_pair(IdxRec, RCRec)).second)
315 throw "SubRegIndex '" + IdxRec->getName() + "' mentioned twice";
319 // Allow targets to override the size in bits of the RegisterClass.
320 unsigned Size = R->getValueAsInt("Size");
322 Namespace = R->getValueAsString("Namespace");
323 SpillSize = Size ? Size : EVT(VTs[0]).getSizeInBits();
324 SpillAlignment = R->getValueAsInt("Alignment");
325 CopyCost = R->getValueAsInt("CopyCost");
326 Allocatable = R->getValueAsBit("isAllocatable");
327 AltOrderSelect = R->getValueAsCode("AltOrderSelect");
330 bool CodeGenRegisterClass::contains(const CodeGenRegister *Reg) const {
331 return Members.count(Reg);
334 // Returns true if RC is a strict subclass.
335 // RC is a sub-class of this class if it is a valid replacement for any
336 // instruction operand where a register of this classis required. It must
337 // satisfy these conditions:
339 // 1. All RC registers are also in this.
340 // 2. The RC spill size must not be smaller than our spill size.
341 // 3. RC spill alignment must be compatible with ours.
343 bool CodeGenRegisterClass::hasSubClass(const CodeGenRegisterClass *RC) const {
344 return SpillAlignment && RC->SpillAlignment % SpillAlignment == 0 &&
345 SpillSize <= RC->SpillSize &&
346 std::includes(Members.begin(), Members.end(),
347 RC->Members.begin(), RC->Members.end(),
348 CodeGenRegister::Less());
351 const std::string &CodeGenRegisterClass::getName() const {
352 return TheDef->getName();
355 //===----------------------------------------------------------------------===//
357 //===----------------------------------------------------------------------===//
359 CodeGenRegBank::CodeGenRegBank(RecordKeeper &Records) : Records(Records) {
360 // Configure register Sets to understand register classes and tuples.
361 Sets.addFieldExpander("RegisterClass", "MemberList");
362 Sets.addExpander("RegisterTuples", new TupleExpander());
364 // Read in the user-defined (named) sub-register indices.
365 // More indices will be synthesized later.
366 SubRegIndices = Records.getAllDerivedDefinitions("SubRegIndex");
367 std::sort(SubRegIndices.begin(), SubRegIndices.end(), LessRecord());
368 NumNamedIndices = SubRegIndices.size();
370 // Read in the register definitions.
371 std::vector<Record*> Regs = Records.getAllDerivedDefinitions("Register");
372 std::sort(Regs.begin(), Regs.end(), LessRecord());
373 Registers.reserve(Regs.size());
374 // Assign the enumeration values.
375 for (unsigned i = 0, e = Regs.size(); i != e; ++i)
378 // Expand tuples and number the new registers.
379 std::vector<Record*> Tups =
380 Records.getAllDerivedDefinitions("RegisterTuples");
381 for (unsigned i = 0, e = Tups.size(); i != e; ++i) {
382 const std::vector<Record*> *TupRegs = Sets.expand(Tups[i]);
383 for (unsigned j = 0, je = TupRegs->size(); j != je; ++j)
384 getReg((*TupRegs)[j]);
387 // Read in register class definitions.
388 std::vector<Record*> RCs = Records.getAllDerivedDefinitions("RegisterClass");
390 throw std::string("No 'RegisterClass' subclasses defined!");
392 RegClasses.reserve(RCs.size());
393 for (unsigned i = 0, e = RCs.size(); i != e; ++i)
394 RegClasses.push_back(CodeGenRegisterClass(*this, RCs[i]));
397 CodeGenRegister *CodeGenRegBank::getReg(Record *Def) {
398 CodeGenRegister *&Reg = Def2Reg[Def];
401 Reg = new CodeGenRegister(Def, Registers.size() + 1);
402 Registers.push_back(Reg);
406 CodeGenRegisterClass *CodeGenRegBank::getRegClass(Record *Def) {
408 for (unsigned i = 0, e = RegClasses.size(); i != e; ++i)
409 Def2RC[RegClasses[i].TheDef] = &RegClasses[i];
411 if (CodeGenRegisterClass *RC = Def2RC[Def])
414 throw TGError(Def->getLoc(), "Not a known RegisterClass!");
417 Record *CodeGenRegBank::getCompositeSubRegIndex(Record *A, Record *B,
419 // Look for an existing entry.
420 Record *&Comp = Composite[std::make_pair(A, B)];
424 // None exists, synthesize one.
425 std::string Name = A->getName() + "_then_" + B->getName();
426 Comp = new Record(Name, SMLoc(), Records);
427 Records.addDef(Comp);
428 SubRegIndices.push_back(Comp);
432 unsigned CodeGenRegBank::getSubRegIndexNo(Record *idx) {
433 std::vector<Record*>::const_iterator i =
434 std::find(SubRegIndices.begin(), SubRegIndices.end(), idx);
435 assert(i != SubRegIndices.end() && "Not a SubRegIndex");
436 return (i - SubRegIndices.begin()) + 1;
439 void CodeGenRegBank::computeComposites() {
440 // Precompute all sub-register maps. This will create Composite entries for
441 // all inferred sub-register indices.
442 for (unsigned i = 0, e = Registers.size(); i != e; ++i)
443 Registers[i]->getSubRegs(*this);
445 for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
446 CodeGenRegister *Reg1 = Registers[i];
447 const CodeGenRegister::SubRegMap &SRM1 = Reg1->getSubRegs();
448 for (CodeGenRegister::SubRegMap::const_iterator i1 = SRM1.begin(),
449 e1 = SRM1.end(); i1 != e1; ++i1) {
450 Record *Idx1 = i1->first;
451 CodeGenRegister *Reg2 = i1->second;
452 // Ignore identity compositions.
455 const CodeGenRegister::SubRegMap &SRM2 = Reg2->getSubRegs();
456 // Try composing Idx1 with another SubRegIndex.
457 for (CodeGenRegister::SubRegMap::const_iterator i2 = SRM2.begin(),
458 e2 = SRM2.end(); i2 != e2; ++i2) {
459 std::pair<Record*, Record*> IdxPair(Idx1, i2->first);
460 CodeGenRegister *Reg3 = i2->second;
461 // Ignore identity compositions.
464 // OK Reg1:IdxPair == Reg3. Find the index with Reg:Idx == Reg3.
465 for (CodeGenRegister::SubRegMap::const_iterator i1d = SRM1.begin(),
466 e1d = SRM1.end(); i1d != e1d; ++i1d) {
467 if (i1d->second == Reg3) {
468 std::pair<CompositeMap::iterator, bool> Ins =
469 Composite.insert(std::make_pair(IdxPair, i1d->first));
470 // Conflicting composition? Emit a warning but allow it.
471 if (!Ins.second && Ins.first->second != i1d->first) {
472 errs() << "Warning: SubRegIndex " << getQualifiedName(Idx1)
473 << " and " << getQualifiedName(IdxPair.second)
474 << " compose ambiguously as "
475 << getQualifiedName(Ins.first->second) << " or "
476 << getQualifiedName(i1d->first) << "\n";
484 // We don't care about the difference between (Idx1, Idx2) -> Idx2 and invalid
485 // compositions, so remove any mappings of that form.
486 for (CompositeMap::iterator i = Composite.begin(), e = Composite.end();
488 CompositeMap::iterator j = i;
490 if (j->first.second == j->second)
495 // Compute sets of overlapping registers.
497 // The standard set is all super-registers and all sub-registers, but the
498 // target description can add arbitrary overlapping registers via the 'Aliases'
499 // field. This complicates things, but we can compute overlapping sets using
500 // the following rules:
502 // 1. The relation overlap(A, B) is reflexive and symmetric but not transitive.
504 // 2. overlap(A, B) implies overlap(A, S) for all S in supers(B).
508 // overlap(A, B) iff there exists:
509 // A' in { A, subregs(A) } and B' in { B, subregs(B) } such that:
510 // A' = B' or A' in aliases(B') or B' in aliases(A').
512 // Here subregs(A) is the full flattened sub-register set returned by
513 // A.getSubRegs() while aliases(A) is simply the special 'Aliases' field in the
514 // description of register A.
516 // This also implies that registers with a common sub-register are considered
517 // overlapping. This can happen when forming register pairs:
523 // In this case, we will infer an overlap between P0 and P1 because of the
524 // shared sub-register R1. There is no overlap between P0 and P2.
526 void CodeGenRegBank::
527 computeOverlaps(std::map<const CodeGenRegister*, CodeGenRegister::Set> &Map) {
530 // Collect overlaps that don't follow from rule 2.
531 for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
532 CodeGenRegister *Reg = Registers[i];
533 CodeGenRegister::Set &Overlaps = Map[Reg];
535 // Reg overlaps itself.
536 Overlaps.insert(Reg);
538 // All super-registers overlap.
539 const CodeGenRegister::SuperRegList &Supers = Reg->getSuperRegs();
540 Overlaps.insert(Supers.begin(), Supers.end());
542 // Form symmetrical relations from the special Aliases[] lists.
543 std::vector<Record*> RegList = Reg->TheDef->getValueAsListOfDefs("Aliases");
544 for (unsigned i2 = 0, e2 = RegList.size(); i2 != e2; ++i2) {
545 CodeGenRegister *Reg2 = getReg(RegList[i2]);
546 CodeGenRegister::Set &Overlaps2 = Map[Reg2];
547 const CodeGenRegister::SuperRegList &Supers2 = Reg2->getSuperRegs();
548 // Reg overlaps Reg2 which implies it overlaps supers(Reg2).
549 Overlaps.insert(Reg2);
550 Overlaps.insert(Supers2.begin(), Supers2.end());
551 Overlaps2.insert(Reg);
552 Overlaps2.insert(Supers.begin(), Supers.end());
556 // Apply rule 2. and inherit all sub-register overlaps.
557 for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
558 CodeGenRegister *Reg = Registers[i];
559 CodeGenRegister::Set &Overlaps = Map[Reg];
560 const CodeGenRegister::SubRegMap &SRM = Reg->getSubRegs();
561 for (CodeGenRegister::SubRegMap::const_iterator i2 = SRM.begin(),
562 e2 = SRM.end(); i2 != e2; ++i2) {
563 CodeGenRegister::Set &Overlaps2 = Map[i2->second];
564 Overlaps.insert(Overlaps2.begin(), Overlaps2.end());
569 void CodeGenRegBank::computeDerivedInfo() {
573 /// getRegisterClassForRegister - Find the register class that contains the
574 /// specified physical register. If the register is not in a register class,
575 /// return null. If the register is in multiple classes, and the classes have a
576 /// superset-subset relationship and the same set of types, return the
577 /// superclass. Otherwise return null.
578 const CodeGenRegisterClass*
579 CodeGenRegBank::getRegClassForRegister(Record *R) {
580 const CodeGenRegister *Reg = getReg(R);
581 const std::vector<CodeGenRegisterClass> &RCs = getRegClasses();
582 const CodeGenRegisterClass *FoundRC = 0;
583 for (unsigned i = 0, e = RCs.size(); i != e; ++i) {
584 const CodeGenRegisterClass &RC = RCs[i];
585 if (!RC.contains(Reg))
588 // If this is the first class that contains the register,
589 // make a note of it and go on to the next class.
595 // If a register's classes have different types, return null.
596 if (RC.getValueTypes() != FoundRC->getValueTypes())
599 // Check to see if the previously found class that contains
600 // the register is a subclass of the current class. If so,
601 // prefer the superclass.
602 if (RC.hasSubClass(FoundRC)) {
607 // Check to see if the previously found class that contains
608 // the register is a superclass of the current class. If so,
609 // prefer the superclass.
610 if (FoundRC->hasSubClass(&RC))
613 // Multiple classes, and neither is a superclass of the other.