1 //===- CodeGenRegisters.cpp - Register and RegisterClass Info -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines structures to encapsulate information gleaned from the
11 // target register and register class definitions.
13 //===----------------------------------------------------------------------===//
15 #include "CodeGenRegisters.h"
16 #include "CodeGenTarget.h"
17 #include "llvm/ADT/IntEqClasses.h"
18 #include "llvm/ADT/STLExtras.h"
19 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/ADT/StringExtras.h"
21 #include "llvm/ADT/Twine.h"
22 #include "llvm/Support/Debug.h"
23 #include "llvm/TableGen/Error.h"
27 #define DEBUG_TYPE "regalloc-emitter"
29 //===----------------------------------------------------------------------===//
31 //===----------------------------------------------------------------------===//
33 CodeGenSubRegIndex::CodeGenSubRegIndex(Record *R, unsigned Enum)
34 : TheDef(R), EnumValue(Enum), LaneMask(0), AllSuperRegsCovered(true) {
36 if (R->getValue("Namespace"))
37 Namespace = R->getValueAsString("Namespace");
38 Size = R->getValueAsInt("Size");
39 Offset = R->getValueAsInt("Offset");
42 CodeGenSubRegIndex::CodeGenSubRegIndex(StringRef N, StringRef Nspace,
44 : TheDef(nullptr), Name(N), Namespace(Nspace), Size(-1), Offset(-1),
45 EnumValue(Enum), LaneMask(0), AllSuperRegsCovered(true) {
48 std::string CodeGenSubRegIndex::getQualifiedName() const {
49 std::string N = getNamespace();
56 void CodeGenSubRegIndex::updateComponents(CodeGenRegBank &RegBank) {
60 std::vector<Record*> Comps = TheDef->getValueAsListOfDefs("ComposedOf");
62 if (Comps.size() != 2)
63 PrintFatalError(TheDef->getLoc(),
64 "ComposedOf must have exactly two entries");
65 CodeGenSubRegIndex *A = RegBank.getSubRegIdx(Comps[0]);
66 CodeGenSubRegIndex *B = RegBank.getSubRegIdx(Comps[1]);
67 CodeGenSubRegIndex *X = A->addComposite(B, this);
69 PrintFatalError(TheDef->getLoc(), "Ambiguous ComposedOf entries");
72 std::vector<Record*> Parts =
73 TheDef->getValueAsListOfDefs("CoveringSubRegIndices");
76 PrintFatalError(TheDef->getLoc(),
77 "CoveredBySubRegs must have two or more entries");
78 SmallVector<CodeGenSubRegIndex*, 8> IdxParts;
79 for (unsigned i = 0, e = Parts.size(); i != e; ++i)
80 IdxParts.push_back(RegBank.getSubRegIdx(Parts[i]));
81 RegBank.addConcatSubRegIndex(IdxParts, this);
85 unsigned CodeGenSubRegIndex::computeLaneMask() const {
90 // Recursion guard, shouldn't be required.
93 // The lane mask is simply the union of all sub-indices.
95 for (const auto &C : Composed)
96 M |= C.second->computeLaneMask();
97 assert(M && "Missing lane mask, sub-register cycle?");
102 //===----------------------------------------------------------------------===//
104 //===----------------------------------------------------------------------===//
106 CodeGenRegister::CodeGenRegister(Record *R, unsigned Enum)
109 CostPerUse(R->getValueAsInt("CostPerUse")),
110 CoveredBySubRegs(R->getValueAsBit("CoveredBySubRegs")),
111 HasDisjunctSubRegs(false),
112 SubRegsComplete(false),
113 SuperRegsComplete(false),
117 void CodeGenRegister::buildObjectGraph(CodeGenRegBank &RegBank) {
118 std::vector<Record*> SRIs = TheDef->getValueAsListOfDefs("SubRegIndices");
119 std::vector<Record*> SRs = TheDef->getValueAsListOfDefs("SubRegs");
121 if (SRIs.size() != SRs.size())
122 PrintFatalError(TheDef->getLoc(),
123 "SubRegs and SubRegIndices must have the same size");
125 for (unsigned i = 0, e = SRIs.size(); i != e; ++i) {
126 ExplicitSubRegIndices.push_back(RegBank.getSubRegIdx(SRIs[i]));
127 ExplicitSubRegs.push_back(RegBank.getReg(SRs[i]));
130 // Also compute leading super-registers. Each register has a list of
131 // covered-by-subregs super-registers where it appears as the first explicit
134 // This is used by computeSecondarySubRegs() to find candidates.
135 if (CoveredBySubRegs && !ExplicitSubRegs.empty())
136 ExplicitSubRegs.front()->LeadingSuperRegs.push_back(this);
138 // Add ad hoc alias links. This is a symmetric relationship between two
139 // registers, so build a symmetric graph by adding links in both ends.
140 std::vector<Record*> Aliases = TheDef->getValueAsListOfDefs("Aliases");
141 for (unsigned i = 0, e = Aliases.size(); i != e; ++i) {
142 CodeGenRegister *Reg = RegBank.getReg(Aliases[i]);
143 ExplicitAliases.push_back(Reg);
144 Reg->ExplicitAliases.push_back(this);
148 const std::string &CodeGenRegister::getName() const {
149 assert(TheDef && "no def");
150 return TheDef->getName();
154 // Iterate over all register units in a set of registers.
155 class RegUnitIterator {
156 CodeGenRegister::Vec::const_iterator RegI, RegE;
157 CodeGenRegister::RegUnitList::iterator UnitI, UnitE;
160 RegUnitIterator(const CodeGenRegister::Vec &Regs):
161 RegI(Regs.begin()), RegE(Regs.end()), UnitI(), UnitE() {
164 UnitI = (*RegI)->getRegUnits().begin();
165 UnitE = (*RegI)->getRegUnits().end();
170 bool isValid() const { return UnitI != UnitE; }
172 unsigned operator* () const { assert(isValid()); return *UnitI; }
174 const CodeGenRegister *getReg() const { assert(isValid()); return *RegI; }
176 /// Preincrement. Move to the next unit.
178 assert(isValid() && "Cannot advance beyond the last operand");
185 while (UnitI == UnitE) {
188 UnitI = (*RegI)->getRegUnits().begin();
189 UnitE = (*RegI)->getRegUnits().end();
195 // Return true of this unit appears in RegUnits.
196 static bool hasRegUnit(CodeGenRegister::RegUnitList &RegUnits, unsigned Unit) {
197 return RegUnits.test(Unit);
200 // Inherit register units from subregisters.
201 // Return true if the RegUnits changed.
202 bool CodeGenRegister::inheritRegUnits(CodeGenRegBank &RegBank) {
203 bool changed = false;
204 for (SubRegMap::const_iterator I = SubRegs.begin(), E = SubRegs.end();
206 CodeGenRegister *SR = I->second;
207 // Merge the subregister's units into this register's RegUnits.
208 changed |= (RegUnits |= SR->RegUnits);
214 const CodeGenRegister::SubRegMap &
215 CodeGenRegister::computeSubRegs(CodeGenRegBank &RegBank) {
216 // Only compute this map once.
219 SubRegsComplete = true;
221 HasDisjunctSubRegs = ExplicitSubRegs.size() > 1;
223 // First insert the explicit subregs and make sure they are fully indexed.
224 for (unsigned i = 0, e = ExplicitSubRegs.size(); i != e; ++i) {
225 CodeGenRegister *SR = ExplicitSubRegs[i];
226 CodeGenSubRegIndex *Idx = ExplicitSubRegIndices[i];
227 if (!SubRegs.insert(std::make_pair(Idx, SR)).second)
228 PrintFatalError(TheDef->getLoc(), "SubRegIndex " + Idx->getName() +
229 " appears twice in Register " + getName());
230 // Map explicit sub-registers first, so the names take precedence.
231 // The inherited sub-registers are mapped below.
232 SubReg2Idx.insert(std::make_pair(SR, Idx));
235 // Keep track of inherited subregs and how they can be reached.
236 SmallPtrSet<CodeGenRegister*, 8> Orphans;
238 // Clone inherited subregs and place duplicate entries in Orphans.
239 // Here the order is important - earlier subregs take precedence.
240 for (unsigned i = 0, e = ExplicitSubRegs.size(); i != e; ++i) {
241 CodeGenRegister *SR = ExplicitSubRegs[i];
242 const SubRegMap &Map = SR->computeSubRegs(RegBank);
243 HasDisjunctSubRegs |= SR->HasDisjunctSubRegs;
245 for (SubRegMap::const_iterator SI = Map.begin(), SE = Map.end(); SI != SE;
247 if (!SubRegs.insert(*SI).second)
248 Orphans.insert(SI->second);
252 // Expand any composed subreg indices.
253 // If dsub_2 has ComposedOf = [qsub_1, dsub_0], and this register has a
254 // qsub_1 subreg, add a dsub_2 subreg. Keep growing Indices and process
255 // expanded subreg indices recursively.
256 SmallVector<CodeGenSubRegIndex*, 8> Indices = ExplicitSubRegIndices;
257 for (unsigned i = 0; i != Indices.size(); ++i) {
258 CodeGenSubRegIndex *Idx = Indices[i];
259 const CodeGenSubRegIndex::CompMap &Comps = Idx->getComposites();
260 CodeGenRegister *SR = SubRegs[Idx];
261 const SubRegMap &Map = SR->computeSubRegs(RegBank);
263 // Look at the possible compositions of Idx.
264 // They may not all be supported by SR.
265 for (CodeGenSubRegIndex::CompMap::const_iterator I = Comps.begin(),
266 E = Comps.end(); I != E; ++I) {
267 SubRegMap::const_iterator SRI = Map.find(I->first);
268 if (SRI == Map.end())
269 continue; // Idx + I->first doesn't exist in SR.
270 // Add I->second as a name for the subreg SRI->second, assuming it is
271 // orphaned, and the name isn't already used for something else.
272 if (SubRegs.count(I->second) || !Orphans.erase(SRI->second))
274 // We found a new name for the orphaned sub-register.
275 SubRegs.insert(std::make_pair(I->second, SRI->second));
276 Indices.push_back(I->second);
280 // Now Orphans contains the inherited subregisters without a direct index.
281 // Create inferred indexes for all missing entries.
282 // Work backwards in the Indices vector in order to compose subregs bottom-up.
283 // Consider this subreg sequence:
285 // qsub_1 -> dsub_0 -> ssub_0
287 // The qsub_1 -> dsub_0 composition becomes dsub_2, so the ssub_0 register
288 // can be reached in two different ways:
293 // We pick the latter composition because another register may have [dsub_0,
294 // dsub_1, dsub_2] subregs without necessarily having a qsub_1 subreg. The
295 // dsub_2 -> ssub_0 composition can be shared.
296 while (!Indices.empty() && !Orphans.empty()) {
297 CodeGenSubRegIndex *Idx = Indices.pop_back_val();
298 CodeGenRegister *SR = SubRegs[Idx];
299 const SubRegMap &Map = SR->computeSubRegs(RegBank);
300 for (SubRegMap::const_iterator SI = Map.begin(), SE = Map.end(); SI != SE;
302 if (Orphans.erase(SI->second))
303 SubRegs[RegBank.getCompositeSubRegIndex(Idx, SI->first)] = SI->second;
306 // Compute the inverse SubReg -> Idx map.
307 for (SubRegMap::const_iterator SI = SubRegs.begin(), SE = SubRegs.end();
309 if (SI->second == this) {
312 Loc = TheDef->getLoc();
313 PrintFatalError(Loc, "Register " + getName() +
314 " has itself as a sub-register");
317 // Compute AllSuperRegsCovered.
318 if (!CoveredBySubRegs)
319 SI->first->AllSuperRegsCovered = false;
321 // Ensure that every sub-register has a unique name.
322 DenseMap<const CodeGenRegister*, CodeGenSubRegIndex*>::iterator Ins =
323 SubReg2Idx.insert(std::make_pair(SI->second, SI->first)).first;
324 if (Ins->second == SI->first)
326 // Trouble: Two different names for SI->second.
329 Loc = TheDef->getLoc();
330 PrintFatalError(Loc, "Sub-register can't have two names: " +
331 SI->second->getName() + " available as " +
332 SI->first->getName() + " and " + Ins->second->getName());
335 // Derive possible names for sub-register concatenations from any explicit
336 // sub-registers. By doing this before computeSecondarySubRegs(), we ensure
337 // that getConcatSubRegIndex() won't invent any concatenated indices that the
338 // user already specified.
339 for (unsigned i = 0, e = ExplicitSubRegs.size(); i != e; ++i) {
340 CodeGenRegister *SR = ExplicitSubRegs[i];
341 if (!SR->CoveredBySubRegs || SR->ExplicitSubRegs.size() <= 1)
344 // SR is composed of multiple sub-regs. Find their names in this register.
345 SmallVector<CodeGenSubRegIndex*, 8> Parts;
346 for (unsigned j = 0, e = SR->ExplicitSubRegs.size(); j != e; ++j)
347 Parts.push_back(getSubRegIndex(SR->ExplicitSubRegs[j]));
349 // Offer this as an existing spelling for the concatenation of Parts.
350 RegBank.addConcatSubRegIndex(Parts, ExplicitSubRegIndices[i]);
353 // Initialize RegUnitList. Because getSubRegs is called recursively, this
354 // processes the register hierarchy in postorder.
356 // Inherit all sub-register units. It is good enough to look at the explicit
357 // sub-registers, the other registers won't contribute any more units.
358 for (unsigned i = 0, e = ExplicitSubRegs.size(); i != e; ++i) {
359 CodeGenRegister *SR = ExplicitSubRegs[i];
360 RegUnits |= SR->RegUnits;
363 // Absent any ad hoc aliasing, we create one register unit per leaf register.
364 // These units correspond to the maximal cliques in the register overlap
365 // graph which is optimal.
367 // When there is ad hoc aliasing, we simply create one unit per edge in the
368 // undirected ad hoc aliasing graph. Technically, we could do better by
369 // identifying maximal cliques in the ad hoc graph, but cliques larger than 2
370 // are extremely rare anyway (I've never seen one), so we don't bother with
371 // the added complexity.
372 for (unsigned i = 0, e = ExplicitAliases.size(); i != e; ++i) {
373 CodeGenRegister *AR = ExplicitAliases[i];
374 // Only visit each edge once.
375 if (AR->SubRegsComplete)
377 // Create a RegUnit representing this alias edge, and add it to both
379 unsigned Unit = RegBank.newRegUnit(this, AR);
381 AR->RegUnits.set(Unit);
384 // Finally, create units for leaf registers without ad hoc aliases. Note that
385 // a leaf register with ad hoc aliases doesn't get its own unit - it isn't
386 // necessary. This means the aliasing leaf registers can share a single unit.
387 if (RegUnits.empty())
388 RegUnits.set(RegBank.newRegUnit(this));
390 // We have now computed the native register units. More may be adopted later
391 // for balancing purposes.
392 NativeRegUnits = RegUnits;
397 // In a register that is covered by its sub-registers, try to find redundant
398 // sub-registers. For example:
404 // We can infer that D1_D2 is also a sub-register, even if it wasn't named in
405 // the register definition.
407 // The explicitly specified registers form a tree. This function discovers
408 // sub-register relationships that would force a DAG.
410 void CodeGenRegister::computeSecondarySubRegs(CodeGenRegBank &RegBank) {
411 // Collect new sub-registers first, add them later.
412 SmallVector<SubRegMap::value_type, 8> NewSubRegs;
414 // Look at the leading super-registers of each sub-register. Those are the
415 // candidates for new sub-registers, assuming they are fully contained in
417 for (SubRegMap::iterator I = SubRegs.begin(), E = SubRegs.end(); I != E; ++I){
418 const CodeGenRegister *SubReg = I->second;
419 const CodeGenRegister::SuperRegList &Leads = SubReg->LeadingSuperRegs;
420 for (unsigned i = 0, e = Leads.size(); i != e; ++i) {
421 CodeGenRegister *Cand = const_cast<CodeGenRegister*>(Leads[i]);
422 // Already got this sub-register?
423 if (Cand == this || getSubRegIndex(Cand))
425 // Check if each component of Cand is already a sub-register.
426 // We know that the first component is I->second, and is present with the
428 SmallVector<CodeGenSubRegIndex*, 8> Parts(1, I->first);
429 assert(!Cand->ExplicitSubRegs.empty() &&
430 "Super-register has no sub-registers");
431 for (unsigned j = 1, e = Cand->ExplicitSubRegs.size(); j != e; ++j) {
432 if (CodeGenSubRegIndex *Idx = getSubRegIndex(Cand->ExplicitSubRegs[j]))
433 Parts.push_back(Idx);
435 // Sub-register doesn't exist.
440 // If some Cand sub-register is not part of this register, or if Cand only
441 // has one sub-register, there is nothing to do.
442 if (Parts.size() <= 1)
445 // Each part of Cand is a sub-register of this. Make the full Cand also
446 // a sub-register with a concatenated sub-register index.
447 CodeGenSubRegIndex *Concat= RegBank.getConcatSubRegIndex(Parts);
448 NewSubRegs.push_back(std::make_pair(Concat, Cand));
452 // Now add all the new sub-registers.
453 for (unsigned i = 0, e = NewSubRegs.size(); i != e; ++i) {
454 // Don't add Cand if another sub-register is already using the index.
455 if (!SubRegs.insert(NewSubRegs[i]).second)
458 CodeGenSubRegIndex *NewIdx = NewSubRegs[i].first;
459 CodeGenRegister *NewSubReg = NewSubRegs[i].second;
460 SubReg2Idx.insert(std::make_pair(NewSubReg, NewIdx));
463 // Create sub-register index composition maps for the synthesized indices.
464 for (unsigned i = 0, e = NewSubRegs.size(); i != e; ++i) {
465 CodeGenSubRegIndex *NewIdx = NewSubRegs[i].first;
466 CodeGenRegister *NewSubReg = NewSubRegs[i].second;
467 for (SubRegMap::const_iterator SI = NewSubReg->SubRegs.begin(),
468 SE = NewSubReg->SubRegs.end(); SI != SE; ++SI) {
469 CodeGenSubRegIndex *SubIdx = getSubRegIndex(SI->second);
471 PrintFatalError(TheDef->getLoc(), "No SubRegIndex for " +
472 SI->second->getName() + " in " + getName());
473 NewIdx->addComposite(SI->first, SubIdx);
478 void CodeGenRegister::computeSuperRegs(CodeGenRegBank &RegBank) {
479 // Only visit each register once.
480 if (SuperRegsComplete)
482 SuperRegsComplete = true;
484 // Make sure all sub-registers have been visited first, so the super-reg
485 // lists will be topologically ordered.
486 for (SubRegMap::const_iterator I = SubRegs.begin(), E = SubRegs.end();
488 I->second->computeSuperRegs(RegBank);
490 // Now add this as a super-register on all sub-registers.
491 // Also compute the TopoSigId in post-order.
493 for (SubRegMap::const_iterator I = SubRegs.begin(), E = SubRegs.end();
495 // Topological signature computed from SubIdx, TopoId(SubReg).
496 // Loops and idempotent indices have TopoSig = ~0u.
497 Id.push_back(I->first->EnumValue);
498 Id.push_back(I->second->TopoSig);
500 // Don't add duplicate entries.
501 if (!I->second->SuperRegs.empty() && I->second->SuperRegs.back() == this)
503 I->second->SuperRegs.push_back(this);
505 TopoSig = RegBank.getTopoSig(Id);
509 CodeGenRegister::addSubRegsPreOrder(SetVector<const CodeGenRegister*> &OSet,
510 CodeGenRegBank &RegBank) const {
511 assert(SubRegsComplete && "Must precompute sub-registers");
512 for (unsigned i = 0, e = ExplicitSubRegs.size(); i != e; ++i) {
513 CodeGenRegister *SR = ExplicitSubRegs[i];
515 SR->addSubRegsPreOrder(OSet, RegBank);
517 // Add any secondary sub-registers that weren't part of the explicit tree.
518 for (SubRegMap::const_iterator I = SubRegs.begin(), E = SubRegs.end();
520 OSet.insert(I->second);
523 // Get the sum of this register's unit weights.
524 unsigned CodeGenRegister::getWeight(const CodeGenRegBank &RegBank) const {
526 for (RegUnitList::iterator I = RegUnits.begin(), E = RegUnits.end();
528 Weight += RegBank.getRegUnit(*I).Weight;
533 //===----------------------------------------------------------------------===//
535 //===----------------------------------------------------------------------===//
537 // A RegisterTuples def is used to generate pseudo-registers from lists of
538 // sub-registers. We provide a SetTheory expander class that returns the new
541 struct TupleExpander : SetTheory::Expander {
542 void expand(SetTheory &ST, Record *Def, SetTheory::RecSet &Elts) override {
543 std::vector<Record*> Indices = Def->getValueAsListOfDefs("SubRegIndices");
544 unsigned Dim = Indices.size();
545 ListInit *SubRegs = Def->getValueAsListInit("SubRegs");
546 if (Dim != SubRegs->getSize())
547 PrintFatalError(Def->getLoc(), "SubRegIndices and SubRegs size mismatch");
549 PrintFatalError(Def->getLoc(),
550 "Tuples must have at least 2 sub-registers");
552 // Evaluate the sub-register lists to be zipped.
553 unsigned Length = ~0u;
554 SmallVector<SetTheory::RecSet, 4> Lists(Dim);
555 for (unsigned i = 0; i != Dim; ++i) {
556 ST.evaluate(SubRegs->getElement(i), Lists[i], Def->getLoc());
557 Length = std::min(Length, unsigned(Lists[i].size()));
563 // Precompute some types.
564 Record *RegisterCl = Def->getRecords().getClass("Register");
565 RecTy *RegisterRecTy = RecordRecTy::get(RegisterCl);
566 StringInit *BlankName = StringInit::get("");
569 for (unsigned n = 0; n != Length; ++n) {
571 Record *Proto = Lists[0][n];
572 std::vector<Init*> Tuple;
573 unsigned CostPerUse = 0;
574 for (unsigned i = 0; i != Dim; ++i) {
575 Record *Reg = Lists[i][n];
577 Name += Reg->getName();
578 Tuple.push_back(DefInit::get(Reg));
579 CostPerUse = std::max(CostPerUse,
580 unsigned(Reg->getValueAsInt("CostPerUse")));
583 // Create a new Record representing the synthesized register. This record
584 // is only for consumption by CodeGenRegister, it is not added to the
586 Record *NewReg = new Record(Name, Def->getLoc(), Def->getRecords());
589 // Copy Proto super-classes.
590 ArrayRef<Record *> Supers = Proto->getSuperClasses();
591 ArrayRef<SMRange> Ranges = Proto->getSuperClassRanges();
592 for (unsigned i = 0, e = Supers.size(); i != e; ++i)
593 NewReg->addSuperClass(Supers[i], Ranges[i]);
595 // Copy Proto fields.
596 for (unsigned i = 0, e = Proto->getValues().size(); i != e; ++i) {
597 RecordVal RV = Proto->getValues()[i];
599 // Skip existing fields, like NAME.
600 if (NewReg->getValue(RV.getNameInit()))
603 StringRef Field = RV.getName();
605 // Replace the sub-register list with Tuple.
606 if (Field == "SubRegs")
607 RV.setValue(ListInit::get(Tuple, RegisterRecTy));
609 // Provide a blank AsmName. MC hacks are required anyway.
610 if (Field == "AsmName")
611 RV.setValue(BlankName);
613 // CostPerUse is aggregated from all Tuple members.
614 if (Field == "CostPerUse")
615 RV.setValue(IntInit::get(CostPerUse));
617 // Composite registers are always covered by sub-registers.
618 if (Field == "CoveredBySubRegs")
619 RV.setValue(BitInit::get(true));
621 // Copy fields from the RegisterTuples def.
622 if (Field == "SubRegIndices" ||
623 Field == "CompositeIndices") {
624 NewReg->addValue(*Def->getValue(Field));
628 // Some fields get their default uninitialized value.
629 if (Field == "DwarfNumbers" ||
630 Field == "DwarfAlias" ||
631 Field == "Aliases") {
632 if (const RecordVal *DefRV = RegisterCl->getValue(Field))
633 NewReg->addValue(*DefRV);
637 // Everything else is copied from Proto.
638 NewReg->addValue(RV);
645 //===----------------------------------------------------------------------===//
646 // CodeGenRegisterClass
647 //===----------------------------------------------------------------------===//
649 static void sortAndUniqueRegisters(CodeGenRegister::Vec &M) {
650 std::sort(M.begin(), M.end(), deref<llvm::less>());
651 M.erase(std::unique(M.begin(), M.end(), deref<llvm::equal>()), M.end());
654 CodeGenRegisterClass::CodeGenRegisterClass(CodeGenRegBank &RegBank, Record *R)
657 TopoSigs(RegBank.getNumTopoSigs()),
660 // Rename anonymous register classes.
661 if (R->getName().size() > 9 && R->getName()[9] == '.') {
662 static unsigned AnonCounter = 0;
663 R->setName("AnonRegClass_" + utostr(AnonCounter++));
666 std::vector<Record*> TypeList = R->getValueAsListOfDefs("RegTypes");
667 for (unsigned i = 0, e = TypeList.size(); i != e; ++i) {
668 Record *Type = TypeList[i];
669 if (!Type->isSubClassOf("ValueType"))
670 PrintFatalError("RegTypes list member '" + Type->getName() +
671 "' does not derive from the ValueType class!");
672 VTs.push_back(getValueType(Type));
674 assert(!VTs.empty() && "RegisterClass must contain at least one ValueType!");
676 // Allocation order 0 is the full set. AltOrders provides others.
677 const SetTheory::RecVec *Elements = RegBank.getSets().expand(R);
678 ListInit *AltOrders = R->getValueAsListInit("AltOrders");
679 Orders.resize(1 + AltOrders->size());
681 // Default allocation order always contains all registers.
682 for (unsigned i = 0, e = Elements->size(); i != e; ++i) {
683 Orders[0].push_back((*Elements)[i]);
684 const CodeGenRegister *Reg = RegBank.getReg((*Elements)[i]);
685 Members.push_back(Reg);
686 TopoSigs.set(Reg->getTopoSig());
688 sortAndUniqueRegisters(Members);
690 // Alternative allocation orders may be subsets.
691 SetTheory::RecSet Order;
692 for (unsigned i = 0, e = AltOrders->size(); i != e; ++i) {
693 RegBank.getSets().evaluate(AltOrders->getElement(i), Order, R->getLoc());
694 Orders[1 + i].append(Order.begin(), Order.end());
695 // Verify that all altorder members are regclass members.
696 while (!Order.empty()) {
697 CodeGenRegister *Reg = RegBank.getReg(Order.back());
700 PrintFatalError(R->getLoc(), " AltOrder register " + Reg->getName() +
701 " is not a class member");
705 // Allow targets to override the size in bits of the RegisterClass.
706 unsigned Size = R->getValueAsInt("Size");
708 Namespace = R->getValueAsString("Namespace");
709 SpillSize = Size ? Size : MVT(VTs[0]).getSizeInBits();
710 SpillAlignment = R->getValueAsInt("Alignment");
711 CopyCost = R->getValueAsInt("CopyCost");
712 Allocatable = R->getValueAsBit("isAllocatable");
713 AltOrderSelect = R->getValueAsString("AltOrderSelect");
716 // Create an inferred register class that was missing from the .td files.
717 // Most properties will be inherited from the closest super-class after the
718 // class structure has been computed.
719 CodeGenRegisterClass::CodeGenRegisterClass(CodeGenRegBank &RegBank,
720 StringRef Name, Key Props)
721 : Members(*Props.Members),
724 TopoSigs(RegBank.getNumTopoSigs()),
726 SpillSize(Props.SpillSize),
727 SpillAlignment(Props.SpillAlignment),
730 for (const auto R : Members)
731 TopoSigs.set(R->getTopoSig());
734 // Compute inherited propertied for a synthesized register class.
735 void CodeGenRegisterClass::inheritProperties(CodeGenRegBank &RegBank) {
736 assert(!getDef() && "Only synthesized classes can inherit properties");
737 assert(!SuperClasses.empty() && "Synthesized class without super class");
739 // The last super-class is the smallest one.
740 CodeGenRegisterClass &Super = *SuperClasses.back();
742 // Most properties are copied directly.
743 // Exceptions are members, size, and alignment
744 Namespace = Super.Namespace;
746 CopyCost = Super.CopyCost;
747 Allocatable = Super.Allocatable;
748 AltOrderSelect = Super.AltOrderSelect;
750 // Copy all allocation orders, filter out foreign registers from the larger
752 Orders.resize(Super.Orders.size());
753 for (unsigned i = 0, ie = Super.Orders.size(); i != ie; ++i)
754 for (unsigned j = 0, je = Super.Orders[i].size(); j != je; ++j)
755 if (contains(RegBank.getReg(Super.Orders[i][j])))
756 Orders[i].push_back(Super.Orders[i][j]);
759 bool CodeGenRegisterClass::contains(const CodeGenRegister *Reg) const {
760 return std::binary_search(Members.begin(), Members.end(), Reg,
761 deref<llvm::less>());
765 raw_ostream &operator<<(raw_ostream &OS, const CodeGenRegisterClass::Key &K) {
766 OS << "{ S=" << K.SpillSize << ", A=" << K.SpillAlignment;
767 for (const auto R : *K.Members)
768 OS << ", " << R->getName();
773 // This is a simple lexicographical order that can be used to search for sets.
774 // It is not the same as the topological order provided by TopoOrderRC.
775 bool CodeGenRegisterClass::Key::
776 operator<(const CodeGenRegisterClass::Key &B) const {
777 assert(Members && B.Members);
778 return std::tie(*Members, SpillSize, SpillAlignment) <
779 std::tie(*B.Members, B.SpillSize, B.SpillAlignment);
782 // Returns true if RC is a strict subclass.
783 // RC is a sub-class of this class if it is a valid replacement for any
784 // instruction operand where a register of this classis required. It must
785 // satisfy these conditions:
787 // 1. All RC registers are also in this.
788 // 2. The RC spill size must not be smaller than our spill size.
789 // 3. RC spill alignment must be compatible with ours.
791 static bool testSubClass(const CodeGenRegisterClass *A,
792 const CodeGenRegisterClass *B) {
793 return A->SpillAlignment && B->SpillAlignment % A->SpillAlignment == 0 &&
794 A->SpillSize <= B->SpillSize &&
795 std::includes(A->getMembers().begin(), A->getMembers().end(),
796 B->getMembers().begin(), B->getMembers().end(),
797 deref<llvm::less>());
800 /// Sorting predicate for register classes. This provides a topological
801 /// ordering that arranges all register classes before their sub-classes.
803 /// Register classes with the same registers, spill size, and alignment form a
804 /// clique. They will be ordered alphabetically.
806 static bool TopoOrderRC(const CodeGenRegisterClass &PA,
807 const CodeGenRegisterClass &PB) {
813 // Order by ascending spill size.
814 if (A->SpillSize < B->SpillSize)
816 if (A->SpillSize > B->SpillSize)
819 // Order by ascending spill alignment.
820 if (A->SpillAlignment < B->SpillAlignment)
822 if (A->SpillAlignment > B->SpillAlignment)
825 // Order by descending set size. Note that the classes' allocation order may
826 // not have been computed yet. The Members set is always vaild.
827 if (A->getMembers().size() > B->getMembers().size())
829 if (A->getMembers().size() < B->getMembers().size())
832 // Finally order by name as a tie breaker.
833 return StringRef(A->getName()) < B->getName();
836 std::string CodeGenRegisterClass::getQualifiedName() const {
837 if (Namespace.empty())
840 return Namespace + "::" + getName();
843 // Compute sub-classes of all register classes.
844 // Assume the classes are ordered topologically.
845 void CodeGenRegisterClass::computeSubClasses(CodeGenRegBank &RegBank) {
846 auto &RegClasses = RegBank.getRegClasses();
848 // Visit backwards so sub-classes are seen first.
849 for (auto I = RegClasses.rbegin(), E = RegClasses.rend(); I != E; ++I) {
850 CodeGenRegisterClass &RC = *I;
851 RC.SubClasses.resize(RegClasses.size());
852 RC.SubClasses.set(RC.EnumValue);
854 // Normally, all subclasses have IDs >= rci, unless RC is part of a clique.
855 for (auto I2 = I.base(), E2 = RegClasses.end(); I2 != E2; ++I2) {
856 CodeGenRegisterClass &SubRC = *I2;
857 if (RC.SubClasses.test(SubRC.EnumValue))
859 if (!testSubClass(&RC, &SubRC))
861 // SubRC is a sub-class. Grap all its sub-classes so we won't have to
863 RC.SubClasses |= SubRC.SubClasses;
866 // Sweep up missed clique members. They will be immediately preceding RC.
867 for (auto I2 = std::next(I); I2 != E && testSubClass(&RC, &*I2); ++I2)
868 RC.SubClasses.set(I2->EnumValue);
871 // Compute the SuperClasses lists from the SubClasses vectors.
872 for (auto &RC : RegClasses) {
873 const BitVector &SC = RC.getSubClasses();
874 auto I = RegClasses.begin();
875 for (int s = 0, next_s = SC.find_first(); next_s != -1;
876 next_s = SC.find_next(s)) {
877 std::advance(I, next_s - s);
881 I->SuperClasses.push_back(&RC);
885 // With the class hierarchy in place, let synthesized register classes inherit
886 // properties from their closest super-class. The iteration order here can
887 // propagate properties down multiple levels.
888 for (auto &RC : RegClasses)
890 RC.inheritProperties(RegBank);
893 void CodeGenRegisterClass::getSuperRegClasses(const CodeGenSubRegIndex *SubIdx,
894 BitVector &Out) const {
895 auto FindI = SuperRegClasses.find(SubIdx);
896 if (FindI == SuperRegClasses.end())
898 for (CodeGenRegisterClass *RC : FindI->second)
899 Out.set(RC->EnumValue);
902 // Populate a unique sorted list of units from a register set.
903 void CodeGenRegisterClass::buildRegUnitSet(
904 std::vector<unsigned> &RegUnits) const {
905 std::vector<unsigned> TmpUnits;
906 for (RegUnitIterator UnitI(Members); UnitI.isValid(); ++UnitI)
907 TmpUnits.push_back(*UnitI);
908 std::sort(TmpUnits.begin(), TmpUnits.end());
909 std::unique_copy(TmpUnits.begin(), TmpUnits.end(),
910 std::back_inserter(RegUnits));
913 //===----------------------------------------------------------------------===//
915 //===----------------------------------------------------------------------===//
917 CodeGenRegBank::CodeGenRegBank(RecordKeeper &Records) {
918 // Configure register Sets to understand register classes and tuples.
919 Sets.addFieldExpander("RegisterClass", "MemberList");
920 Sets.addFieldExpander("CalleeSavedRegs", "SaveList");
921 Sets.addExpander("RegisterTuples", new TupleExpander());
923 // Read in the user-defined (named) sub-register indices.
924 // More indices will be synthesized later.
925 std::vector<Record*> SRIs = Records.getAllDerivedDefinitions("SubRegIndex");
926 std::sort(SRIs.begin(), SRIs.end(), LessRecord());
927 for (unsigned i = 0, e = SRIs.size(); i != e; ++i)
928 getSubRegIdx(SRIs[i]);
929 // Build composite maps from ComposedOf fields.
930 for (auto &Idx : SubRegIndices)
931 Idx.updateComponents(*this);
933 // Read in the register definitions.
934 std::vector<Record*> Regs = Records.getAllDerivedDefinitions("Register");
935 std::sort(Regs.begin(), Regs.end(), LessRecordRegister());
936 // Assign the enumeration values.
937 for (unsigned i = 0, e = Regs.size(); i != e; ++i)
940 // Expand tuples and number the new registers.
941 std::vector<Record*> Tups =
942 Records.getAllDerivedDefinitions("RegisterTuples");
944 for (Record *R : Tups) {
945 std::vector<Record *> TupRegs = *Sets.expand(R);
946 std::sort(TupRegs.begin(), TupRegs.end(), LessRecordRegister());
947 for (Record *RC : TupRegs)
951 // Now all the registers are known. Build the object graph of explicit
952 // register-register references.
953 for (auto &Reg : Registers)
954 Reg.buildObjectGraph(*this);
956 // Compute register name map.
957 for (auto &Reg : Registers)
958 // FIXME: This could just be RegistersByName[name] = register, except that
959 // causes some failures in MIPS - perhaps they have duplicate register name
960 // entries? (or maybe there's a reason for it - I don't know much about this
961 // code, just drive-by refactoring)
962 RegistersByName.insert(
963 std::make_pair(Reg.TheDef->getValueAsString("AsmName"), &Reg));
965 // Precompute all sub-register maps.
966 // This will create Composite entries for all inferred sub-register indices.
967 for (auto &Reg : Registers)
968 Reg.computeSubRegs(*this);
970 // Infer even more sub-registers by combining leading super-registers.
971 for (auto &Reg : Registers)
972 if (Reg.CoveredBySubRegs)
973 Reg.computeSecondarySubRegs(*this);
975 // After the sub-register graph is complete, compute the topologically
976 // ordered SuperRegs list.
977 for (auto &Reg : Registers)
978 Reg.computeSuperRegs(*this);
980 // Native register units are associated with a leaf register. They've all been
982 NumNativeRegUnits = RegUnits.size();
984 // Read in register class definitions.
985 std::vector<Record*> RCs = Records.getAllDerivedDefinitions("RegisterClass");
987 PrintFatalError("No 'RegisterClass' subclasses defined!");
989 // Allocate user-defined register classes.
990 for (auto *RC : RCs) {
991 RegClasses.push_back(CodeGenRegisterClass(*this, RC));
992 addToMaps(&RegClasses.back());
995 // Infer missing classes to create a full algebra.
996 computeInferredRegisterClasses();
998 // Order register classes topologically and assign enum values.
999 RegClasses.sort(TopoOrderRC);
1001 for (auto &RC : RegClasses)
1003 CodeGenRegisterClass::computeSubClasses(*this);
1006 // Create a synthetic CodeGenSubRegIndex without a corresponding Record.
1008 CodeGenRegBank::createSubRegIndex(StringRef Name, StringRef Namespace) {
1009 SubRegIndices.emplace_back(Name, Namespace, SubRegIndices.size() + 1);
1010 return &SubRegIndices.back();
1013 CodeGenSubRegIndex *CodeGenRegBank::getSubRegIdx(Record *Def) {
1014 CodeGenSubRegIndex *&Idx = Def2SubRegIdx[Def];
1017 SubRegIndices.emplace_back(Def, SubRegIndices.size() + 1);
1018 Idx = &SubRegIndices.back();
1022 CodeGenRegister *CodeGenRegBank::getReg(Record *Def) {
1023 CodeGenRegister *&Reg = Def2Reg[Def];
1026 Registers.emplace_back(Def, Registers.size() + 1);
1027 Reg = &Registers.back();
1031 void CodeGenRegBank::addToMaps(CodeGenRegisterClass *RC) {
1032 if (Record *Def = RC->getDef())
1033 Def2RC.insert(std::make_pair(Def, RC));
1035 // Duplicate classes are rejected by insert().
1036 // That's OK, we only care about the properties handled by CGRC::Key.
1037 CodeGenRegisterClass::Key K(*RC);
1038 Key2RC.insert(std::make_pair(K, RC));
1041 // Create a synthetic sub-class if it is missing.
1042 CodeGenRegisterClass*
1043 CodeGenRegBank::getOrCreateSubClass(const CodeGenRegisterClass *RC,
1044 const CodeGenRegister::Vec *Members,
1046 // Synthetic sub-class has the same size and alignment as RC.
1047 CodeGenRegisterClass::Key K(Members, RC->SpillSize, RC->SpillAlignment);
1048 RCKeyMap::const_iterator FoundI = Key2RC.find(K);
1049 if (FoundI != Key2RC.end())
1050 return FoundI->second;
1052 // Sub-class doesn't exist, create a new one.
1053 RegClasses.push_back(CodeGenRegisterClass(*this, Name, K));
1054 addToMaps(&RegClasses.back());
1055 return &RegClasses.back();
1058 CodeGenRegisterClass *CodeGenRegBank::getRegClass(Record *Def) {
1059 if (CodeGenRegisterClass *RC = Def2RC[Def])
1062 PrintFatalError(Def->getLoc(), "Not a known RegisterClass!");
1066 CodeGenRegBank::getCompositeSubRegIndex(CodeGenSubRegIndex *A,
1067 CodeGenSubRegIndex *B) {
1068 // Look for an existing entry.
1069 CodeGenSubRegIndex *Comp = A->compose(B);
1073 // None exists, synthesize one.
1074 std::string Name = A->getName() + "_then_" + B->getName();
1075 Comp = createSubRegIndex(Name, A->getNamespace());
1076 A->addComposite(B, Comp);
1080 CodeGenSubRegIndex *CodeGenRegBank::
1081 getConcatSubRegIndex(const SmallVector<CodeGenSubRegIndex *, 8> &Parts) {
1082 assert(Parts.size() > 1 && "Need two parts to concatenate");
1084 // Look for an existing entry.
1085 CodeGenSubRegIndex *&Idx = ConcatIdx[Parts];
1089 // None exists, synthesize one.
1090 std::string Name = Parts.front()->getName();
1091 // Determine whether all parts are contiguous.
1092 bool isContinuous = true;
1093 unsigned Size = Parts.front()->Size;
1094 unsigned LastOffset = Parts.front()->Offset;
1095 unsigned LastSize = Parts.front()->Size;
1096 for (unsigned i = 1, e = Parts.size(); i != e; ++i) {
1098 Name += Parts[i]->getName();
1099 Size += Parts[i]->Size;
1100 if (Parts[i]->Offset != (LastOffset + LastSize))
1101 isContinuous = false;
1102 LastOffset = Parts[i]->Offset;
1103 LastSize = Parts[i]->Size;
1105 Idx = createSubRegIndex(Name, Parts.front()->getNamespace());
1107 Idx->Offset = isContinuous ? Parts.front()->Offset : -1;
1111 void CodeGenRegBank::computeComposites() {
1112 // Keep track of TopoSigs visited. We only need to visit each TopoSig once,
1113 // and many registers will share TopoSigs on regular architectures.
1114 BitVector TopoSigs(getNumTopoSigs());
1116 for (const auto &Reg1 : Registers) {
1117 // Skip identical subreg structures already processed.
1118 if (TopoSigs.test(Reg1.getTopoSig()))
1120 TopoSigs.set(Reg1.getTopoSig());
1122 const CodeGenRegister::SubRegMap &SRM1 = Reg1.getSubRegs();
1123 for (CodeGenRegister::SubRegMap::const_iterator i1 = SRM1.begin(),
1124 e1 = SRM1.end(); i1 != e1; ++i1) {
1125 CodeGenSubRegIndex *Idx1 = i1->first;
1126 CodeGenRegister *Reg2 = i1->second;
1127 // Ignore identity compositions.
1130 const CodeGenRegister::SubRegMap &SRM2 = Reg2->getSubRegs();
1131 // Try composing Idx1 with another SubRegIndex.
1132 for (CodeGenRegister::SubRegMap::const_iterator i2 = SRM2.begin(),
1133 e2 = SRM2.end(); i2 != e2; ++i2) {
1134 CodeGenSubRegIndex *Idx2 = i2->first;
1135 CodeGenRegister *Reg3 = i2->second;
1136 // Ignore identity compositions.
1139 // OK Reg1:IdxPair == Reg3. Find the index with Reg:Idx == Reg3.
1140 CodeGenSubRegIndex *Idx3 = Reg1.getSubRegIndex(Reg3);
1141 assert(Idx3 && "Sub-register doesn't have an index");
1143 // Conflicting composition? Emit a warning but allow it.
1144 if (CodeGenSubRegIndex *Prev = Idx1->addComposite(Idx2, Idx3))
1145 PrintWarning(Twine("SubRegIndex ") + Idx1->getQualifiedName() +
1146 " and " + Idx2->getQualifiedName() +
1147 " compose ambiguously as " + Prev->getQualifiedName() +
1148 " or " + Idx3->getQualifiedName());
1154 // Compute lane masks. This is similar to register units, but at the
1155 // sub-register index level. Each bit in the lane mask is like a register unit
1156 // class, and two lane masks will have a bit in common if two sub-register
1157 // indices overlap in some register.
1159 // Conservatively share a lane mask bit if two sub-register indices overlap in
1160 // some registers, but not in others. That shouldn't happen a lot.
1161 void CodeGenRegBank::computeSubRegLaneMasks() {
1162 // First assign individual bits to all the leaf indices.
1164 // Determine mask of lanes that cover their registers.
1165 CoveringLanes = ~0u;
1166 for (auto &Idx : SubRegIndices) {
1167 if (Idx.getComposites().empty()) {
1168 Idx.LaneMask = 1u << Bit;
1169 // Share bit 31 in the unlikely case there are more than 32 leafs.
1171 // Sharing bits is harmless; it allows graceful degradation in targets
1172 // with more than 32 vector lanes. They simply get a limited resolution
1173 // view of lanes beyond the 32nd.
1175 // See also the comment for getSubRegIndexLaneMask().
1179 // Once bit 31 is shared among multiple leafs, the 'lane' it represents
1180 // is no longer covering its registers.
1181 CoveringLanes &= ~(1u << Bit);
1187 // Compute transformation sequences for composeSubRegIndexLaneMask. The idea
1188 // here is that for each possible target subregister we look at the leafs
1189 // in the subregister graph that compose for this target and create
1190 // transformation sequences for the lanemasks. Each step in the sequence
1191 // consists of a bitmask and a bitrotate operation. As the rotation amounts
1192 // are usually the same for many subregisters we can easily combine the steps
1193 // by combining the masks.
1194 for (const auto &Idx : SubRegIndices) {
1195 const auto &Composites = Idx.getComposites();
1196 auto &LaneTransforms = Idx.CompositionLaneMaskTransform;
1197 // Go through all leaf subregisters and find the ones that compose with Idx.
1198 // These make out all possible valid bits in the lane mask we want to
1199 // transform. Looking only at the leafs ensure that only a single bit in
1201 unsigned NextBit = 0;
1202 for (auto &Idx2 : SubRegIndices) {
1203 // Skip non-leaf subregisters.
1204 if (!Idx2.getComposites().empty())
1206 // Replicate the behaviour from the lane mask generation loop above.
1207 unsigned SrcBit = NextBit;
1208 unsigned SrcMask = 1u << SrcBit;
1211 assert(Idx2.LaneMask == SrcMask);
1213 // Get the composed subregister if there is any.
1214 auto C = Composites.find(&Idx2);
1215 if (C == Composites.end())
1217 const CodeGenSubRegIndex *Composite = C->second;
1218 // The Composed subreg should be a leaf subreg too
1219 assert(Composite->getComposites().empty());
1221 // Create Mask+Rotate operation and merge with existing ops if possible.
1222 unsigned DstBit = Log2_32(Composite->LaneMask);
1223 int Shift = DstBit - SrcBit;
1224 uint8_t RotateLeft = Shift >= 0 ? (uint8_t)Shift : 32+Shift;
1225 for (auto &I : LaneTransforms) {
1226 if (I.RotateLeft == RotateLeft) {
1232 MaskRolPair MaskRol = { SrcMask, RotateLeft };
1233 LaneTransforms.push_back(MaskRol);
1236 // Optimize if the transformation consists of one step only: Set mask to
1237 // 0xffffffff (including some irrelevant invalid bits) so that it should
1238 // merge with more entries later while compressing the table.
1239 if (LaneTransforms.size() == 1)
1240 LaneTransforms[0].Mask = ~0u;
1242 // Further compression optimization: For invalid compositions resulting
1243 // in a sequence with 0 entries we can just pick any other. Choose
1244 // Mask 0xffffffff with Rotation 0.
1245 if (LaneTransforms.size() == 0) {
1246 MaskRolPair P = { ~0u, 0 };
1247 LaneTransforms.push_back(P);
1251 // FIXME: What if ad-hoc aliasing introduces overlaps that aren't represented
1252 // by the sub-register graph? This doesn't occur in any known targets.
1254 // Inherit lanes from composites.
1255 for (const auto &Idx : SubRegIndices) {
1256 unsigned Mask = Idx.computeLaneMask();
1257 // If some super-registers without CoveredBySubRegs use this index, we can
1258 // no longer assume that the lanes are covering their registers.
1259 if (!Idx.AllSuperRegsCovered)
1260 CoveringLanes &= ~Mask;
1263 // Compute lane mask combinations for register classes.
1264 for (auto &RegClass : RegClasses) {
1265 unsigned LaneMask = 0;
1266 for (const auto &SubRegIndex : SubRegIndices) {
1267 if (RegClass.getSubClassWithSubReg(&SubRegIndex) == nullptr)
1269 LaneMask |= SubRegIndex.LaneMask;
1271 RegClass.LaneMask = LaneMask;
1276 // UberRegSet is a helper class for computeRegUnitWeights. Each UberRegSet is
1277 // the transitive closure of the union of overlapping register
1278 // classes. Together, the UberRegSets form a partition of the registers. If we
1279 // consider overlapping register classes to be connected, then each UberRegSet
1280 // is a set of connected components.
1282 // An UberRegSet will likely be a horizontal slice of register names of
1283 // the same width. Nontrivial subregisters should then be in a separate
1284 // UberRegSet. But this property isn't required for valid computation of
1285 // register unit weights.
1287 // A Weight field caches the max per-register unit weight in each UberRegSet.
1289 // A set of SingularDeterminants flags single units of some register in this set
1290 // for which the unit weight equals the set weight. These units should not have
1291 // their weight increased.
1293 CodeGenRegister::Vec Regs;
1295 CodeGenRegister::RegUnitList SingularDeterminants;
1297 UberRegSet(): Weight(0) {}
1301 // Partition registers into UberRegSets, where each set is the transitive
1302 // closure of the union of overlapping register classes.
1304 // UberRegSets[0] is a special non-allocatable set.
1305 static void computeUberSets(std::vector<UberRegSet> &UberSets,
1306 std::vector<UberRegSet*> &RegSets,
1307 CodeGenRegBank &RegBank) {
1309 const auto &Registers = RegBank.getRegisters();
1311 // The Register EnumValue is one greater than its index into Registers.
1312 assert(Registers.size() == Registers.back().EnumValue &&
1313 "register enum value mismatch");
1315 // For simplicitly make the SetID the same as EnumValue.
1316 IntEqClasses UberSetIDs(Registers.size()+1);
1317 std::set<unsigned> AllocatableRegs;
1318 for (auto &RegClass : RegBank.getRegClasses()) {
1319 if (!RegClass.Allocatable)
1322 const CodeGenRegister::Vec &Regs = RegClass.getMembers();
1326 unsigned USetID = UberSetIDs.findLeader((*Regs.begin())->EnumValue);
1327 assert(USetID && "register number 0 is invalid");
1329 AllocatableRegs.insert((*Regs.begin())->EnumValue);
1330 for (auto I = std::next(Regs.begin()), E = Regs.end(); I != E; ++I) {
1331 AllocatableRegs.insert((*I)->EnumValue);
1332 UberSetIDs.join(USetID, (*I)->EnumValue);
1335 // Combine non-allocatable regs.
1336 for (const auto &Reg : Registers) {
1337 unsigned RegNum = Reg.EnumValue;
1338 if (AllocatableRegs.count(RegNum))
1341 UberSetIDs.join(0, RegNum);
1343 UberSetIDs.compress();
1345 // Make the first UberSet a special unallocatable set.
1346 unsigned ZeroID = UberSetIDs[0];
1348 // Insert Registers into the UberSets formed by union-find.
1349 // Do not resize after this.
1350 UberSets.resize(UberSetIDs.getNumClasses());
1352 for (const CodeGenRegister &Reg : Registers) {
1353 unsigned USetID = UberSetIDs[Reg.EnumValue];
1356 else if (USetID == ZeroID)
1359 UberRegSet *USet = &UberSets[USetID];
1360 USet->Regs.push_back(&Reg);
1361 sortAndUniqueRegisters(USet->Regs);
1362 RegSets[i++] = USet;
1366 // Recompute each UberSet weight after changing unit weights.
1367 static void computeUberWeights(std::vector<UberRegSet> &UberSets,
1368 CodeGenRegBank &RegBank) {
1369 // Skip the first unallocatable set.
1370 for (std::vector<UberRegSet>::iterator I = std::next(UberSets.begin()),
1371 E = UberSets.end(); I != E; ++I) {
1373 // Initialize all unit weights in this set, and remember the max units/reg.
1374 const CodeGenRegister *Reg = nullptr;
1375 unsigned MaxWeight = 0, Weight = 0;
1376 for (RegUnitIterator UnitI(I->Regs); UnitI.isValid(); ++UnitI) {
1377 if (Reg != UnitI.getReg()) {
1378 if (Weight > MaxWeight)
1380 Reg = UnitI.getReg();
1383 unsigned UWeight = RegBank.getRegUnit(*UnitI).Weight;
1386 RegBank.increaseRegUnitWeight(*UnitI, UWeight);
1390 if (Weight > MaxWeight)
1392 if (I->Weight != MaxWeight) {
1394 dbgs() << "UberSet " << I - UberSets.begin() << " Weight " << MaxWeight;
1395 for (auto &Unit : I->Regs)
1396 dbgs() << " " << Unit->getName();
1398 // Update the set weight.
1399 I->Weight = MaxWeight;
1402 // Find singular determinants.
1403 for (const auto R : I->Regs) {
1404 if (R->getRegUnits().count() == 1 && R->getWeight(RegBank) == I->Weight) {
1405 I->SingularDeterminants |= R->getRegUnits();
1411 // normalizeWeight is a computeRegUnitWeights helper that adjusts the weight of
1412 // a register and its subregisters so that they have the same weight as their
1413 // UberSet. Self-recursion processes the subregister tree in postorder so
1414 // subregisters are normalized first.
1417 // - creates new adopted register units
1418 // - causes superregisters to inherit adopted units
1419 // - increases the weight of "singular" units
1420 // - induces recomputation of UberWeights.
1421 static bool normalizeWeight(CodeGenRegister *Reg,
1422 std::vector<UberRegSet> &UberSets,
1423 std::vector<UberRegSet*> &RegSets,
1424 SparseBitVector<> &NormalRegs,
1425 CodeGenRegister::RegUnitList &NormalUnits,
1426 CodeGenRegBank &RegBank) {
1427 if (NormalRegs.test(Reg->EnumValue))
1429 NormalRegs.set(Reg->EnumValue);
1431 bool Changed = false;
1432 const CodeGenRegister::SubRegMap &SRM = Reg->getSubRegs();
1433 for (CodeGenRegister::SubRegMap::const_iterator SRI = SRM.begin(),
1434 SRE = SRM.end(); SRI != SRE; ++SRI) {
1435 if (SRI->second == Reg)
1436 continue; // self-cycles happen
1438 Changed |= normalizeWeight(SRI->second, UberSets, RegSets,
1439 NormalRegs, NormalUnits, RegBank);
1441 // Postorder register normalization.
1443 // Inherit register units newly adopted by subregisters.
1444 if (Reg->inheritRegUnits(RegBank))
1445 computeUberWeights(UberSets, RegBank);
1447 // Check if this register is too skinny for its UberRegSet.
1448 UberRegSet *UberSet = RegSets[RegBank.getRegIndex(Reg)];
1450 unsigned RegWeight = Reg->getWeight(RegBank);
1451 if (UberSet->Weight > RegWeight) {
1452 // A register unit's weight can be adjusted only if it is the singular unit
1453 // for this register, has not been used to normalize a subregister's set,
1454 // and has not already been used to singularly determine this UberRegSet.
1455 unsigned AdjustUnit = *Reg->getRegUnits().begin();
1456 if (Reg->getRegUnits().count() != 1
1457 || hasRegUnit(NormalUnits, AdjustUnit)
1458 || hasRegUnit(UberSet->SingularDeterminants, AdjustUnit)) {
1459 // We don't have an adjustable unit, so adopt a new one.
1460 AdjustUnit = RegBank.newRegUnit(UberSet->Weight - RegWeight);
1461 Reg->adoptRegUnit(AdjustUnit);
1462 // Adopting a unit does not immediately require recomputing set weights.
1465 // Adjust the existing single unit.
1466 RegBank.increaseRegUnitWeight(AdjustUnit, UberSet->Weight - RegWeight);
1467 // The unit may be shared among sets and registers within this set.
1468 computeUberWeights(UberSets, RegBank);
1473 // Mark these units normalized so superregisters can't change their weights.
1474 NormalUnits |= Reg->getRegUnits();
1479 // Compute a weight for each register unit created during getSubRegs.
1481 // The goal is that two registers in the same class will have the same weight,
1482 // where each register's weight is defined as sum of its units' weights.
1483 void CodeGenRegBank::computeRegUnitWeights() {
1484 std::vector<UberRegSet> UberSets;
1485 std::vector<UberRegSet*> RegSets(Registers.size());
1486 computeUberSets(UberSets, RegSets, *this);
1487 // UberSets and RegSets are now immutable.
1489 computeUberWeights(UberSets, *this);
1491 // Iterate over each Register, normalizing the unit weights until reaching
1493 unsigned NumIters = 0;
1494 for (bool Changed = true; Changed; ++NumIters) {
1495 assert(NumIters <= NumNativeRegUnits && "Runaway register unit weights");
1497 for (auto &Reg : Registers) {
1498 CodeGenRegister::RegUnitList NormalUnits;
1499 SparseBitVector<> NormalRegs;
1500 Changed |= normalizeWeight(&Reg, UberSets, RegSets, NormalRegs,
1501 NormalUnits, *this);
1506 // Find a set in UniqueSets with the same elements as Set.
1507 // Return an iterator into UniqueSets.
1508 static std::vector<RegUnitSet>::const_iterator
1509 findRegUnitSet(const std::vector<RegUnitSet> &UniqueSets,
1510 const RegUnitSet &Set) {
1511 std::vector<RegUnitSet>::const_iterator
1512 I = UniqueSets.begin(), E = UniqueSets.end();
1514 if (I->Units == Set.Units)
1520 // Return true if the RUSubSet is a subset of RUSuperSet.
1521 static bool isRegUnitSubSet(const std::vector<unsigned> &RUSubSet,
1522 const std::vector<unsigned> &RUSuperSet) {
1523 return std::includes(RUSuperSet.begin(), RUSuperSet.end(),
1524 RUSubSet.begin(), RUSubSet.end());
1527 /// Iteratively prune unit sets. Prune subsets that are close to the superset,
1528 /// but with one or two registers removed. We occasionally have registers like
1529 /// APSR and PC thrown in with the general registers. We also see many
1530 /// special-purpose register subsets, such as tail-call and Thumb
1531 /// encodings. Generating all possible overlapping sets is combinatorial and
1532 /// overkill for modeling pressure. Ideally we could fix this statically in
1533 /// tablegen by (1) having the target define register classes that only include
1534 /// the allocatable registers and marking other classes as non-allocatable and
1535 /// (2) having a way to mark special purpose classes as "don't-care" classes for
1536 /// the purpose of pressure. However, we make an attempt to handle targets that
1537 /// are not nicely defined by merging nearly identical register unit sets
1538 /// statically. This generates smaller tables. Then, dynamically, we adjust the
1539 /// set limit by filtering the reserved registers.
1541 /// Merge sets only if the units have the same weight. For example, on ARM,
1542 /// Q-tuples with ssub index 0 include all S regs but also include D16+. We
1543 /// should not expand the S set to include D regs.
1544 void CodeGenRegBank::pruneUnitSets() {
1545 assert(RegClassUnitSets.empty() && "this invalidates RegClassUnitSets");
1547 // Form an equivalence class of UnitSets with no significant difference.
1548 std::vector<unsigned> SuperSetIDs;
1549 for (unsigned SubIdx = 0, EndIdx = RegUnitSets.size();
1550 SubIdx != EndIdx; ++SubIdx) {
1551 const RegUnitSet &SubSet = RegUnitSets[SubIdx];
1552 unsigned SuperIdx = 0;
1553 for (; SuperIdx != EndIdx; ++SuperIdx) {
1554 if (SuperIdx == SubIdx)
1557 unsigned UnitWeight = RegUnits[SubSet.Units[0]].Weight;
1558 const RegUnitSet &SuperSet = RegUnitSets[SuperIdx];
1559 if (isRegUnitSubSet(SubSet.Units, SuperSet.Units)
1560 && (SubSet.Units.size() + 3 > SuperSet.Units.size())
1561 && UnitWeight == RegUnits[SuperSet.Units[0]].Weight
1562 && UnitWeight == RegUnits[SuperSet.Units.back()].Weight) {
1563 DEBUG(dbgs() << "UnitSet " << SubIdx << " subsumed by " << SuperIdx
1568 if (SuperIdx == EndIdx)
1569 SuperSetIDs.push_back(SubIdx);
1571 // Populate PrunedUnitSets with each equivalence class's superset.
1572 std::vector<RegUnitSet> PrunedUnitSets(SuperSetIDs.size());
1573 for (unsigned i = 0, e = SuperSetIDs.size(); i != e; ++i) {
1574 unsigned SuperIdx = SuperSetIDs[i];
1575 PrunedUnitSets[i].Name = RegUnitSets[SuperIdx].Name;
1576 PrunedUnitSets[i].Units.swap(RegUnitSets[SuperIdx].Units);
1578 RegUnitSets.swap(PrunedUnitSets);
1581 // Create a RegUnitSet for each RegClass that contains all units in the class
1582 // including adopted units that are necessary to model register pressure. Then
1583 // iteratively compute RegUnitSets such that the union of any two overlapping
1584 // RegUnitSets is repreresented.
1586 // RegisterInfoEmitter will map each RegClass to its RegUnitClass and any
1587 // RegUnitSet that is a superset of that RegUnitClass.
1588 void CodeGenRegBank::computeRegUnitSets() {
1589 assert(RegUnitSets.empty() && "dirty RegUnitSets");
1591 // Compute a unique RegUnitSet for each RegClass.
1592 auto &RegClasses = getRegClasses();
1593 for (auto &RC : RegClasses) {
1594 if (!RC.Allocatable)
1597 // Speculatively grow the RegUnitSets to hold the new set.
1598 RegUnitSets.resize(RegUnitSets.size() + 1);
1599 RegUnitSets.back().Name = RC.getName();
1601 // Compute a sorted list of units in this class.
1602 RC.buildRegUnitSet(RegUnitSets.back().Units);
1604 // Find an existing RegUnitSet.
1605 std::vector<RegUnitSet>::const_iterator SetI =
1606 findRegUnitSet(RegUnitSets, RegUnitSets.back());
1607 if (SetI != std::prev(RegUnitSets.end()))
1608 RegUnitSets.pop_back();
1611 DEBUG(dbgs() << "\nBefore pruning:\n";
1612 for (unsigned USIdx = 0, USEnd = RegUnitSets.size();
1613 USIdx < USEnd; ++USIdx) {
1614 dbgs() << "UnitSet " << USIdx << " " << RegUnitSets[USIdx].Name
1616 for (auto &U : RegUnitSets[USIdx].Units)
1617 dbgs() << " " << RegUnits[U].Roots[0]->getName();
1621 // Iteratively prune unit sets.
1624 DEBUG(dbgs() << "\nBefore union:\n";
1625 for (unsigned USIdx = 0, USEnd = RegUnitSets.size();
1626 USIdx < USEnd; ++USIdx) {
1627 dbgs() << "UnitSet " << USIdx << " " << RegUnitSets[USIdx].Name
1629 for (auto &U : RegUnitSets[USIdx].Units)
1630 dbgs() << " " << RegUnits[U].Roots[0]->getName();
1633 dbgs() << "\nUnion sets:\n");
1635 // Iterate over all unit sets, including new ones added by this loop.
1636 unsigned NumRegUnitSubSets = RegUnitSets.size();
1637 for (unsigned Idx = 0, EndIdx = RegUnitSets.size(); Idx != EndIdx; ++Idx) {
1638 // In theory, this is combinatorial. In practice, it needs to be bounded
1639 // by a small number of sets for regpressure to be efficient.
1640 // If the assert is hit, we need to implement pruning.
1641 assert(Idx < (2*NumRegUnitSubSets) && "runaway unit set inference");
1643 // Compare new sets with all original classes.
1644 for (unsigned SearchIdx = (Idx >= NumRegUnitSubSets) ? 0 : Idx+1;
1645 SearchIdx != EndIdx; ++SearchIdx) {
1646 std::set<unsigned> Intersection;
1647 std::set_intersection(RegUnitSets[Idx].Units.begin(),
1648 RegUnitSets[Idx].Units.end(),
1649 RegUnitSets[SearchIdx].Units.begin(),
1650 RegUnitSets[SearchIdx].Units.end(),
1651 std::inserter(Intersection, Intersection.begin()));
1652 if (Intersection.empty())
1655 // Speculatively grow the RegUnitSets to hold the new set.
1656 RegUnitSets.resize(RegUnitSets.size() + 1);
1657 RegUnitSets.back().Name =
1658 RegUnitSets[Idx].Name + "+" + RegUnitSets[SearchIdx].Name;
1660 std::set_union(RegUnitSets[Idx].Units.begin(),
1661 RegUnitSets[Idx].Units.end(),
1662 RegUnitSets[SearchIdx].Units.begin(),
1663 RegUnitSets[SearchIdx].Units.end(),
1664 std::inserter(RegUnitSets.back().Units,
1665 RegUnitSets.back().Units.begin()));
1667 // Find an existing RegUnitSet, or add the union to the unique sets.
1668 std::vector<RegUnitSet>::const_iterator SetI =
1669 findRegUnitSet(RegUnitSets, RegUnitSets.back());
1670 if (SetI != std::prev(RegUnitSets.end()))
1671 RegUnitSets.pop_back();
1673 DEBUG(dbgs() << "UnitSet " << RegUnitSets.size()-1
1674 << " " << RegUnitSets.back().Name << ":";
1675 for (auto &U : RegUnitSets.back().Units)
1676 dbgs() << " " << RegUnits[U].Roots[0]->getName();
1682 // Iteratively prune unit sets after inferring supersets.
1685 DEBUG(dbgs() << "\n";
1686 for (unsigned USIdx = 0, USEnd = RegUnitSets.size();
1687 USIdx < USEnd; ++USIdx) {
1688 dbgs() << "UnitSet " << USIdx << " " << RegUnitSets[USIdx].Name
1690 for (auto &U : RegUnitSets[USIdx].Units)
1691 dbgs() << " " << RegUnits[U].Roots[0]->getName();
1695 // For each register class, list the UnitSets that are supersets.
1696 RegClassUnitSets.resize(RegClasses.size());
1698 for (auto &RC : RegClasses) {
1700 if (!RC.Allocatable)
1703 // Recompute the sorted list of units in this class.
1704 std::vector<unsigned> RCRegUnits;
1705 RC.buildRegUnitSet(RCRegUnits);
1707 // Don't increase pressure for unallocatable regclasses.
1708 if (RCRegUnits.empty())
1711 DEBUG(dbgs() << "RC " << RC.getName() << " Units: \n";
1712 for (auto &U : RCRegUnits)
1713 dbgs() << RegUnits[U].getRoots()[0]->getName() << " ";
1714 dbgs() << "\n UnitSetIDs:");
1716 // Find all supersets.
1717 for (unsigned USIdx = 0, USEnd = RegUnitSets.size();
1718 USIdx != USEnd; ++USIdx) {
1719 if (isRegUnitSubSet(RCRegUnits, RegUnitSets[USIdx].Units)) {
1720 DEBUG(dbgs() << " " << USIdx);
1721 RegClassUnitSets[RCIdx].push_back(USIdx);
1724 DEBUG(dbgs() << "\n");
1725 assert(!RegClassUnitSets[RCIdx].empty() && "missing unit set for regclass");
1728 // For each register unit, ensure that we have the list of UnitSets that
1729 // contain the unit. Normally, this matches an existing list of UnitSets for a
1730 // register class. If not, we create a new entry in RegClassUnitSets as a
1731 // "fake" register class.
1732 for (unsigned UnitIdx = 0, UnitEnd = NumNativeRegUnits;
1733 UnitIdx < UnitEnd; ++UnitIdx) {
1734 std::vector<unsigned> RUSets;
1735 for (unsigned i = 0, e = RegUnitSets.size(); i != e; ++i) {
1736 RegUnitSet &RUSet = RegUnitSets[i];
1737 if (std::find(RUSet.Units.begin(), RUSet.Units.end(), UnitIdx)
1738 == RUSet.Units.end())
1740 RUSets.push_back(i);
1742 unsigned RCUnitSetsIdx = 0;
1743 for (unsigned e = RegClassUnitSets.size();
1744 RCUnitSetsIdx != e; ++RCUnitSetsIdx) {
1745 if (RegClassUnitSets[RCUnitSetsIdx] == RUSets) {
1749 RegUnits[UnitIdx].RegClassUnitSetsIdx = RCUnitSetsIdx;
1750 if (RCUnitSetsIdx == RegClassUnitSets.size()) {
1751 // Create a new list of UnitSets as a "fake" register class.
1752 RegClassUnitSets.resize(RCUnitSetsIdx + 1);
1753 RegClassUnitSets[RCUnitSetsIdx].swap(RUSets);
1758 void CodeGenRegBank::computeRegUnitLaneMasks() {
1759 for (auto &Register : Registers) {
1760 // Create an initial lane mask for all register units.
1761 const auto &RegUnits = Register.getRegUnits();
1762 CodeGenRegister::RegUnitLaneMaskList RegUnitLaneMasks(RegUnits.count(), 0);
1763 // Iterate through SubRegisters.
1764 typedef CodeGenRegister::SubRegMap SubRegMap;
1765 const SubRegMap &SubRegs = Register.getSubRegs();
1766 for (SubRegMap::const_iterator S = SubRegs.begin(),
1767 SE = SubRegs.end(); S != SE; ++S) {
1768 CodeGenRegister *SubReg = S->second;
1769 // Ignore non-leaf subregisters, their lane masks are fully covered by
1770 // the leaf subregisters anyway.
1771 if (SubReg->getSubRegs().size() != 0)
1773 CodeGenSubRegIndex *SubRegIndex = S->first;
1774 const CodeGenRegister *SubRegister = S->second;
1775 unsigned LaneMask = SubRegIndex->LaneMask;
1776 // Distribute LaneMask to Register Units touched.
1777 for (const auto &SUI : SubRegister->getRegUnits()) {
1780 for (unsigned RU : RegUnits) {
1782 RegUnitLaneMasks[u] |= LaneMask;
1792 Register.setRegUnitLaneMasks(RegUnitLaneMasks);
1796 void CodeGenRegBank::computeDerivedInfo() {
1797 computeComposites();
1798 computeSubRegLaneMasks();
1800 // Compute a weight for each register unit created during getSubRegs.
1801 // This may create adopted register units (with unit # >= NumNativeRegUnits).
1802 computeRegUnitWeights();
1804 // Compute a unique set of RegUnitSets. One for each RegClass and inferred
1805 // supersets for the union of overlapping sets.
1806 computeRegUnitSets();
1808 computeRegUnitLaneMasks();
1810 // Compute register class HasDisjunctSubRegs flag.
1811 for (CodeGenRegisterClass &RC : RegClasses) {
1812 RC.HasDisjunctSubRegs = false;
1813 for (const CodeGenRegister *Reg : RC.getMembers())
1814 RC.HasDisjunctSubRegs |= Reg->HasDisjunctSubRegs;
1817 // Get the weight of each set.
1818 for (unsigned Idx = 0, EndIdx = RegUnitSets.size(); Idx != EndIdx; ++Idx)
1819 RegUnitSets[Idx].Weight = getRegUnitSetWeight(RegUnitSets[Idx].Units);
1821 // Find the order of each set.
1822 RegUnitSetOrder.reserve(RegUnitSets.size());
1823 for (unsigned Idx = 0, EndIdx = RegUnitSets.size(); Idx != EndIdx; ++Idx)
1824 RegUnitSetOrder.push_back(Idx);
1826 std::stable_sort(RegUnitSetOrder.begin(), RegUnitSetOrder.end(),
1827 [this](unsigned ID1, unsigned ID2) {
1828 return getRegPressureSet(ID1).Units.size() <
1829 getRegPressureSet(ID2).Units.size();
1831 for (unsigned Idx = 0, EndIdx = RegUnitSets.size(); Idx != EndIdx; ++Idx) {
1832 RegUnitSets[RegUnitSetOrder[Idx]].Order = Idx;
1837 // Synthesize missing register class intersections.
1839 // Make sure that sub-classes of RC exists such that getCommonSubClass(RC, X)
1840 // returns a maximal register class for all X.
1842 void CodeGenRegBank::inferCommonSubClass(CodeGenRegisterClass *RC) {
1843 assert(!RegClasses.empty());
1844 // Stash the iterator to the last element so that this loop doesn't visit
1845 // elements added by the getOrCreateSubClass call within it.
1846 for (auto I = RegClasses.begin(), E = std::prev(RegClasses.end());
1847 I != std::next(E); ++I) {
1848 CodeGenRegisterClass *RC1 = RC;
1849 CodeGenRegisterClass *RC2 = &*I;
1853 // Compute the set intersection of RC1 and RC2.
1854 const CodeGenRegister::Vec &Memb1 = RC1->getMembers();
1855 const CodeGenRegister::Vec &Memb2 = RC2->getMembers();
1856 CodeGenRegister::Vec Intersection;
1857 std::set_intersection(
1858 Memb1.begin(), Memb1.end(), Memb2.begin(), Memb2.end(),
1859 std::inserter(Intersection, Intersection.begin()), deref<llvm::less>());
1861 // Skip disjoint class pairs.
1862 if (Intersection.empty())
1865 // If RC1 and RC2 have different spill sizes or alignments, use the
1866 // larger size for sub-classing. If they are equal, prefer RC1.
1867 if (RC2->SpillSize > RC1->SpillSize ||
1868 (RC2->SpillSize == RC1->SpillSize &&
1869 RC2->SpillAlignment > RC1->SpillAlignment))
1870 std::swap(RC1, RC2);
1872 getOrCreateSubClass(RC1, &Intersection,
1873 RC1->getName() + "_and_" + RC2->getName());
1878 // Synthesize missing sub-classes for getSubClassWithSubReg().
1880 // Make sure that the set of registers in RC with a given SubIdx sub-register
1881 // form a register class. Update RC->SubClassWithSubReg.
1883 void CodeGenRegBank::inferSubClassWithSubReg(CodeGenRegisterClass *RC) {
1884 // Map SubRegIndex to set of registers in RC supporting that SubRegIndex.
1885 typedef std::map<const CodeGenSubRegIndex *, CodeGenRegister::Vec,
1886 deref<llvm::less>> SubReg2SetMap;
1888 // Compute the set of registers supporting each SubRegIndex.
1889 SubReg2SetMap SRSets;
1890 for (const auto R : RC->getMembers()) {
1891 const CodeGenRegister::SubRegMap &SRM = R->getSubRegs();
1892 for (CodeGenRegister::SubRegMap::const_iterator I = SRM.begin(),
1893 E = SRM.end(); I != E; ++I)
1894 SRSets[I->first].push_back(R);
1897 for (auto I : SRSets)
1898 sortAndUniqueRegisters(I.second);
1900 // Find matching classes for all SRSets entries. Iterate in SubRegIndex
1901 // numerical order to visit synthetic indices last.
1902 for (const auto &SubIdx : SubRegIndices) {
1903 SubReg2SetMap::const_iterator I = SRSets.find(&SubIdx);
1904 // Unsupported SubRegIndex. Skip it.
1905 if (I == SRSets.end())
1907 // In most cases, all RC registers support the SubRegIndex.
1908 if (I->second.size() == RC->getMembers().size()) {
1909 RC->setSubClassWithSubReg(&SubIdx, RC);
1912 // This is a real subset. See if we have a matching class.
1913 CodeGenRegisterClass *SubRC =
1914 getOrCreateSubClass(RC, &I->second,
1915 RC->getName() + "_with_" + I->first->getName());
1916 RC->setSubClassWithSubReg(&SubIdx, SubRC);
1921 // Synthesize missing sub-classes of RC for getMatchingSuperRegClass().
1923 // Create sub-classes of RC such that getMatchingSuperRegClass(RC, SubIdx, X)
1924 // has a maximal result for any SubIdx and any X >= FirstSubRegRC.
1927 void CodeGenRegBank::inferMatchingSuperRegClass(CodeGenRegisterClass *RC,
1928 std::list<CodeGenRegisterClass>::iterator FirstSubRegRC) {
1929 SmallVector<std::pair<const CodeGenRegister*,
1930 const CodeGenRegister*>, 16> SSPairs;
1931 BitVector TopoSigs(getNumTopoSigs());
1933 // Iterate in SubRegIndex numerical order to visit synthetic indices last.
1934 for (auto &SubIdx : SubRegIndices) {
1935 // Skip indexes that aren't fully supported by RC's registers. This was
1936 // computed by inferSubClassWithSubReg() above which should have been
1938 if (RC->getSubClassWithSubReg(&SubIdx) != RC)
1941 // Build list of (Super, Sub) pairs for this SubIdx.
1944 for (const auto Super : RC->getMembers()) {
1945 const CodeGenRegister *Sub = Super->getSubRegs().find(&SubIdx)->second;
1946 assert(Sub && "Missing sub-register");
1947 SSPairs.push_back(std::make_pair(Super, Sub));
1948 TopoSigs.set(Sub->getTopoSig());
1951 // Iterate over sub-register class candidates. Ignore classes created by
1952 // this loop. They will never be useful.
1953 // Store an iterator to the last element (not end) so that this loop doesn't
1954 // visit newly inserted elements.
1955 assert(!RegClasses.empty());
1956 for (auto I = FirstSubRegRC, E = std::prev(RegClasses.end());
1957 I != std::next(E); ++I) {
1958 CodeGenRegisterClass &SubRC = *I;
1959 // Topological shortcut: SubRC members have the wrong shape.
1960 if (!TopoSigs.anyCommon(SubRC.getTopoSigs()))
1962 // Compute the subset of RC that maps into SubRC.
1963 CodeGenRegister::Vec SubSetVec;
1964 for (unsigned i = 0, e = SSPairs.size(); i != e; ++i)
1965 if (SubRC.contains(SSPairs[i].second))
1966 SubSetVec.push_back(SSPairs[i].first);
1968 if (SubSetVec.empty())
1971 // RC injects completely into SubRC.
1972 sortAndUniqueRegisters(SubSetVec);
1973 if (SubSetVec.size() == SSPairs.size()) {
1974 SubRC.addSuperRegClass(&SubIdx, RC);
1978 // Only a subset of RC maps into SubRC. Make sure it is represented by a
1980 getOrCreateSubClass(RC, &SubSetVec, RC->getName() + "_with_" +
1981 SubIdx.getName() + "_in_" +
1989 // Infer missing register classes.
1991 void CodeGenRegBank::computeInferredRegisterClasses() {
1992 assert(!RegClasses.empty());
1993 // When this function is called, the register classes have not been sorted
1994 // and assigned EnumValues yet. That means getSubClasses(),
1995 // getSuperClasses(), and hasSubClass() functions are defunct.
1997 // Use one-before-the-end so it doesn't move forward when new elements are
1999 auto FirstNewRC = std::prev(RegClasses.end());
2001 // Visit all register classes, including the ones being added by the loop.
2002 // Watch out for iterator invalidation here.
2003 for (auto I = RegClasses.begin(), E = RegClasses.end(); I != E; ++I) {
2004 CodeGenRegisterClass *RC = &*I;
2006 // Synthesize answers for getSubClassWithSubReg().
2007 inferSubClassWithSubReg(RC);
2009 // Synthesize answers for getCommonSubClass().
2010 inferCommonSubClass(RC);
2012 // Synthesize answers for getMatchingSuperRegClass().
2013 inferMatchingSuperRegClass(RC);
2015 // New register classes are created while this loop is running, and we need
2016 // to visit all of them. I particular, inferMatchingSuperRegClass needs
2017 // to match old super-register classes with sub-register classes created
2018 // after inferMatchingSuperRegClass was called. At this point,
2019 // inferMatchingSuperRegClass has checked SuperRC = [0..rci] with SubRC =
2020 // [0..FirstNewRC). We need to cover SubRC = [FirstNewRC..rci].
2021 if (I == FirstNewRC) {
2022 auto NextNewRC = std::prev(RegClasses.end());
2023 for (auto I2 = RegClasses.begin(), E2 = std::next(FirstNewRC); I2 != E2;
2025 inferMatchingSuperRegClass(&*I2, E2);
2026 FirstNewRC = NextNewRC;
2031 /// getRegisterClassForRegister - Find the register class that contains the
2032 /// specified physical register. If the register is not in a register class,
2033 /// return null. If the register is in multiple classes, and the classes have a
2034 /// superset-subset relationship and the same set of types, return the
2035 /// superclass. Otherwise return null.
2036 const CodeGenRegisterClass*
2037 CodeGenRegBank::getRegClassForRegister(Record *R) {
2038 const CodeGenRegister *Reg = getReg(R);
2039 const CodeGenRegisterClass *FoundRC = nullptr;
2040 for (const auto &RC : getRegClasses()) {
2041 if (!RC.contains(Reg))
2044 // If this is the first class that contains the register,
2045 // make a note of it and go on to the next class.
2051 // If a register's classes have different types, return null.
2052 if (RC.getValueTypes() != FoundRC->getValueTypes())
2055 // Check to see if the previously found class that contains
2056 // the register is a subclass of the current class. If so,
2057 // prefer the superclass.
2058 if (RC.hasSubClass(FoundRC)) {
2063 // Check to see if the previously found class that contains
2064 // the register is a superclass of the current class. If so,
2065 // prefer the superclass.
2066 if (FoundRC->hasSubClass(&RC))
2069 // Multiple classes, and neither is a superclass of the other.
2076 BitVector CodeGenRegBank::computeCoveredRegisters(ArrayRef<Record*> Regs) {
2077 SetVector<const CodeGenRegister*> Set;
2079 // First add Regs with all sub-registers.
2080 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
2081 CodeGenRegister *Reg = getReg(Regs[i]);
2082 if (Set.insert(Reg))
2083 // Reg is new, add all sub-registers.
2084 // The pre-ordering is not important here.
2085 Reg->addSubRegsPreOrder(Set, *this);
2088 // Second, find all super-registers that are completely covered by the set.
2089 for (unsigned i = 0; i != Set.size(); ++i) {
2090 const CodeGenRegister::SuperRegList &SR = Set[i]->getSuperRegs();
2091 for (unsigned j = 0, e = SR.size(); j != e; ++j) {
2092 const CodeGenRegister *Super = SR[j];
2093 if (!Super->CoveredBySubRegs || Set.count(Super))
2095 // This new super-register is covered by its sub-registers.
2096 bool AllSubsInSet = true;
2097 const CodeGenRegister::SubRegMap &SRM = Super->getSubRegs();
2098 for (CodeGenRegister::SubRegMap::const_iterator I = SRM.begin(),
2099 E = SRM.end(); I != E; ++I)
2100 if (!Set.count(I->second)) {
2101 AllSubsInSet = false;
2104 // All sub-registers in Set, add Super as well.
2105 // We will visit Super later to recheck its super-registers.
2111 // Convert to BitVector.
2112 BitVector BV(Registers.size() + 1);
2113 for (unsigned i = 0, e = Set.size(); i != e; ++i)
2114 BV.set(Set[i]->EnumValue);