1 //===- CodeGenRegisters.cpp - Register and RegisterClass Info -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines structures to encapsulate information gleaned from the
11 // target register and register class definitions.
13 //===----------------------------------------------------------------------===//
15 #include "CodeGenRegisters.h"
16 #include "CodeGenTarget.h"
17 #include "llvm/TableGen/Error.h"
18 #include "llvm/ADT/IntEqClasses.h"
19 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/StringExtras.h"
22 #include "llvm/ADT/Twine.h"
26 //===----------------------------------------------------------------------===//
28 //===----------------------------------------------------------------------===//
30 CodeGenSubRegIndex::CodeGenSubRegIndex(Record *R, unsigned Enum)
35 std::string CodeGenSubRegIndex::getNamespace() const {
36 if (TheDef->getValue("Namespace"))
37 return TheDef->getValueAsString("Namespace");
42 const std::string &CodeGenSubRegIndex::getName() const {
43 return TheDef->getName();
46 std::string CodeGenSubRegIndex::getQualifiedName() const {
47 std::string N = getNamespace();
54 void CodeGenSubRegIndex::updateComponents(CodeGenRegBank &RegBank) {
55 std::vector<Record*> Comps = TheDef->getValueAsListOfDefs("ComposedOf");
58 if (Comps.size() != 2)
59 throw TGError(TheDef->getLoc(), "ComposedOf must have exactly two entries");
60 CodeGenSubRegIndex *A = RegBank.getSubRegIdx(Comps[0]);
61 CodeGenSubRegIndex *B = RegBank.getSubRegIdx(Comps[1]);
62 CodeGenSubRegIndex *X = A->addComposite(B, this);
64 throw TGError(TheDef->getLoc(), "Ambiguous ComposedOf entries");
67 void CodeGenSubRegIndex::cleanComposites() {
68 // Clean out redundant mappings of the form this+X -> X.
69 for (CompMap::iterator i = Composed.begin(), e = Composed.end(); i != e;) {
70 CompMap::iterator j = i;
72 if (j->first == j->second)
77 //===----------------------------------------------------------------------===//
79 //===----------------------------------------------------------------------===//
81 CodeGenRegister::CodeGenRegister(Record *R, unsigned Enum)
84 CostPerUse(R->getValueAsInt("CostPerUse")),
85 CoveredBySubRegs(R->getValueAsBit("CoveredBySubRegs")),
86 SubRegsComplete(false)
89 const std::string &CodeGenRegister::getName() const {
90 return TheDef->getName();
94 // Iterate over all register units in a set of registers.
95 class RegUnitIterator {
96 CodeGenRegister::Set::const_iterator RegI, RegE;
97 CodeGenRegister::RegUnitList::const_iterator UnitI, UnitE;
100 RegUnitIterator(const CodeGenRegister::Set &Regs):
101 RegI(Regs.begin()), RegE(Regs.end()), UnitI(), UnitE() {
104 UnitI = (*RegI)->getRegUnits().begin();
105 UnitE = (*RegI)->getRegUnits().end();
110 bool isValid() const { return UnitI != UnitE; }
112 unsigned operator* () const { assert(isValid()); return *UnitI; };
114 const CodeGenRegister *getReg() const { assert(isValid()); return *RegI; }
116 /// Preincrement. Move to the next unit.
118 assert(isValid() && "Cannot advance beyond the last operand");
125 while (UnitI == UnitE) {
128 UnitI = (*RegI)->getRegUnits().begin();
129 UnitE = (*RegI)->getRegUnits().end();
135 // Merge two RegUnitLists maintaining the order and removing duplicates.
136 // Overwrites MergedRU in the process.
137 static void mergeRegUnits(CodeGenRegister::RegUnitList &MergedRU,
138 const CodeGenRegister::RegUnitList &RRU) {
139 CodeGenRegister::RegUnitList LRU = MergedRU;
141 std::set_union(LRU.begin(), LRU.end(), RRU.begin(), RRU.end(),
142 std::back_inserter(MergedRU));
145 // Return true of this unit appears in RegUnits.
146 static bool hasRegUnit(CodeGenRegister::RegUnitList &RegUnits, unsigned Unit) {
147 return std::count(RegUnits.begin(), RegUnits.end(), Unit);
150 // Inherit register units from subregisters.
151 // Return true if the RegUnits changed.
152 bool CodeGenRegister::inheritRegUnits(CodeGenRegBank &RegBank) {
153 unsigned OldNumUnits = RegUnits.size();
154 for (SubRegMap::const_iterator I = SubRegs.begin(), E = SubRegs.end();
156 // Strangely a register may have itself as a subreg (self-cycle) e.g. XMM.
157 // Only create a unit if no other subregs have units.
158 CodeGenRegister *SR = I->second;
160 // RegUnits are only empty during getSubRegs, prior to computing weight.
161 if (RegUnits.empty())
162 RegUnits.push_back(RegBank.newRegUnit(0));
165 // Merge the subregister's units into this register's RegUnits.
166 mergeRegUnits(RegUnits, SR->RegUnits);
168 return OldNumUnits != RegUnits.size();
171 const CodeGenRegister::SubRegMap &
172 CodeGenRegister::getSubRegs(CodeGenRegBank &RegBank) {
173 // Only compute this map once.
176 SubRegsComplete = true;
178 std::vector<Record*> SubList = TheDef->getValueAsListOfDefs("SubRegs");
179 std::vector<Record*> IdxList = TheDef->getValueAsListOfDefs("SubRegIndices");
180 if (SubList.size() != IdxList.size())
181 throw TGError(TheDef->getLoc(), "Register " + getName() +
182 " SubRegIndices doesn't match SubRegs");
184 // First insert the direct subregs and make sure they are fully indexed.
185 SmallVector<CodeGenSubRegIndex*, 8> Indices;
186 for (unsigned i = 0, e = SubList.size(); i != e; ++i) {
187 CodeGenRegister *SR = RegBank.getReg(SubList[i]);
188 CodeGenSubRegIndex *Idx = RegBank.getSubRegIdx(IdxList[i]);
189 Indices.push_back(Idx);
190 if (!SubRegs.insert(std::make_pair(Idx, SR)).second)
191 throw TGError(TheDef->getLoc(), "SubRegIndex " + Idx->getName() +
192 " appears twice in Register " + getName());
195 // Keep track of inherited subregs and how they can be reached.
196 SmallPtrSet<CodeGenRegister*, 8> Orphans;
198 // Clone inherited subregs and place duplicate entries in Orphans.
199 // Here the order is important - earlier subregs take precedence.
200 for (unsigned i = 0, e = SubList.size(); i != e; ++i) {
201 CodeGenRegister *SR = RegBank.getReg(SubList[i]);
202 const SubRegMap &Map = SR->getSubRegs(RegBank);
204 // Add this as a super-register of SR now all sub-registers are in the list.
205 // This creates a topological ordering, the exact order depends on the
206 // order getSubRegs is called on all registers.
207 SR->SuperRegs.push_back(this);
209 for (SubRegMap::const_iterator SI = Map.begin(), SE = Map.end(); SI != SE;
211 if (!SubRegs.insert(*SI).second)
212 Orphans.insert(SI->second);
214 // Noop sub-register indexes are possible, so avoid duplicates.
215 if (SI->second != SR)
216 SI->second->SuperRegs.push_back(this);
220 // Expand any composed subreg indices.
221 // If dsub_2 has ComposedOf = [qsub_1, dsub_0], and this register has a
222 // qsub_1 subreg, add a dsub_2 subreg. Keep growing Indices and process
223 // expanded subreg indices recursively.
224 for (unsigned i = 0; i != Indices.size(); ++i) {
225 CodeGenSubRegIndex *Idx = Indices[i];
226 const CodeGenSubRegIndex::CompMap &Comps = Idx->getComposites();
227 CodeGenRegister *SR = SubRegs[Idx];
228 const SubRegMap &Map = SR->getSubRegs(RegBank);
230 // Look at the possible compositions of Idx.
231 // They may not all be supported by SR.
232 for (CodeGenSubRegIndex::CompMap::const_iterator I = Comps.begin(),
233 E = Comps.end(); I != E; ++I) {
234 SubRegMap::const_iterator SRI = Map.find(I->first);
235 if (SRI == Map.end())
236 continue; // Idx + I->first doesn't exist in SR.
237 // Add I->second as a name for the subreg SRI->second, assuming it is
238 // orphaned, and the name isn't already used for something else.
239 if (SubRegs.count(I->second) || !Orphans.erase(SRI->second))
241 // We found a new name for the orphaned sub-register.
242 SubRegs.insert(std::make_pair(I->second, SRI->second));
243 Indices.push_back(I->second);
247 // Process the composites.
248 ListInit *Comps = TheDef->getValueAsListInit("CompositeIndices");
249 for (unsigned i = 0, e = Comps->size(); i != e; ++i) {
250 DagInit *Pat = dynamic_cast<DagInit*>(Comps->getElement(i));
252 throw TGError(TheDef->getLoc(), "Invalid dag '" +
253 Comps->getElement(i)->getAsString() +
254 "' in CompositeIndices");
255 DefInit *BaseIdxInit = dynamic_cast<DefInit*>(Pat->getOperator());
256 if (!BaseIdxInit || !BaseIdxInit->getDef()->isSubClassOf("SubRegIndex"))
257 throw TGError(TheDef->getLoc(), "Invalid SubClassIndex in " +
259 CodeGenSubRegIndex *BaseIdx = RegBank.getSubRegIdx(BaseIdxInit->getDef());
261 // Resolve list of subreg indices into R2.
262 CodeGenRegister *R2 = this;
263 for (DagInit::const_arg_iterator di = Pat->arg_begin(),
264 de = Pat->arg_end(); di != de; ++di) {
265 DefInit *IdxInit = dynamic_cast<DefInit*>(*di);
266 if (!IdxInit || !IdxInit->getDef()->isSubClassOf("SubRegIndex"))
267 throw TGError(TheDef->getLoc(), "Invalid SubClassIndex in " +
269 CodeGenSubRegIndex *Idx = RegBank.getSubRegIdx(IdxInit->getDef());
270 const SubRegMap &R2Subs = R2->getSubRegs(RegBank);
271 SubRegMap::const_iterator ni = R2Subs.find(Idx);
272 if (ni == R2Subs.end())
273 throw TGError(TheDef->getLoc(), "Composite " + Pat->getAsString() +
274 " refers to bad index in " + R2->getName());
278 // Insert composite index. Allow overriding inherited indices etc.
279 SubRegs[BaseIdx] = R2;
281 // R2 is no longer an orphan.
285 // Now Orphans contains the inherited subregisters without a direct index.
286 // Create inferred indexes for all missing entries.
287 // Work backwards in the Indices vector in order to compose subregs bottom-up.
288 // Consider this subreg sequence:
290 // qsub_1 -> dsub_0 -> ssub_0
292 // The qsub_1 -> dsub_0 composition becomes dsub_2, so the ssub_0 register
293 // can be reached in two different ways:
298 // We pick the latter composition because another register may have [dsub_0,
299 // dsub_1, dsub_2] subregs without neccessarily having a qsub_1 subreg. The
300 // dsub_2 -> ssub_0 composition can be shared.
301 while (!Indices.empty() && !Orphans.empty()) {
302 CodeGenSubRegIndex *Idx = Indices.pop_back_val();
303 CodeGenRegister *SR = SubRegs[Idx];
304 const SubRegMap &Map = SR->getSubRegs(RegBank);
305 for (SubRegMap::const_iterator SI = Map.begin(), SE = Map.end(); SI != SE;
307 if (Orphans.erase(SI->second))
308 SubRegs[RegBank.getCompositeSubRegIndex(Idx, SI->first)] = SI->second;
311 // Initialize RegUnitList. A register with no subregisters creates its own
312 // unit. Otherwise, it inherits all its subregister's units. Because
313 // getSubRegs is called recursively, this processes the register hierarchy in
316 // TODO: We currently assume all register units correspond to a named "leaf"
317 // register. We should also unify register units for ad-hoc register
318 // aliases. This can be done by iteratively merging units for aliasing
319 // registers using a worklist.
320 assert(RegUnits.empty() && "Should only initialize RegUnits once");
322 RegUnits.push_back(RegBank.newRegUnit(0));
324 inheritRegUnits(RegBank);
329 CodeGenRegister::addSubRegsPreOrder(SetVector<const CodeGenRegister*> &OSet,
330 CodeGenRegBank &RegBank) const {
331 assert(SubRegsComplete && "Must precompute sub-registers");
332 std::vector<Record*> Indices = TheDef->getValueAsListOfDefs("SubRegIndices");
333 for (unsigned i = 0, e = Indices.size(); i != e; ++i) {
334 CodeGenSubRegIndex *Idx = RegBank.getSubRegIdx(Indices[i]);
335 CodeGenRegister *SR = SubRegs.find(Idx)->second;
337 SR->addSubRegsPreOrder(OSet, RegBank);
341 // Get the sum of this register's unit weights.
342 unsigned CodeGenRegister::getWeight(const CodeGenRegBank &RegBank) const {
344 for (RegUnitList::const_iterator I = RegUnits.begin(), E = RegUnits.end();
346 Weight += RegBank.getRegUnitWeight(*I);
351 //===----------------------------------------------------------------------===//
353 //===----------------------------------------------------------------------===//
355 // A RegisterTuples def is used to generate pseudo-registers from lists of
356 // sub-registers. We provide a SetTheory expander class that returns the new
359 struct TupleExpander : SetTheory::Expander {
360 void expand(SetTheory &ST, Record *Def, SetTheory::RecSet &Elts) {
361 std::vector<Record*> Indices = Def->getValueAsListOfDefs("SubRegIndices");
362 unsigned Dim = Indices.size();
363 ListInit *SubRegs = Def->getValueAsListInit("SubRegs");
364 if (Dim != SubRegs->getSize())
365 throw TGError(Def->getLoc(), "SubRegIndices and SubRegs size mismatch");
367 throw TGError(Def->getLoc(), "Tuples must have at least 2 sub-registers");
369 // Evaluate the sub-register lists to be zipped.
370 unsigned Length = ~0u;
371 SmallVector<SetTheory::RecSet, 4> Lists(Dim);
372 for (unsigned i = 0; i != Dim; ++i) {
373 ST.evaluate(SubRegs->getElement(i), Lists[i]);
374 Length = std::min(Length, unsigned(Lists[i].size()));
380 // Precompute some types.
381 Record *RegisterCl = Def->getRecords().getClass("Register");
382 RecTy *RegisterRecTy = RecordRecTy::get(RegisterCl);
383 StringInit *BlankName = StringInit::get("");
386 for (unsigned n = 0; n != Length; ++n) {
388 Record *Proto = Lists[0][n];
389 std::vector<Init*> Tuple;
390 unsigned CostPerUse = 0;
391 for (unsigned i = 0; i != Dim; ++i) {
392 Record *Reg = Lists[i][n];
394 Name += Reg->getName();
395 Tuple.push_back(DefInit::get(Reg));
396 CostPerUse = std::max(CostPerUse,
397 unsigned(Reg->getValueAsInt("CostPerUse")));
400 // Create a new Record representing the synthesized register. This record
401 // is only for consumption by CodeGenRegister, it is not added to the
403 Record *NewReg = new Record(Name, Def->getLoc(), Def->getRecords());
406 // Copy Proto super-classes.
407 for (unsigned i = 0, e = Proto->getSuperClasses().size(); i != e; ++i)
408 NewReg->addSuperClass(Proto->getSuperClasses()[i]);
410 // Copy Proto fields.
411 for (unsigned i = 0, e = Proto->getValues().size(); i != e; ++i) {
412 RecordVal RV = Proto->getValues()[i];
414 // Skip existing fields, like NAME.
415 if (NewReg->getValue(RV.getNameInit()))
418 StringRef Field = RV.getName();
420 // Replace the sub-register list with Tuple.
421 if (Field == "SubRegs")
422 RV.setValue(ListInit::get(Tuple, RegisterRecTy));
424 // Provide a blank AsmName. MC hacks are required anyway.
425 if (Field == "AsmName")
426 RV.setValue(BlankName);
428 // CostPerUse is aggregated from all Tuple members.
429 if (Field == "CostPerUse")
430 RV.setValue(IntInit::get(CostPerUse));
432 // Composite registers are always covered by sub-registers.
433 if (Field == "CoveredBySubRegs")
434 RV.setValue(BitInit::get(true));
436 // Copy fields from the RegisterTuples def.
437 if (Field == "SubRegIndices" ||
438 Field == "CompositeIndices") {
439 NewReg->addValue(*Def->getValue(Field));
443 // Some fields get their default uninitialized value.
444 if (Field == "DwarfNumbers" ||
445 Field == "DwarfAlias" ||
446 Field == "Aliases") {
447 if (const RecordVal *DefRV = RegisterCl->getValue(Field))
448 NewReg->addValue(*DefRV);
452 // Everything else is copied from Proto.
453 NewReg->addValue(RV);
460 //===----------------------------------------------------------------------===//
461 // CodeGenRegisterClass
462 //===----------------------------------------------------------------------===//
464 CodeGenRegisterClass::CodeGenRegisterClass(CodeGenRegBank &RegBank, Record *R)
465 : TheDef(R), Name(R->getName()), EnumValue(-1) {
466 // Rename anonymous register classes.
467 if (R->getName().size() > 9 && R->getName()[9] == '.') {
468 static unsigned AnonCounter = 0;
469 R->setName("AnonRegClass_"+utostr(AnonCounter++));
472 std::vector<Record*> TypeList = R->getValueAsListOfDefs("RegTypes");
473 for (unsigned i = 0, e = TypeList.size(); i != e; ++i) {
474 Record *Type = TypeList[i];
475 if (!Type->isSubClassOf("ValueType"))
476 throw "RegTypes list member '" + Type->getName() +
477 "' does not derive from the ValueType class!";
478 VTs.push_back(getValueType(Type));
480 assert(!VTs.empty() && "RegisterClass must contain at least one ValueType!");
482 // Allocation order 0 is the full set. AltOrders provides others.
483 const SetTheory::RecVec *Elements = RegBank.getSets().expand(R);
484 ListInit *AltOrders = R->getValueAsListInit("AltOrders");
485 Orders.resize(1 + AltOrders->size());
487 // Default allocation order always contains all registers.
488 for (unsigned i = 0, e = Elements->size(); i != e; ++i) {
489 Orders[0].push_back((*Elements)[i]);
490 Members.insert(RegBank.getReg((*Elements)[i]));
493 // Alternative allocation orders may be subsets.
494 SetTheory::RecSet Order;
495 for (unsigned i = 0, e = AltOrders->size(); i != e; ++i) {
496 RegBank.getSets().evaluate(AltOrders->getElement(i), Order);
497 Orders[1 + i].append(Order.begin(), Order.end());
498 // Verify that all altorder members are regclass members.
499 while (!Order.empty()) {
500 CodeGenRegister *Reg = RegBank.getReg(Order.back());
503 throw TGError(R->getLoc(), " AltOrder register " + Reg->getName() +
504 " is not a class member");
508 // SubRegClasses is a list<dag> containing (RC, subregindex, ...) dags.
509 ListInit *SRC = R->getValueAsListInit("SubRegClasses");
510 for (ListInit::const_iterator i = SRC->begin(), e = SRC->end(); i != e; ++i) {
511 DagInit *DAG = dynamic_cast<DagInit*>(*i);
512 if (!DAG) throw "SubRegClasses must contain DAGs";
513 DefInit *DAGOp = dynamic_cast<DefInit*>(DAG->getOperator());
515 if (!DAGOp || !(RCRec = DAGOp->getDef())->isSubClassOf("RegisterClass"))
516 throw "Operator '" + DAG->getOperator()->getAsString() +
517 "' in SubRegClasses is not a RegisterClass";
518 // Iterate over args, all SubRegIndex instances.
519 for (DagInit::const_arg_iterator ai = DAG->arg_begin(), ae = DAG->arg_end();
521 DefInit *Idx = dynamic_cast<DefInit*>(*ai);
523 if (!Idx || !(IdxRec = Idx->getDef())->isSubClassOf("SubRegIndex"))
524 throw "Argument '" + (*ai)->getAsString() +
525 "' in SubRegClasses is not a SubRegIndex";
526 if (!SubRegClasses.insert(std::make_pair(IdxRec, RCRec)).second)
527 throw "SubRegIndex '" + IdxRec->getName() + "' mentioned twice";
531 // Allow targets to override the size in bits of the RegisterClass.
532 unsigned Size = R->getValueAsInt("Size");
534 Namespace = R->getValueAsString("Namespace");
535 SpillSize = Size ? Size : EVT(VTs[0]).getSizeInBits();
536 SpillAlignment = R->getValueAsInt("Alignment");
537 CopyCost = R->getValueAsInt("CopyCost");
538 Allocatable = R->getValueAsBit("isAllocatable");
539 AltOrderSelect = R->getValueAsString("AltOrderSelect");
542 // Create an inferred register class that was missing from the .td files.
543 // Most properties will be inherited from the closest super-class after the
544 // class structure has been computed.
545 CodeGenRegisterClass::CodeGenRegisterClass(StringRef Name, Key Props)
546 : Members(*Props.Members),
550 SpillSize(Props.SpillSize),
551 SpillAlignment(Props.SpillAlignment),
556 // Compute inherited propertied for a synthesized register class.
557 void CodeGenRegisterClass::inheritProperties(CodeGenRegBank &RegBank) {
558 assert(!getDef() && "Only synthesized classes can inherit properties");
559 assert(!SuperClasses.empty() && "Synthesized class without super class");
561 // The last super-class is the smallest one.
562 CodeGenRegisterClass &Super = *SuperClasses.back();
564 // Most properties are copied directly.
565 // Exceptions are members, size, and alignment
566 Namespace = Super.Namespace;
568 CopyCost = Super.CopyCost;
569 Allocatable = Super.Allocatable;
570 AltOrderSelect = Super.AltOrderSelect;
572 // Copy all allocation orders, filter out foreign registers from the larger
574 Orders.resize(Super.Orders.size());
575 for (unsigned i = 0, ie = Super.Orders.size(); i != ie; ++i)
576 for (unsigned j = 0, je = Super.Orders[i].size(); j != je; ++j)
577 if (contains(RegBank.getReg(Super.Orders[i][j])))
578 Orders[i].push_back(Super.Orders[i][j]);
581 bool CodeGenRegisterClass::contains(const CodeGenRegister *Reg) const {
582 return Members.count(Reg);
586 raw_ostream &operator<<(raw_ostream &OS, const CodeGenRegisterClass::Key &K) {
587 OS << "{ S=" << K.SpillSize << ", A=" << K.SpillAlignment;
588 for (CodeGenRegister::Set::const_iterator I = K.Members->begin(),
589 E = K.Members->end(); I != E; ++I)
590 OS << ", " << (*I)->getName();
595 // This is a simple lexicographical order that can be used to search for sets.
596 // It is not the same as the topological order provided by TopoOrderRC.
597 bool CodeGenRegisterClass::Key::
598 operator<(const CodeGenRegisterClass::Key &B) const {
599 assert(Members && B.Members);
600 if (*Members != *B.Members)
601 return *Members < *B.Members;
602 if (SpillSize != B.SpillSize)
603 return SpillSize < B.SpillSize;
604 return SpillAlignment < B.SpillAlignment;
607 // Returns true if RC is a strict subclass.
608 // RC is a sub-class of this class if it is a valid replacement for any
609 // instruction operand where a register of this classis required. It must
610 // satisfy these conditions:
612 // 1. All RC registers are also in this.
613 // 2. The RC spill size must not be smaller than our spill size.
614 // 3. RC spill alignment must be compatible with ours.
616 static bool testSubClass(const CodeGenRegisterClass *A,
617 const CodeGenRegisterClass *B) {
618 return A->SpillAlignment && B->SpillAlignment % A->SpillAlignment == 0 &&
619 A->SpillSize <= B->SpillSize &&
620 std::includes(A->getMembers().begin(), A->getMembers().end(),
621 B->getMembers().begin(), B->getMembers().end(),
622 CodeGenRegister::Less());
625 /// Sorting predicate for register classes. This provides a topological
626 /// ordering that arranges all register classes before their sub-classes.
628 /// Register classes with the same registers, spill size, and alignment form a
629 /// clique. They will be ordered alphabetically.
631 static int TopoOrderRC(const void *PA, const void *PB) {
632 const CodeGenRegisterClass *A = *(const CodeGenRegisterClass* const*)PA;
633 const CodeGenRegisterClass *B = *(const CodeGenRegisterClass* const*)PB;
637 // Order by descending set size. Note that the classes' allocation order may
638 // not have been computed yet. The Members set is always vaild.
639 if (A->getMembers().size() > B->getMembers().size())
641 if (A->getMembers().size() < B->getMembers().size())
644 // Order by ascending spill size.
645 if (A->SpillSize < B->SpillSize)
647 if (A->SpillSize > B->SpillSize)
650 // Order by ascending spill alignment.
651 if (A->SpillAlignment < B->SpillAlignment)
653 if (A->SpillAlignment > B->SpillAlignment)
656 // Finally order by name as a tie breaker.
657 return StringRef(A->getName()).compare(B->getName());
660 std::string CodeGenRegisterClass::getQualifiedName() const {
661 if (Namespace.empty())
664 return Namespace + "::" + getName();
667 // Compute sub-classes of all register classes.
668 // Assume the classes are ordered topologically.
669 void CodeGenRegisterClass::computeSubClasses(CodeGenRegBank &RegBank) {
670 ArrayRef<CodeGenRegisterClass*> RegClasses = RegBank.getRegClasses();
672 // Visit backwards so sub-classes are seen first.
673 for (unsigned rci = RegClasses.size(); rci; --rci) {
674 CodeGenRegisterClass &RC = *RegClasses[rci - 1];
675 RC.SubClasses.resize(RegClasses.size());
676 RC.SubClasses.set(RC.EnumValue);
678 // Normally, all subclasses have IDs >= rci, unless RC is part of a clique.
679 for (unsigned s = rci; s != RegClasses.size(); ++s) {
680 if (RC.SubClasses.test(s))
682 CodeGenRegisterClass *SubRC = RegClasses[s];
683 if (!testSubClass(&RC, SubRC))
685 // SubRC is a sub-class. Grap all its sub-classes so we won't have to
687 RC.SubClasses |= SubRC->SubClasses;
690 // Sweep up missed clique members. They will be immediately preceeding RC.
691 for (unsigned s = rci - 1; s && testSubClass(&RC, RegClasses[s - 1]); --s)
692 RC.SubClasses.set(s - 1);
695 // Compute the SuperClasses lists from the SubClasses vectors.
696 for (unsigned rci = 0; rci != RegClasses.size(); ++rci) {
697 const BitVector &SC = RegClasses[rci]->getSubClasses();
698 for (int s = SC.find_first(); s >= 0; s = SC.find_next(s)) {
699 if (unsigned(s) == rci)
701 RegClasses[s]->SuperClasses.push_back(RegClasses[rci]);
705 // With the class hierarchy in place, let synthesized register classes inherit
706 // properties from their closest super-class. The iteration order here can
707 // propagate properties down multiple levels.
708 for (unsigned rci = 0; rci != RegClasses.size(); ++rci)
709 if (!RegClasses[rci]->getDef())
710 RegClasses[rci]->inheritProperties(RegBank);
714 CodeGenRegisterClass::getSuperRegClasses(CodeGenSubRegIndex *SubIdx,
715 BitVector &Out) const {
716 DenseMap<CodeGenSubRegIndex*,
717 SmallPtrSet<CodeGenRegisterClass*, 8> >::const_iterator
718 FindI = SuperRegClasses.find(SubIdx);
719 if (FindI == SuperRegClasses.end())
721 for (SmallPtrSet<CodeGenRegisterClass*, 8>::const_iterator I =
722 FindI->second.begin(), E = FindI->second.end(); I != E; ++I)
723 Out.set((*I)->EnumValue);
726 // Populate a unique sorted list of units from a register set.
727 void CodeGenRegisterClass::buildRegUnitSet(
728 std::vector<unsigned> &RegUnits) const {
729 std::vector<unsigned> TmpUnits;
730 for (RegUnitIterator UnitI(Members); UnitI.isValid(); ++UnitI)
731 TmpUnits.push_back(*UnitI);
732 std::sort(TmpUnits.begin(), TmpUnits.end());
733 std::unique_copy(TmpUnits.begin(), TmpUnits.end(),
734 std::back_inserter(RegUnits));
737 //===----------------------------------------------------------------------===//
739 //===----------------------------------------------------------------------===//
741 CodeGenRegBank::CodeGenRegBank(RecordKeeper &Records) : Records(Records) {
742 // Configure register Sets to understand register classes and tuples.
743 Sets.addFieldExpander("RegisterClass", "MemberList");
744 Sets.addFieldExpander("CalleeSavedRegs", "SaveList");
745 Sets.addExpander("RegisterTuples", new TupleExpander());
747 // Read in the user-defined (named) sub-register indices.
748 // More indices will be synthesized later.
749 std::vector<Record*> SRIs = Records.getAllDerivedDefinitions("SubRegIndex");
750 std::sort(SRIs.begin(), SRIs.end(), LessRecord());
751 NumNamedIndices = SRIs.size();
752 for (unsigned i = 0, e = SRIs.size(); i != e; ++i)
753 getSubRegIdx(SRIs[i]);
754 // Build composite maps from ComposedOf fields.
755 for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i)
756 SubRegIndices[i]->updateComponents(*this);
758 // Read in the register definitions.
759 std::vector<Record*> Regs = Records.getAllDerivedDefinitions("Register");
760 std::sort(Regs.begin(), Regs.end(), LessRecord());
761 Registers.reserve(Regs.size());
762 // Assign the enumeration values.
763 for (unsigned i = 0, e = Regs.size(); i != e; ++i)
766 // Expand tuples and number the new registers.
767 std::vector<Record*> Tups =
768 Records.getAllDerivedDefinitions("RegisterTuples");
769 for (unsigned i = 0, e = Tups.size(); i != e; ++i) {
770 const std::vector<Record*> *TupRegs = Sets.expand(Tups[i]);
771 for (unsigned j = 0, je = TupRegs->size(); j != je; ++j)
772 getReg((*TupRegs)[j]);
775 // Precompute all sub-register maps now all the registers are known.
776 // This will create Composite entries for all inferred sub-register indices.
778 for (unsigned i = 0, e = Registers.size(); i != e; ++i)
779 Registers[i]->getSubRegs(*this);
781 // Native register units are associated with a leaf register. They've all been
783 NumNativeRegUnits = NumRegUnits;
785 // Read in register class definitions.
786 std::vector<Record*> RCs = Records.getAllDerivedDefinitions("RegisterClass");
788 throw std::string("No 'RegisterClass' subclasses defined!");
790 // Allocate user-defined register classes.
791 RegClasses.reserve(RCs.size());
792 for (unsigned i = 0, e = RCs.size(); i != e; ++i)
793 addToMaps(new CodeGenRegisterClass(*this, RCs[i]));
795 // Infer missing classes to create a full algebra.
796 computeInferredRegisterClasses();
798 // Order register classes topologically and assign enum values.
799 array_pod_sort(RegClasses.begin(), RegClasses.end(), TopoOrderRC);
800 for (unsigned i = 0, e = RegClasses.size(); i != e; ++i)
801 RegClasses[i]->EnumValue = i;
802 CodeGenRegisterClass::computeSubClasses(*this);
805 CodeGenSubRegIndex *CodeGenRegBank::getSubRegIdx(Record *Def) {
806 CodeGenSubRegIndex *&Idx = Def2SubRegIdx[Def];
809 Idx = new CodeGenSubRegIndex(Def, SubRegIndices.size() + 1);
810 SubRegIndices.push_back(Idx);
814 CodeGenRegister *CodeGenRegBank::getReg(Record *Def) {
815 CodeGenRegister *&Reg = Def2Reg[Def];
818 Reg = new CodeGenRegister(Def, Registers.size() + 1);
819 Registers.push_back(Reg);
823 void CodeGenRegBank::addToMaps(CodeGenRegisterClass *RC) {
824 RegClasses.push_back(RC);
826 if (Record *Def = RC->getDef())
827 Def2RC.insert(std::make_pair(Def, RC));
829 // Duplicate classes are rejected by insert().
830 // That's OK, we only care about the properties handled by CGRC::Key.
831 CodeGenRegisterClass::Key K(*RC);
832 Key2RC.insert(std::make_pair(K, RC));
835 // Create a synthetic sub-class if it is missing.
836 CodeGenRegisterClass*
837 CodeGenRegBank::getOrCreateSubClass(const CodeGenRegisterClass *RC,
838 const CodeGenRegister::Set *Members,
840 // Synthetic sub-class has the same size and alignment as RC.
841 CodeGenRegisterClass::Key K(Members, RC->SpillSize, RC->SpillAlignment);
842 RCKeyMap::const_iterator FoundI = Key2RC.find(K);
843 if (FoundI != Key2RC.end())
844 return FoundI->second;
846 // Sub-class doesn't exist, create a new one.
847 CodeGenRegisterClass *NewRC = new CodeGenRegisterClass(Name, K);
852 CodeGenRegisterClass *CodeGenRegBank::getRegClass(Record *Def) {
853 if (CodeGenRegisterClass *RC = Def2RC[Def])
856 throw TGError(Def->getLoc(), "Not a known RegisterClass!");
860 CodeGenRegBank::getCompositeSubRegIndex(CodeGenSubRegIndex *A,
861 CodeGenSubRegIndex *B) {
862 // Look for an existing entry.
863 CodeGenSubRegIndex *Comp = A->compose(B);
867 // None exists, synthesize one.
868 std::string Name = A->getName() + "_then_" + B->getName();
869 Comp = getSubRegIdx(new Record(Name, SMLoc(), Records));
870 A->addComposite(B, Comp);
874 void CodeGenRegBank::computeComposites() {
875 for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
876 CodeGenRegister *Reg1 = Registers[i];
877 const CodeGenRegister::SubRegMap &SRM1 = Reg1->getSubRegs();
878 for (CodeGenRegister::SubRegMap::const_iterator i1 = SRM1.begin(),
879 e1 = SRM1.end(); i1 != e1; ++i1) {
880 CodeGenSubRegIndex *Idx1 = i1->first;
881 CodeGenRegister *Reg2 = i1->second;
882 // Ignore identity compositions.
885 const CodeGenRegister::SubRegMap &SRM2 = Reg2->getSubRegs();
886 // Try composing Idx1 with another SubRegIndex.
887 for (CodeGenRegister::SubRegMap::const_iterator i2 = SRM2.begin(),
888 e2 = SRM2.end(); i2 != e2; ++i2) {
889 CodeGenSubRegIndex *Idx2 = i2->first;
890 CodeGenRegister *Reg3 = i2->second;
891 // Ignore identity compositions.
894 // OK Reg1:IdxPair == Reg3. Find the index with Reg:Idx == Reg3.
895 for (CodeGenRegister::SubRegMap::const_iterator i1d = SRM1.begin(),
896 e1d = SRM1.end(); i1d != e1d; ++i1d) {
897 if (i1d->second == Reg3) {
898 // Conflicting composition? Emit a warning but allow it.
899 if (CodeGenSubRegIndex *Prev = Idx1->addComposite(Idx2, i1d->first))
900 PrintWarning(Twine("SubRegIndex") + Idx1->getQualifiedName() +
901 " and " + Idx2->getQualifiedName() +
902 " compose ambiguously as " + Prev->getQualifiedName() +
903 " or " + i1d->first->getQualifiedName());
910 // We don't care about the difference between (Idx1, Idx2) -> Idx2 and invalid
911 // compositions, so remove any mappings of that form.
912 for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i)
913 SubRegIndices[i]->cleanComposites();
917 // UberRegSet is a helper class for computeRegUnitWeights. Each UberRegSet is
918 // the transitive closure of the union of overlapping register
919 // classes. Together, the UberRegSets form a partition of the registers. If we
920 // consider overlapping register classes to be connected, then each UberRegSet
921 // is a set of connected components.
923 // An UberRegSet will likely be a horizontal slice of register names of
924 // the same width. Nontrivial subregisters should then be in a separate
925 // UberRegSet. But this property isn't required for valid computation of
926 // register unit weights.
928 // A Weight field caches the max per-register unit weight in each UberRegSet.
930 // A set of SingularDeterminants flags single units of some register in this set
931 // for which the unit weight equals the set weight. These units should not have
932 // their weight increased.
934 CodeGenRegister::Set Regs;
936 CodeGenRegister::RegUnitList SingularDeterminants;
938 UberRegSet(): Weight(0) {}
942 // Partition registers into UberRegSets, where each set is the transitive
943 // closure of the union of overlapping register classes.
945 // UberRegSets[0] is a special non-allocatable set.
946 static void computeUberSets(std::vector<UberRegSet> &UberSets,
947 std::vector<UberRegSet*> &RegSets,
948 CodeGenRegBank &RegBank) {
950 const std::vector<CodeGenRegister*> &Registers = RegBank.getRegisters();
952 // The Register EnumValue is one greater than its index into Registers.
953 assert(Registers.size() == Registers[Registers.size()-1]->EnumValue &&
954 "register enum value mismatch");
956 // For simplicitly make the SetID the same as EnumValue.
957 IntEqClasses UberSetIDs(Registers.size()+1);
958 std::set<unsigned> AllocatableRegs;
959 for (unsigned i = 0, e = RegBank.getRegClasses().size(); i != e; ++i) {
961 CodeGenRegisterClass *RegClass = RegBank.getRegClasses()[i];
962 if (!RegClass->Allocatable)
965 const CodeGenRegister::Set &Regs = RegClass->getMembers();
969 unsigned USetID = UberSetIDs.findLeader((*Regs.begin())->EnumValue);
970 assert(USetID && "register number 0 is invalid");
972 AllocatableRegs.insert((*Regs.begin())->EnumValue);
973 for (CodeGenRegister::Set::const_iterator I = llvm::next(Regs.begin()),
974 E = Regs.end(); I != E; ++I) {
975 AllocatableRegs.insert((*I)->EnumValue);
976 UberSetIDs.join(USetID, (*I)->EnumValue);
979 // Combine non-allocatable regs.
980 for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
981 unsigned RegNum = Registers[i]->EnumValue;
982 if (AllocatableRegs.count(RegNum))
985 UberSetIDs.join(0, RegNum);
987 UberSetIDs.compress();
989 // Make the first UberSet a special unallocatable set.
990 unsigned ZeroID = UberSetIDs[0];
992 // Insert Registers into the UberSets formed by union-find.
993 // Do not resize after this.
994 UberSets.resize(UberSetIDs.getNumClasses());
995 for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
996 const CodeGenRegister *Reg = Registers[i];
997 unsigned USetID = UberSetIDs[Reg->EnumValue];
1000 else if (USetID == ZeroID)
1003 UberRegSet *USet = &UberSets[USetID];
1004 USet->Regs.insert(Reg);
1009 // Recompute each UberSet weight after changing unit weights.
1010 static void computeUberWeights(std::vector<UberRegSet> &UberSets,
1011 CodeGenRegBank &RegBank) {
1012 // Skip the first unallocatable set.
1013 for (std::vector<UberRegSet>::iterator I = llvm::next(UberSets.begin()),
1014 E = UberSets.end(); I != E; ++I) {
1016 // Initialize all unit weights in this set, and remember the max units/reg.
1017 const CodeGenRegister *Reg = 0;
1018 unsigned MaxWeight = 0, Weight = 0;
1019 for (RegUnitIterator UnitI(I->Regs); UnitI.isValid(); ++UnitI) {
1020 if (Reg != UnitI.getReg()) {
1021 if (Weight > MaxWeight)
1023 Reg = UnitI.getReg();
1026 unsigned UWeight = RegBank.getRegUnitWeight(*UnitI);
1029 RegBank.increaseRegUnitWeight(*UnitI, UWeight);
1033 if (Weight > MaxWeight)
1036 // Update the set weight.
1037 I->Weight = MaxWeight;
1039 // Find singular determinants.
1040 for (CodeGenRegister::Set::iterator RegI = I->Regs.begin(),
1041 RegE = I->Regs.end(); RegI != RegE; ++RegI) {
1042 if ((*RegI)->getRegUnits().size() == 1
1043 && (*RegI)->getWeight(RegBank) == I->Weight)
1044 mergeRegUnits(I->SingularDeterminants, (*RegI)->getRegUnits());
1049 // normalizeWeight is a computeRegUnitWeights helper that adjusts the weight of
1050 // a register and its subregisters so that they have the same weight as their
1051 // UberSet. Self-recursion processes the subregister tree in postorder so
1052 // subregisters are normalized first.
1055 // - creates new adopted register units
1056 // - causes superregisters to inherit adopted units
1057 // - increases the weight of "singular" units
1058 // - induces recomputation of UberWeights.
1059 static bool normalizeWeight(CodeGenRegister *Reg,
1060 std::vector<UberRegSet> &UberSets,
1061 std::vector<UberRegSet*> &RegSets,
1062 CodeGenRegister::RegUnitList &NormalUnits,
1063 CodeGenRegBank &RegBank) {
1064 bool Changed = false;
1065 const CodeGenRegister::SubRegMap &SRM = Reg->getSubRegs();
1066 for (CodeGenRegister::SubRegMap::const_iterator SRI = SRM.begin(),
1067 SRE = SRM.end(); SRI != SRE; ++SRI) {
1068 if (SRI->second == Reg)
1069 continue; // self-cycles happen
1072 normalizeWeight(SRI->second, UberSets, RegSets, NormalUnits, RegBank);
1074 // Postorder register normalization.
1076 // Inherit register units newly adopted by subregisters.
1077 if (Reg->inheritRegUnits(RegBank))
1078 computeUberWeights(UberSets, RegBank);
1080 // Check if this register is too skinny for its UberRegSet.
1081 UberRegSet *UberSet = RegSets[RegBank.getRegIndex(Reg)];
1083 unsigned RegWeight = Reg->getWeight(RegBank);
1084 if (UberSet->Weight > RegWeight) {
1085 // A register unit's weight can be adjusted only if it is the singular unit
1086 // for this register, has not been used to normalize a subregister's set,
1087 // and has not already been used to singularly determine this UberRegSet.
1088 unsigned AdjustUnit = Reg->getRegUnits().front();
1089 if (Reg->getRegUnits().size() != 1
1090 || hasRegUnit(NormalUnits, AdjustUnit)
1091 || hasRegUnit(UberSet->SingularDeterminants, AdjustUnit)) {
1092 // We don't have an adjustable unit, so adopt a new one.
1093 AdjustUnit = RegBank.newRegUnit(UberSet->Weight - RegWeight);
1094 Reg->adoptRegUnit(AdjustUnit);
1095 // Adopting a unit does not immediately require recomputing set weights.
1098 // Adjust the existing single unit.
1099 RegBank.increaseRegUnitWeight(AdjustUnit, UberSet->Weight - RegWeight);
1100 // The unit may be shared among sets and registers within this set.
1101 computeUberWeights(UberSets, RegBank);
1106 // Mark these units normalized so superregisters can't change their weights.
1107 mergeRegUnits(NormalUnits, Reg->getRegUnits());
1112 // Compute a weight for each register unit created during getSubRegs.
1114 // The goal is that two registers in the same class will have the same weight,
1115 // where each register's weight is defined as sum of its units' weights.
1116 void CodeGenRegBank::computeRegUnitWeights() {
1117 assert(RegUnitWeights.empty() && "Only initialize RegUnitWeights once");
1119 // Only allocatable units will be initialized to nonzero weight.
1120 RegUnitWeights.resize(NumRegUnits);
1122 std::vector<UberRegSet> UberSets;
1123 std::vector<UberRegSet*> RegSets(Registers.size());
1124 computeUberSets(UberSets, RegSets, *this);
1125 // UberSets and RegSets are now immutable.
1127 computeUberWeights(UberSets, *this);
1129 // Iterate over each Register, normalizing the unit weights until reaching
1131 unsigned NumIters = 0;
1132 for (bool Changed = true; Changed; ++NumIters) {
1133 assert(NumIters <= NumNativeRegUnits && "Runaway register unit weights");
1135 for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
1136 CodeGenRegister::RegUnitList NormalUnits;
1138 normalizeWeight(Registers[i], UberSets, RegSets, NormalUnits, *this);
1143 // Find a set in UniqueSets with the same elements as Set.
1144 // Return an iterator into UniqueSets.
1145 static std::vector<RegUnitSet>::const_iterator
1146 findRegUnitSet(const std::vector<RegUnitSet> &UniqueSets,
1147 const RegUnitSet &Set) {
1148 std::vector<RegUnitSet>::const_iterator
1149 I = UniqueSets.begin(), E = UniqueSets.end();
1151 if (I->Units == Set.Units)
1157 // Return true if the RUSubSet is a subset of RUSuperSet.
1158 static bool isRegUnitSubSet(const std::vector<unsigned> &RUSubSet,
1159 const std::vector<unsigned> &RUSuperSet) {
1160 return std::includes(RUSuperSet.begin(), RUSuperSet.end(),
1161 RUSubSet.begin(), RUSubSet.end());
1164 // Iteratively prune unit sets.
1165 void CodeGenRegBank::pruneUnitSets() {
1166 assert(RegClassUnitSets.empty() && "this invalidates RegClassUnitSets");
1168 // Form an equivalence class of UnitSets with no significant difference.
1169 std::vector<unsigned> SuperSetIDs;
1170 for (unsigned SubIdx = 0, EndIdx = RegUnitSets.size();
1171 SubIdx != EndIdx; ++SubIdx) {
1172 const RegUnitSet &SubSet = RegUnitSets[SubIdx];
1173 unsigned SuperIdx = 0;
1174 for (; SuperIdx != EndIdx; ++SuperIdx) {
1175 if (SuperIdx == SubIdx)
1178 const RegUnitSet &SuperSet = RegUnitSets[SuperIdx];
1179 if (isRegUnitSubSet(SubSet.Units, SuperSet.Units)
1180 && (SubSet.Units.size() + 3 > SuperSet.Units.size())) {
1184 if (SuperIdx == EndIdx)
1185 SuperSetIDs.push_back(SubIdx);
1187 // Populate PrunedUnitSets with each equivalence class's superset.
1188 std::vector<RegUnitSet> PrunedUnitSets(SuperSetIDs.size());
1189 for (unsigned i = 0, e = SuperSetIDs.size(); i != e; ++i) {
1190 unsigned SuperIdx = SuperSetIDs[i];
1191 PrunedUnitSets[i].Name = RegUnitSets[SuperIdx].Name;
1192 PrunedUnitSets[i].Units.swap(RegUnitSets[SuperIdx].Units);
1194 RegUnitSets.swap(PrunedUnitSets);
1197 // Create a RegUnitSet for each RegClass that contains all units in the class
1198 // including adopted units that are necessary to model register pressure. Then
1199 // iteratively compute RegUnitSets such that the union of any two overlapping
1200 // RegUnitSets is repreresented.
1202 // RegisterInfoEmitter will map each RegClass to its RegUnitClass and any
1203 // RegUnitSet that is a superset of that RegUnitClass.
1204 void CodeGenRegBank::computeRegUnitSets() {
1206 // Compute a unique RegUnitSet for each RegClass.
1207 const ArrayRef<CodeGenRegisterClass*> &RegClasses = getRegClasses();
1208 unsigned NumRegClasses = RegClasses.size();
1209 for (unsigned RCIdx = 0, RCEnd = NumRegClasses; RCIdx != RCEnd; ++RCIdx) {
1210 if (!RegClasses[RCIdx]->Allocatable)
1213 // Speculatively grow the RegUnitSets to hold the new set.
1214 RegUnitSets.resize(RegUnitSets.size() + 1);
1215 RegUnitSets.back().Name = RegClasses[RCIdx]->getName();
1217 // Compute a sorted list of units in this class.
1218 RegClasses[RCIdx]->buildRegUnitSet(RegUnitSets.back().Units);
1220 // Find an existing RegUnitSet.
1221 std::vector<RegUnitSet>::const_iterator SetI =
1222 findRegUnitSet(RegUnitSets, RegUnitSets.back());
1223 if (SetI != llvm::prior(RegUnitSets.end()))
1224 RegUnitSets.pop_back();
1227 // Iteratively prune unit sets.
1230 // Iterate over all unit sets, including new ones added by this loop.
1231 unsigned NumRegUnitSubSets = RegUnitSets.size();
1232 for (unsigned Idx = 0, EndIdx = RegUnitSets.size(); Idx != EndIdx; ++Idx) {
1233 // In theory, this is combinatorial. In practice, it needs to be bounded
1234 // by a small number of sets for regpressure to be efficient.
1235 // If the assert is hit, we need to implement pruning.
1236 assert(Idx < (2*NumRegUnitSubSets) && "runaway unit set inference");
1238 // Compare new sets with all original classes.
1239 for (unsigned SearchIdx = (Idx >= NumRegUnitSubSets) ? 0 : Idx+1;
1240 SearchIdx != EndIdx; ++SearchIdx) {
1241 std::set<unsigned> Intersection;
1242 std::set_intersection(RegUnitSets[Idx].Units.begin(),
1243 RegUnitSets[Idx].Units.end(),
1244 RegUnitSets[SearchIdx].Units.begin(),
1245 RegUnitSets[SearchIdx].Units.end(),
1246 std::inserter(Intersection, Intersection.begin()));
1247 if (Intersection.empty())
1250 // Speculatively grow the RegUnitSets to hold the new set.
1251 RegUnitSets.resize(RegUnitSets.size() + 1);
1252 RegUnitSets.back().Name =
1253 RegUnitSets[Idx].Name + "+" + RegUnitSets[SearchIdx].Name;
1255 std::set_union(RegUnitSets[Idx].Units.begin(),
1256 RegUnitSets[Idx].Units.end(),
1257 RegUnitSets[SearchIdx].Units.begin(),
1258 RegUnitSets[SearchIdx].Units.end(),
1259 std::inserter(RegUnitSets.back().Units,
1260 RegUnitSets.back().Units.begin()));
1262 // Find an existing RegUnitSet, or add the union to the unique sets.
1263 std::vector<RegUnitSet>::const_iterator SetI =
1264 findRegUnitSet(RegUnitSets, RegUnitSets.back());
1265 if (SetI != llvm::prior(RegUnitSets.end()))
1266 RegUnitSets.pop_back();
1270 // Iteratively prune unit sets after inferring supersets.
1273 // For each register class, list the UnitSets that are supersets.
1274 RegClassUnitSets.resize(NumRegClasses);
1275 for (unsigned RCIdx = 0, RCEnd = NumRegClasses; RCIdx != RCEnd; ++RCIdx) {
1276 if (!RegClasses[RCIdx]->Allocatable)
1279 // Recompute the sorted list of units in this class.
1280 std::vector<unsigned> RegUnits;
1281 RegClasses[RCIdx]->buildRegUnitSet(RegUnits);
1283 // Don't increase pressure for unallocatable regclasses.
1284 if (RegUnits.empty())
1287 // Find all supersets.
1288 for (unsigned USIdx = 0, USEnd = RegUnitSets.size();
1289 USIdx != USEnd; ++USIdx) {
1290 if (isRegUnitSubSet(RegUnits, RegUnitSets[USIdx].Units))
1291 RegClassUnitSets[RCIdx].push_back(USIdx);
1293 assert(!RegClassUnitSets[RCIdx].empty() && "missing unit set for regclass");
1297 // Compute sets of overlapping registers.
1299 // The standard set is all super-registers and all sub-registers, but the
1300 // target description can add arbitrary overlapping registers via the 'Aliases'
1301 // field. This complicates things, but we can compute overlapping sets using
1302 // the following rules:
1304 // 1. The relation overlap(A, B) is reflexive and symmetric but not transitive.
1306 // 2. overlap(A, B) implies overlap(A, S) for all S in supers(B).
1310 // overlap(A, B) iff there exists:
1311 // A' in { A, subregs(A) } and B' in { B, subregs(B) } such that:
1312 // A' = B' or A' in aliases(B') or B' in aliases(A').
1314 // Here subregs(A) is the full flattened sub-register set returned by
1315 // A.getSubRegs() while aliases(A) is simply the special 'Aliases' field in the
1316 // description of register A.
1318 // This also implies that registers with a common sub-register are considered
1319 // overlapping. This can happen when forming register pairs:
1325 // In this case, we will infer an overlap between P0 and P1 because of the
1326 // shared sub-register R1. There is no overlap between P0 and P2.
1328 void CodeGenRegBank::
1329 computeOverlaps(std::map<const CodeGenRegister*, CodeGenRegister::Set> &Map) {
1330 assert(Map.empty());
1332 // Collect overlaps that don't follow from rule 2.
1333 for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
1334 CodeGenRegister *Reg = Registers[i];
1335 CodeGenRegister::Set &Overlaps = Map[Reg];
1337 // Reg overlaps itself.
1338 Overlaps.insert(Reg);
1340 // All super-registers overlap.
1341 const CodeGenRegister::SuperRegList &Supers = Reg->getSuperRegs();
1342 Overlaps.insert(Supers.begin(), Supers.end());
1344 // Form symmetrical relations from the special Aliases[] lists.
1345 std::vector<Record*> RegList = Reg->TheDef->getValueAsListOfDefs("Aliases");
1346 for (unsigned i2 = 0, e2 = RegList.size(); i2 != e2; ++i2) {
1347 CodeGenRegister *Reg2 = getReg(RegList[i2]);
1348 CodeGenRegister::Set &Overlaps2 = Map[Reg2];
1349 const CodeGenRegister::SuperRegList &Supers2 = Reg2->getSuperRegs();
1350 // Reg overlaps Reg2 which implies it overlaps supers(Reg2).
1351 Overlaps.insert(Reg2);
1352 Overlaps.insert(Supers2.begin(), Supers2.end());
1353 Overlaps2.insert(Reg);
1354 Overlaps2.insert(Supers.begin(), Supers.end());
1358 // Apply rule 2. and inherit all sub-register overlaps.
1359 for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
1360 CodeGenRegister *Reg = Registers[i];
1361 CodeGenRegister::Set &Overlaps = Map[Reg];
1362 const CodeGenRegister::SubRegMap &SRM = Reg->getSubRegs();
1363 for (CodeGenRegister::SubRegMap::const_iterator i2 = SRM.begin(),
1364 e2 = SRM.end(); i2 != e2; ++i2) {
1365 CodeGenRegister::Set &Overlaps2 = Map[i2->second];
1366 Overlaps.insert(Overlaps2.begin(), Overlaps2.end());
1371 void CodeGenRegBank::computeDerivedInfo() {
1372 computeComposites();
1374 // Compute a weight for each register unit created during getSubRegs.
1375 // This may create adopted register units (with unit # >= NumNativeRegUnits).
1376 computeRegUnitWeights();
1378 // Compute a unique set of RegUnitSets. One for each RegClass and inferred
1379 // supersets for the union of overlapping sets.
1380 computeRegUnitSets();
1384 // Synthesize missing register class intersections.
1386 // Make sure that sub-classes of RC exists such that getCommonSubClass(RC, X)
1387 // returns a maximal register class for all X.
1389 void CodeGenRegBank::inferCommonSubClass(CodeGenRegisterClass *RC) {
1390 for (unsigned rci = 0, rce = RegClasses.size(); rci != rce; ++rci) {
1391 CodeGenRegisterClass *RC1 = RC;
1392 CodeGenRegisterClass *RC2 = RegClasses[rci];
1396 // Compute the set intersection of RC1 and RC2.
1397 const CodeGenRegister::Set &Memb1 = RC1->getMembers();
1398 const CodeGenRegister::Set &Memb2 = RC2->getMembers();
1399 CodeGenRegister::Set Intersection;
1400 std::set_intersection(Memb1.begin(), Memb1.end(),
1401 Memb2.begin(), Memb2.end(),
1402 std::inserter(Intersection, Intersection.begin()),
1403 CodeGenRegister::Less());
1405 // Skip disjoint class pairs.
1406 if (Intersection.empty())
1409 // If RC1 and RC2 have different spill sizes or alignments, use the
1410 // larger size for sub-classing. If they are equal, prefer RC1.
1411 if (RC2->SpillSize > RC1->SpillSize ||
1412 (RC2->SpillSize == RC1->SpillSize &&
1413 RC2->SpillAlignment > RC1->SpillAlignment))
1414 std::swap(RC1, RC2);
1416 getOrCreateSubClass(RC1, &Intersection,
1417 RC1->getName() + "_and_" + RC2->getName());
1422 // Synthesize missing sub-classes for getSubClassWithSubReg().
1424 // Make sure that the set of registers in RC with a given SubIdx sub-register
1425 // form a register class. Update RC->SubClassWithSubReg.
1427 void CodeGenRegBank::inferSubClassWithSubReg(CodeGenRegisterClass *RC) {
1428 // Map SubRegIndex to set of registers in RC supporting that SubRegIndex.
1429 typedef std::map<CodeGenSubRegIndex*, CodeGenRegister::Set,
1430 CodeGenSubRegIndex::Less> SubReg2SetMap;
1432 // Compute the set of registers supporting each SubRegIndex.
1433 SubReg2SetMap SRSets;
1434 for (CodeGenRegister::Set::const_iterator RI = RC->getMembers().begin(),
1435 RE = RC->getMembers().end(); RI != RE; ++RI) {
1436 const CodeGenRegister::SubRegMap &SRM = (*RI)->getSubRegs();
1437 for (CodeGenRegister::SubRegMap::const_iterator I = SRM.begin(),
1438 E = SRM.end(); I != E; ++I)
1439 SRSets[I->first].insert(*RI);
1442 // Find matching classes for all SRSets entries. Iterate in SubRegIndex
1443 // numerical order to visit synthetic indices last.
1444 for (unsigned sri = 0, sre = SubRegIndices.size(); sri != sre; ++sri) {
1445 CodeGenSubRegIndex *SubIdx = SubRegIndices[sri];
1446 SubReg2SetMap::const_iterator I = SRSets.find(SubIdx);
1447 // Unsupported SubRegIndex. Skip it.
1448 if (I == SRSets.end())
1450 // In most cases, all RC registers support the SubRegIndex.
1451 if (I->second.size() == RC->getMembers().size()) {
1452 RC->setSubClassWithSubReg(SubIdx, RC);
1455 // This is a real subset. See if we have a matching class.
1456 CodeGenRegisterClass *SubRC =
1457 getOrCreateSubClass(RC, &I->second,
1458 RC->getName() + "_with_" + I->first->getName());
1459 RC->setSubClassWithSubReg(SubIdx, SubRC);
1464 // Synthesize missing sub-classes of RC for getMatchingSuperRegClass().
1466 // Create sub-classes of RC such that getMatchingSuperRegClass(RC, SubIdx, X)
1467 // has a maximal result for any SubIdx and any X >= FirstSubRegRC.
1470 void CodeGenRegBank::inferMatchingSuperRegClass(CodeGenRegisterClass *RC,
1471 unsigned FirstSubRegRC) {
1472 SmallVector<std::pair<const CodeGenRegister*,
1473 const CodeGenRegister*>, 16> SSPairs;
1475 // Iterate in SubRegIndex numerical order to visit synthetic indices last.
1476 for (unsigned sri = 0, sre = SubRegIndices.size(); sri != sre; ++sri) {
1477 CodeGenSubRegIndex *SubIdx = SubRegIndices[sri];
1478 // Skip indexes that aren't fully supported by RC's registers. This was
1479 // computed by inferSubClassWithSubReg() above which should have been
1481 if (RC->getSubClassWithSubReg(SubIdx) != RC)
1484 // Build list of (Super, Sub) pairs for this SubIdx.
1486 for (CodeGenRegister::Set::const_iterator RI = RC->getMembers().begin(),
1487 RE = RC->getMembers().end(); RI != RE; ++RI) {
1488 const CodeGenRegister *Super = *RI;
1489 const CodeGenRegister *Sub = Super->getSubRegs().find(SubIdx)->second;
1490 assert(Sub && "Missing sub-register");
1491 SSPairs.push_back(std::make_pair(Super, Sub));
1494 // Iterate over sub-register class candidates. Ignore classes created by
1495 // this loop. They will never be useful.
1496 for (unsigned rci = FirstSubRegRC, rce = RegClasses.size(); rci != rce;
1498 CodeGenRegisterClass *SubRC = RegClasses[rci];
1499 // Compute the subset of RC that maps into SubRC.
1500 CodeGenRegister::Set SubSet;
1501 for (unsigned i = 0, e = SSPairs.size(); i != e; ++i)
1502 if (SubRC->contains(SSPairs[i].second))
1503 SubSet.insert(SSPairs[i].first);
1506 // RC injects completely into SubRC.
1507 if (SubSet.size() == SSPairs.size()) {
1508 SubRC->addSuperRegClass(SubIdx, RC);
1511 // Only a subset of RC maps into SubRC. Make sure it is represented by a
1513 getOrCreateSubClass(RC, &SubSet, RC->getName() +
1514 "_with_" + SubIdx->getName() +
1515 "_in_" + SubRC->getName());
1522 // Infer missing register classes.
1524 void CodeGenRegBank::computeInferredRegisterClasses() {
1525 // When this function is called, the register classes have not been sorted
1526 // and assigned EnumValues yet. That means getSubClasses(),
1527 // getSuperClasses(), and hasSubClass() functions are defunct.
1528 unsigned FirstNewRC = RegClasses.size();
1530 // Visit all register classes, including the ones being added by the loop.
1531 for (unsigned rci = 0; rci != RegClasses.size(); ++rci) {
1532 CodeGenRegisterClass *RC = RegClasses[rci];
1534 // Synthesize answers for getSubClassWithSubReg().
1535 inferSubClassWithSubReg(RC);
1537 // Synthesize answers for getCommonSubClass().
1538 inferCommonSubClass(RC);
1540 // Synthesize answers for getMatchingSuperRegClass().
1541 inferMatchingSuperRegClass(RC);
1543 // New register classes are created while this loop is running, and we need
1544 // to visit all of them. I particular, inferMatchingSuperRegClass needs
1545 // to match old super-register classes with sub-register classes created
1546 // after inferMatchingSuperRegClass was called. At this point,
1547 // inferMatchingSuperRegClass has checked SuperRC = [0..rci] with SubRC =
1548 // [0..FirstNewRC). We need to cover SubRC = [FirstNewRC..rci].
1549 if (rci + 1 == FirstNewRC) {
1550 unsigned NextNewRC = RegClasses.size();
1551 for (unsigned rci2 = 0; rci2 != FirstNewRC; ++rci2)
1552 inferMatchingSuperRegClass(RegClasses[rci2], FirstNewRC);
1553 FirstNewRC = NextNewRC;
1558 /// getRegisterClassForRegister - Find the register class that contains the
1559 /// specified physical register. If the register is not in a register class,
1560 /// return null. If the register is in multiple classes, and the classes have a
1561 /// superset-subset relationship and the same set of types, return the
1562 /// superclass. Otherwise return null.
1563 const CodeGenRegisterClass*
1564 CodeGenRegBank::getRegClassForRegister(Record *R) {
1565 const CodeGenRegister *Reg = getReg(R);
1566 ArrayRef<CodeGenRegisterClass*> RCs = getRegClasses();
1567 const CodeGenRegisterClass *FoundRC = 0;
1568 for (unsigned i = 0, e = RCs.size(); i != e; ++i) {
1569 const CodeGenRegisterClass &RC = *RCs[i];
1570 if (!RC.contains(Reg))
1573 // If this is the first class that contains the register,
1574 // make a note of it and go on to the next class.
1580 // If a register's classes have different types, return null.
1581 if (RC.getValueTypes() != FoundRC->getValueTypes())
1584 // Check to see if the previously found class that contains
1585 // the register is a subclass of the current class. If so,
1586 // prefer the superclass.
1587 if (RC.hasSubClass(FoundRC)) {
1592 // Check to see if the previously found class that contains
1593 // the register is a superclass of the current class. If so,
1594 // prefer the superclass.
1595 if (FoundRC->hasSubClass(&RC))
1598 // Multiple classes, and neither is a superclass of the other.
1605 BitVector CodeGenRegBank::computeCoveredRegisters(ArrayRef<Record*> Regs) {
1606 SetVector<const CodeGenRegister*> Set;
1608 // First add Regs with all sub-registers.
1609 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
1610 CodeGenRegister *Reg = getReg(Regs[i]);
1611 if (Set.insert(Reg))
1612 // Reg is new, add all sub-registers.
1613 // The pre-ordering is not important here.
1614 Reg->addSubRegsPreOrder(Set, *this);
1617 // Second, find all super-registers that are completely covered by the set.
1618 for (unsigned i = 0; i != Set.size(); ++i) {
1619 const CodeGenRegister::SuperRegList &SR = Set[i]->getSuperRegs();
1620 for (unsigned j = 0, e = SR.size(); j != e; ++j) {
1621 const CodeGenRegister *Super = SR[j];
1622 if (!Super->CoveredBySubRegs || Set.count(Super))
1624 // This new super-register is covered by its sub-registers.
1625 bool AllSubsInSet = true;
1626 const CodeGenRegister::SubRegMap &SRM = Super->getSubRegs();
1627 for (CodeGenRegister::SubRegMap::const_iterator I = SRM.begin(),
1628 E = SRM.end(); I != E; ++I)
1629 if (!Set.count(I->second)) {
1630 AllSubsInSet = false;
1633 // All sub-registers in Set, add Super as well.
1634 // We will visit Super later to recheck its super-registers.
1640 // Convert to BitVector.
1641 BitVector BV(Registers.size() + 1);
1642 for (unsigned i = 0, e = Set.size(); i != e; ++i)
1643 BV.set(Set[i]->EnumValue);