1 //===- AsmWriterEmitter.cpp - Generate an assembly writer -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend is emits an assembly printer for the current target.
11 // Note that this is currently fairly skeletal, but will grow over time.
13 //===----------------------------------------------------------------------===//
15 #include "AsmWriterEmitter.h"
16 #include "CodeGenTarget.h"
18 #include "llvm/ADT/StringExtras.h"
19 #include "llvm/Support/Debug.h"
20 #include "llvm/Support/MathExtras.h"
25 static bool isIdentChar(char C) {
26 return (C >= 'a' && C <= 'z') ||
27 (C >= 'A' && C <= 'Z') ||
28 (C >= '0' && C <= '9') ||
33 struct AsmWriterOperand {
34 enum { isLiteralTextOperand, isMachineInstrOperand } OperandType;
36 /// Str - For isLiteralTextOperand, this IS the literal text. For
37 /// isMachineInstrOperand, this is the PrinterMethodName for the operand.
40 /// MiOpNo - For isMachineInstrOperand, this is the operand number of the
41 /// machine instruction.
44 /// MiModifier - For isMachineInstrOperand, this is the modifier string for
45 /// an operand, specified with syntax like ${opname:modifier}.
46 std::string MiModifier;
48 AsmWriterOperand(const std::string &LitStr)
49 : OperandType(isLiteralTextOperand), Str(LitStr) {}
51 AsmWriterOperand(const std::string &Printer, unsigned OpNo,
52 const std::string &Modifier)
53 : OperandType(isMachineInstrOperand), Str(Printer), MIOpNo(OpNo),
54 MiModifier(Modifier) {}
56 bool operator!=(const AsmWriterOperand &Other) const {
57 if (OperandType != Other.OperandType || Str != Other.Str) return true;
58 if (OperandType == isMachineInstrOperand)
59 return MIOpNo != Other.MIOpNo || MiModifier != Other.MiModifier;
62 bool operator==(const AsmWriterOperand &Other) const {
63 return !operator!=(Other);
66 /// getCode - Return the code that prints this operand.
67 std::string getCode() const;
72 struct AsmWriterInst {
73 std::vector<AsmWriterOperand> Operands;
74 const CodeGenInstruction *CGI;
76 AsmWriterInst(const CodeGenInstruction &CGI, unsigned Variant);
78 /// MatchesAllButOneOp - If this instruction is exactly identical to the
79 /// specified instruction except for one differing operand, return the
80 /// differing operand number. Otherwise return ~0.
81 unsigned MatchesAllButOneOp(const AsmWriterInst &Other) const;
84 void AddLiteralString(const std::string &Str) {
85 // If the last operand was already a literal text string, append this to
86 // it, otherwise add a new operand.
87 if (!Operands.empty() &&
88 Operands.back().OperandType == AsmWriterOperand::isLiteralTextOperand)
89 Operands.back().Str.append(Str);
91 Operands.push_back(AsmWriterOperand(Str));
97 std::string AsmWriterOperand::getCode() const {
98 if (OperandType == isLiteralTextOperand)
99 return "O << \"" + Str + "\"; ";
101 std::string Result = Str + "(MI, " + utostr(MIOpNo);
102 if (!MiModifier.empty())
103 Result += ", \"" + MiModifier + '"';
104 return Result + "); ";
108 /// ParseAsmString - Parse the specified Instruction's AsmString into this
111 AsmWriterInst::AsmWriterInst(const CodeGenInstruction &CGI, unsigned Variant) {
113 unsigned CurVariant = ~0U; // ~0 if we are outside a {.|.|.} region, other #.
115 // NOTE: Any extensions to this code need to be mirrored in the
116 // AsmPrinter::printInlineAsm code that executes as compile time (assuming
117 // that inline asm strings should also get the new feature)!
118 const std::string &AsmString = CGI.AsmString;
119 std::string::size_type LastEmitted = 0;
120 while (LastEmitted != AsmString.size()) {
121 std::string::size_type DollarPos =
122 AsmString.find_first_of("${|}", LastEmitted);
123 if (DollarPos == std::string::npos) DollarPos = AsmString.size();
125 // Emit a constant string fragment.
126 if (DollarPos != LastEmitted) {
127 // TODO: this should eventually handle escaping.
128 if (CurVariant == Variant || CurVariant == ~0U)
129 AddLiteralString(std::string(AsmString.begin()+LastEmitted,
130 AsmString.begin()+DollarPos));
131 LastEmitted = DollarPos;
132 } else if (AsmString[DollarPos] == '{') {
133 if (CurVariant != ~0U)
134 throw "Nested variants found for instruction '" +
135 CGI.TheDef->getName() + "'!";
136 LastEmitted = DollarPos+1;
137 CurVariant = 0; // We are now inside of the variant!
138 } else if (AsmString[DollarPos] == '|') {
139 if (CurVariant == ~0U)
140 throw "'|' character found outside of a variant in instruction '"
141 + CGI.TheDef->getName() + "'!";
144 } else if (AsmString[DollarPos] == '}') {
145 if (CurVariant == ~0U)
146 throw "'}' character found outside of a variant in instruction '"
147 + CGI.TheDef->getName() + "'!";
150 } else if (DollarPos+1 != AsmString.size() &&
151 AsmString[DollarPos+1] == '$') {
152 if (CurVariant == Variant || CurVariant == ~0U)
153 AddLiteralString("$"); // "$$" -> $
154 LastEmitted = DollarPos+2;
156 // Get the name of the variable.
157 std::string::size_type VarEnd = DollarPos+1;
159 // handle ${foo}bar as $foo by detecting whether the character following
160 // the dollar sign is a curly brace. If so, advance VarEnd and DollarPos
161 // so the variable name does not contain the leading curly brace.
162 bool hasCurlyBraces = false;
163 if (VarEnd < AsmString.size() && '{' == AsmString[VarEnd]) {
164 hasCurlyBraces = true;
169 while (VarEnd < AsmString.size() && isIdentChar(AsmString[VarEnd]))
171 std::string VarName(AsmString.begin()+DollarPos+1,
172 AsmString.begin()+VarEnd);
174 // Modifier - Support ${foo:modifier} syntax, where "modifier" is passed
175 // into printOperand.
176 std::string Modifier;
178 // In order to avoid starting the next string at the terminating curly
179 // brace, advance the end position past it if we found an opening curly
181 if (hasCurlyBraces) {
182 if (VarEnd >= AsmString.size())
183 throw "Reached end of string before terminating curly brace in '"
184 + CGI.TheDef->getName() + "'";
186 // Look for a modifier string.
187 if (AsmString[VarEnd] == ':') {
189 if (VarEnd >= AsmString.size())
190 throw "Reached end of string before terminating curly brace in '"
191 + CGI.TheDef->getName() + "'";
193 unsigned ModifierStart = VarEnd;
194 while (VarEnd < AsmString.size() && isIdentChar(AsmString[VarEnd]))
196 Modifier = std::string(AsmString.begin()+ModifierStart,
197 AsmString.begin()+VarEnd);
198 if (Modifier.empty())
199 throw "Bad operand modifier name in '"+ CGI.TheDef->getName() + "'";
202 if (AsmString[VarEnd] != '}')
203 throw "Variable name beginning with '{' did not end with '}' in '"
204 + CGI.TheDef->getName() + "'";
208 throw "Stray '$' in '" + CGI.TheDef->getName() +
209 "' asm string, maybe you want $$?";
211 unsigned OpNo = CGI.getOperandNamed(VarName);
212 CodeGenInstruction::OperandInfo OpInfo = CGI.OperandList[OpNo];
214 // If this is a two-address instruction and we are not accessing the
215 // 0th operand, remove an operand.
216 unsigned MIOp = OpInfo.MIOperandNo;
217 if (CGI.isTwoAddress && MIOp != 0) {
219 throw "Should refer to operand #0 instead of #1 for two-address"
220 " instruction '" + CGI.TheDef->getName() + "'!";
224 if (CurVariant == Variant || CurVariant == ~0U)
225 Operands.push_back(AsmWriterOperand(OpInfo.PrinterMethodName, MIOp,
227 LastEmitted = VarEnd;
231 AddLiteralString("\\n");
234 /// MatchesAllButOneOp - If this instruction is exactly identical to the
235 /// specified instruction except for one differing operand, return the differing
236 /// operand number. If more than one operand mismatches, return ~1, otherwise
237 /// if the instructions are identical return ~0.
238 unsigned AsmWriterInst::MatchesAllButOneOp(const AsmWriterInst &Other)const{
239 if (Operands.size() != Other.Operands.size()) return ~1;
241 unsigned MismatchOperand = ~0U;
242 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
243 if (Operands[i] != Other.Operands[i])
244 if (MismatchOperand != ~0U) // Already have one mismatch?
249 return MismatchOperand;
252 static void PrintCases(std::vector<std::pair<std::string,
253 AsmWriterOperand> > &OpsToPrint, std::ostream &O) {
254 O << " case " << OpsToPrint.back().first << ": ";
255 AsmWriterOperand TheOp = OpsToPrint.back().second;
256 OpsToPrint.pop_back();
258 // Check to see if any other operands are identical in this list, and if so,
259 // emit a case label for them.
260 for (unsigned i = OpsToPrint.size(); i != 0; --i)
261 if (OpsToPrint[i-1].second == TheOp) {
262 O << "\n case " << OpsToPrint[i-1].first << ": ";
263 OpsToPrint.erase(OpsToPrint.begin()+i-1);
266 // Finally, emit the code.
267 O << TheOp.getCode();
272 /// EmitInstructions - Emit the last instruction in the vector and any other
273 /// instructions that are suitably similar to it.
274 static void EmitInstructions(std::vector<AsmWriterInst> &Insts,
276 AsmWriterInst FirstInst = Insts.back();
279 std::vector<AsmWriterInst> SimilarInsts;
280 unsigned DifferingOperand = ~0;
281 for (unsigned i = Insts.size(); i != 0; --i) {
282 unsigned DiffOp = Insts[i-1].MatchesAllButOneOp(FirstInst);
284 if (DifferingOperand == ~0U) // First match!
285 DifferingOperand = DiffOp;
287 // If this differs in the same operand as the rest of the instructions in
288 // this class, move it to the SimilarInsts list.
289 if (DifferingOperand == DiffOp || DiffOp == ~0U) {
290 SimilarInsts.push_back(Insts[i-1]);
291 Insts.erase(Insts.begin()+i-1);
296 O << " case " << FirstInst.CGI->Namespace << "::"
297 << FirstInst.CGI->TheDef->getName() << ":\n";
298 for (unsigned i = 0, e = SimilarInsts.size(); i != e; ++i)
299 O << " case " << SimilarInsts[i].CGI->Namespace << "::"
300 << SimilarInsts[i].CGI->TheDef->getName() << ":\n";
301 for (unsigned i = 0, e = FirstInst.Operands.size(); i != e; ++i) {
302 if (i != DifferingOperand) {
303 // If the operand is the same for all instructions, just print it.
304 O << " " << FirstInst.Operands[i].getCode();
306 // If this is the operand that varies between all of the instructions,
307 // emit a switch for just this operand now.
308 O << " switch (MI->getOpcode()) {\n";
309 std::vector<std::pair<std::string, AsmWriterOperand> > OpsToPrint;
310 OpsToPrint.push_back(std::make_pair(FirstInst.CGI->Namespace + "::" +
311 FirstInst.CGI->TheDef->getName(),
312 FirstInst.Operands[i]));
314 for (unsigned si = 0, e = SimilarInsts.size(); si != e; ++si) {
315 AsmWriterInst &AWI = SimilarInsts[si];
316 OpsToPrint.push_back(std::make_pair(AWI.CGI->Namespace+"::"+
317 AWI.CGI->TheDef->getName(),
320 std::reverse(OpsToPrint.begin(), OpsToPrint.end());
321 while (!OpsToPrint.empty())
322 PrintCases(OpsToPrint, O);
331 void AsmWriterEmitter::
332 FindUniqueOperandCommands(std::vector<std::string> &UniqueOperandCommands,
333 std::vector<unsigned> &InstIdxs, unsigned Op) const {
335 InstIdxs.resize(NumberedInstructions.size());
337 // This vector parallels UniqueOperandCommands, keeping track of which
338 // instructions each case are used for. It is a comma separated string of
340 std::vector<std::string> InstrsForCase;
341 InstrsForCase.resize(UniqueOperandCommands.size());
343 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
344 const AsmWriterInst *Inst = getAsmWriterInstByID(i);
345 if (Inst == 0) continue; // PHI, INLINEASM, etc.
348 if (Op >= Inst->Operands.size())
349 continue; // Instruction already done.
351 Command = " " + Inst->Operands[Op].getCode() + "\n";
353 // If this is the last operand, emit a return.
354 if (Op == Inst->Operands.size()-1)
355 Command += " return true;\n";
357 // Check to see if we already have 'Command' in UniqueOperandCommands.
359 bool FoundIt = false;
360 for (unsigned idx = 0, e = UniqueOperandCommands.size(); idx != e; ++idx)
361 if (UniqueOperandCommands[idx] == Command) {
363 InstrsForCase[idx] += ", ";
364 InstrsForCase[idx] += Inst->CGI->TheDef->getName();
369 InstIdxs[i] = UniqueOperandCommands.size();
370 UniqueOperandCommands.push_back(Command);
371 InstrsForCase.push_back(Inst->CGI->TheDef->getName());
375 // Prepend some of the instructions each case is used for onto the case val.
376 for (unsigned i = 0, e = InstrsForCase.size(); i != e; ++i) {
377 std::string Instrs = InstrsForCase[i];
378 if (Instrs.size() > 70) {
379 Instrs.erase(Instrs.begin()+70, Instrs.end());
384 UniqueOperandCommands[i] = " // " + Instrs + "\n" +
385 UniqueOperandCommands[i];
391 void AsmWriterEmitter::run(std::ostream &O) {
392 EmitSourceFileHeader("Assembly Writer Source Fragment", O);
394 CodeGenTarget Target;
395 Record *AsmWriter = Target.getAsmWriter();
396 std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName");
397 unsigned Variant = AsmWriter->getValueAsInt("Variant");
400 "/// printInstruction - This method is automatically generated by tablegen\n"
401 "/// from the instruction set description. This method returns true if the\n"
402 "/// machine instruction was sufficiently described to print it, otherwise\n"
403 "/// it returns false.\n"
404 "bool " << Target.getName() << ClassName
405 << "::printInstruction(const MachineInstr *MI) {\n";
407 std::vector<AsmWriterInst> Instructions;
409 for (CodeGenTarget::inst_iterator I = Target.inst_begin(),
410 E = Target.inst_end(); I != E; ++I)
411 if (!I->second.AsmString.empty())
412 Instructions.push_back(AsmWriterInst(I->second, Variant));
414 // Get the instruction numbering.
415 Target.getInstructionsByEnumValue(NumberedInstructions);
417 // Compute the CodeGenInstruction -> AsmWriterInst mapping. Note that not
418 // all machine instructions are necessarily being printed, so there may be
419 // target instructions not in this map.
420 for (unsigned i = 0, e = Instructions.size(); i != e; ++i)
421 CGIAWIMap.insert(std::make_pair(Instructions[i].CGI, &Instructions[i]));
423 // Build an aggregate string, and build a table of offsets into it.
424 std::map<std::string, unsigned> StringOffset;
425 std::string AggregateString;
426 AggregateString += '\0';
428 /// OpcodeInfo - Theis encodes the index of the string to use for the first
429 /// chunk of the output as well as indices used for operand printing.
430 std::vector<unsigned> OpcodeInfo;
432 unsigned MaxStringIdx = 0;
433 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
434 AsmWriterInst *AWI = CGIAWIMap[NumberedInstructions[i]];
436 if (AWI == 0 || AWI->Operands[0].Str.empty()) {
437 // Something not handled by the asmwriter printer.
440 unsigned &Entry = StringOffset[AWI->Operands[0].Str];
442 // Add the string to the aggregate if this is the first time found.
443 MaxStringIdx = Entry = AggregateString.size();
444 std::string Str = AWI->Operands[0].Str;
446 AggregateString += Str;
447 AggregateString += '\0';
451 // Nuke the string from the operand list. It is now handled!
452 AWI->Operands.erase(AWI->Operands.begin());
454 OpcodeInfo.push_back(Idx);
457 // Figure out how many bits we used for the string index.
458 unsigned AsmStrBits = Log2_32_Ceil(MaxStringIdx);
460 // To reduce code size, we compactify common instructions into a few bits
461 // in the opcode-indexed table.
462 unsigned BitsLeft = 32-AsmStrBits;
464 std::vector<std::vector<std::string> > TableDrivenOperandPrinters;
466 for (unsigned i = 0; ; ++i) {
467 std::vector<std::string> UniqueOperandCommands;
469 // For the first operand check, add a default value that unhandled
470 // instructions will use.
472 UniqueOperandCommands.push_back(" return false;\n");
474 std::vector<unsigned> InstIdxs;
475 FindUniqueOperandCommands(UniqueOperandCommands, InstIdxs, i);
477 // If we ran out of operands to print, we're done.
478 if (UniqueOperandCommands.empty()) break;
480 // FIXME: GROW THEM MAXIMALLY.
482 // Compute the number of bits we need to represent these cases, this is
483 // ceil(log2(numentries)).
484 unsigned NumBits = Log2_32_Ceil(UniqueOperandCommands.size());
486 // If we don't have enough bits for this operand, don't include it.
487 if (NumBits > BitsLeft) {
488 DEBUG(std::cerr << "Not enough bits to densely encode " << NumBits
493 // Otherwise, we can include this in the initial lookup table. Add it in.
495 for (unsigned i = 0, e = InstIdxs.size(); i != e; ++i)
496 OpcodeInfo[i] |= InstIdxs[i] << (BitsLeft+AsmStrBits);
498 TableDrivenOperandPrinters.push_back(UniqueOperandCommands);
503 O<<" static const unsigned OpInfo[] = {\n";
504 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
505 O << " " << OpcodeInfo[i] << "U,\t// "
506 << NumberedInstructions[i]->TheDef->getName() << "\n";
508 // Add a dummy entry so the array init doesn't end with a comma.
512 // Emit the string itself.
513 O << " const char *AsmStrs = \n \"";
514 unsigned CharsPrinted = 0;
515 EscapeString(AggregateString);
516 for (unsigned i = 0, e = AggregateString.size(); i != e; ++i) {
517 if (CharsPrinted > 70) {
521 O << AggregateString[i];
524 // Print escape sequences all together.
525 if (AggregateString[i] == '\\') {
526 assert(i+1 < AggregateString.size() && "Incomplete escape sequence!");
527 if (isdigit(AggregateString[i+1])) {
528 assert(isdigit(AggregateString[i+2]) && isdigit(AggregateString[i+3]) &&
529 "Expected 3 digit octal escape!");
530 O << AggregateString[++i];
531 O << AggregateString[++i];
532 O << AggregateString[++i];
535 O << AggregateString[++i];
542 O << " if (MI->getOpcode() == TargetInstrInfo::INLINEASM) {\n"
543 << " printInlineAsm(MI);\n"
547 O << " // Emit the opcode for the instruction.\n"
548 << " unsigned Bits = OpInfo[MI->getOpcode()];\n"
549 << " O << AsmStrs+(Bits & " << (1 << AsmStrBits)-1 << ");\n\n";
551 // Output the table driven operand information.
552 BitsLeft = 32-AsmStrBits;
553 for (unsigned i = 0, e = TableDrivenOperandPrinters.size(); i != e; ++i) {
554 std::vector<std::string> &Commands = TableDrivenOperandPrinters[i];
556 // Compute the number of bits we need to represent these cases, this is
557 // ceil(log2(numentries)).
558 unsigned NumBits = Log2_32_Ceil(Commands.size());
559 assert(NumBits <= BitsLeft && "consistency error");
561 // Emit code to extract this field from Bits.
564 O << "\n // Fragment " << i << " encoded into " << NumBits
565 << " bits for " << Commands.size() << " unique commands.\n";
567 if (Commands.size() == 1) {
568 // Only one possibility, just emit it.
570 } else if (Commands.size() == 2) {
571 // Emit two possibilitys with if/else.
572 O << " if ((Bits >> " << (BitsLeft+AsmStrBits) << ") & "
573 << ((1 << NumBits)-1) << ") {\n"
579 O << " switch ((Bits >> " << (BitsLeft+AsmStrBits) << ") & "
580 << ((1 << NumBits)-1) << ") {\n"
581 << " default: // unreachable.\n";
583 // Print out all the cases.
584 for (unsigned i = 0, e = Commands.size(); i != e; ++i) {
585 O << " case " << i << ":\n";
593 // Okay, go through and strip out the operand information that we just
595 unsigned NumOpsToRemove = TableDrivenOperandPrinters.size();
596 for (unsigned i = 0, e = Instructions.size(); i != e; ++i) {
597 // Entire instruction has been emitted?
598 AsmWriterInst &Inst = Instructions[i];
599 if (Inst.Operands.size() <= NumOpsToRemove) {
600 Instructions.erase(Instructions.begin()+i);
603 Inst.Operands.erase(Inst.Operands.begin(),
604 Inst.Operands.begin()+NumOpsToRemove);
609 // Because this is a vector, we want to emit from the end. Reverse all of the
610 // elements in the vector.
611 std::reverse(Instructions.begin(), Instructions.end());
613 if (!Instructions.empty()) {
614 // Find the opcode # of inline asm.
615 O << " switch (MI->getOpcode()) {\n";
616 while (!Instructions.empty())
617 EmitInstructions(Instructions, O);
622 O << " return true;\n"