1 //===- AsmWriterEmitter.cpp - Generate an assembly writer -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend is emits an assembly printer for the current target.
11 // Note that this is currently fairly skeletal, but will grow over time.
13 //===----------------------------------------------------------------------===//
15 #include "AsmWriterEmitter.h"
16 #include "CodeGenTarget.h"
18 #include "llvm/ADT/StringExtras.h"
19 #include "llvm/ADT/StringMap.h"
20 #include "llvm/Support/Debug.h"
21 #include "llvm/Support/MathExtras.h"
25 /// StringToOffsetTable - This class uniques a bunch of nul-terminated strings
26 /// and keeps track of their offset in a massive contiguous string allocation.
27 /// It can then output this string blob and use indexes into the string to
28 /// reference each piece.
29 class StringToOffsetTable {
30 StringMap<unsigned> StringOffset;
31 std::string AggregateString;
34 unsigned GetOrAddStringOffset(StringRef Str) {
35 unsigned &Entry = StringOffset[Str];
37 // Add the string to the aggregate if this is the first time found.
38 Entry = AggregateString.size();
39 AggregateString.append(Str.begin(), Str.end());
40 AggregateString += '\0';
46 void EmitString(raw_ostream &O) {
48 unsigned CharsPrinted = 0;
49 EscapeString(AggregateString);
50 for (unsigned i = 0, e = AggregateString.size(); i != e; ++i) {
51 if (CharsPrinted > 70) {
55 O << AggregateString[i];
58 // Print escape sequences all together.
59 if (AggregateString[i] != '\\')
62 assert(i+1 < AggregateString.size() && "Incomplete escape sequence!");
63 if (isdigit(AggregateString[i+1])) {
64 assert(isdigit(AggregateString[i+2]) &&
65 isdigit(AggregateString[i+3]) &&
66 "Expected 3 digit octal escape!");
67 O << AggregateString[++i];
68 O << AggregateString[++i];
69 O << AggregateString[++i];
72 O << AggregateString[++i];
81 static bool isIdentChar(char C) {
82 return (C >= 'a' && C <= 'z') ||
83 (C >= 'A' && C <= 'Z') ||
84 (C >= '0' && C <= '9') ||
88 // This should be an anon namespace, this works around a GCC warning.
90 struct AsmWriterOperand {
92 // Output this text surrounded by quotes to the asm.
94 // This is the name of a routine to call to print the operand.
95 isMachineInstrOperand,
96 // Output this text verbatim to the asm writer. It is code that
97 // will output some text to the asm.
98 isLiteralStatementOperand
101 /// Str - For isLiteralTextOperand, this IS the literal text. For
102 /// isMachineInstrOperand, this is the PrinterMethodName for the operand..
103 /// For isLiteralStatementOperand, this is the code to insert verbatim
104 /// into the asm writer.
107 /// MiOpNo - For isMachineInstrOperand, this is the operand number of the
108 /// machine instruction.
111 /// MiModifier - For isMachineInstrOperand, this is the modifier string for
112 /// an operand, specified with syntax like ${opname:modifier}.
113 std::string MiModifier;
115 // To make VS STL happy
116 AsmWriterOperand(OpType op = isLiteralTextOperand):OperandType(op) {}
118 AsmWriterOperand(const std::string &LitStr,
119 OpType op = isLiteralTextOperand)
120 : OperandType(op), Str(LitStr) {}
122 AsmWriterOperand(const std::string &Printer, unsigned OpNo,
123 const std::string &Modifier,
124 OpType op = isMachineInstrOperand)
125 : OperandType(op), Str(Printer), MIOpNo(OpNo),
126 MiModifier(Modifier) {}
128 bool operator!=(const AsmWriterOperand &Other) const {
129 if (OperandType != Other.OperandType || Str != Other.Str) return true;
130 if (OperandType == isMachineInstrOperand)
131 return MIOpNo != Other.MIOpNo || MiModifier != Other.MiModifier;
134 bool operator==(const AsmWriterOperand &Other) const {
135 return !operator!=(Other);
138 /// getCode - Return the code that prints this operand.
139 std::string getCode() const;
144 class AsmWriterInst {
146 std::vector<AsmWriterOperand> Operands;
147 const CodeGenInstruction *CGI;
149 AsmWriterInst(const CodeGenInstruction &CGI, Record *AsmWriter);
151 /// MatchesAllButOneOp - If this instruction is exactly identical to the
152 /// specified instruction except for one differing operand, return the
153 /// differing operand number. Otherwise return ~0.
154 unsigned MatchesAllButOneOp(const AsmWriterInst &Other) const;
157 void AddLiteralString(const std::string &Str) {
158 // If the last operand was already a literal text string, append this to
159 // it, otherwise add a new operand.
160 if (!Operands.empty() &&
161 Operands.back().OperandType == AsmWriterOperand::isLiteralTextOperand)
162 Operands.back().Str.append(Str);
164 Operands.push_back(AsmWriterOperand(Str));
170 std::string AsmWriterOperand::getCode() const {
171 if (OperandType == isLiteralTextOperand) {
173 return "O << '" + Str + "'; ";
174 return "O << \"" + Str + "\"; ";
177 if (OperandType == isLiteralStatementOperand)
180 std::string Result = Str + "(MI";
182 Result += ", " + utostr(MIOpNo);
183 if (!MiModifier.empty())
184 Result += ", \"" + MiModifier + '"';
185 return Result + "); ";
189 /// ParseAsmString - Parse the specified Instruction's AsmString into this
192 AsmWriterInst::AsmWriterInst(const CodeGenInstruction &CGI, Record *AsmWriter) {
195 unsigned Variant = AsmWriter->getValueAsInt("Variant");
196 int FirstOperandColumn = AsmWriter->getValueAsInt("FirstOperandColumn");
197 int OperandSpacing = AsmWriter->getValueAsInt("OperandSpacing");
199 unsigned CurVariant = ~0U; // ~0 if we are outside a {.|.|.} region, other #.
201 // This is the number of tabs we've seen if we're doing columnar layout.
202 unsigned CurColumn = 0;
205 // NOTE: Any extensions to this code need to be mirrored in the
206 // AsmPrinter::printInlineAsm code that executes as compile time (assuming
207 // that inline asm strings should also get the new feature)!
208 const std::string &AsmString = CGI.AsmString;
209 std::string::size_type LastEmitted = 0;
210 while (LastEmitted != AsmString.size()) {
211 std::string::size_type DollarPos =
212 AsmString.find_first_of("${|}\\", LastEmitted);
213 if (DollarPos == std::string::npos) DollarPos = AsmString.size();
215 // Emit a constant string fragment.
217 if (DollarPos != LastEmitted) {
218 if (CurVariant == Variant || CurVariant == ~0U) {
219 for (; LastEmitted != DollarPos; ++LastEmitted)
220 switch (AsmString[LastEmitted]) {
222 AddLiteralString("\\n");
225 // If the asm writer is not using a columnar layout, \t is not
227 if (FirstOperandColumn == -1 || OperandSpacing == -1) {
228 AddLiteralString("\\t");
230 // We recognize a tab as an operand delimeter.
231 unsigned DestColumn = FirstOperandColumn +
232 CurColumn++ * OperandSpacing;
234 AsmWriterOperand("O.PadToColumn(" +
235 utostr(DestColumn) + ");\n",
236 AsmWriterOperand::isLiteralStatementOperand));
240 AddLiteralString("\\\"");
243 AddLiteralString("\\\\");
246 AddLiteralString(std::string(1, AsmString[LastEmitted]));
250 LastEmitted = DollarPos;
252 } else if (AsmString[DollarPos] == '\\') {
253 if (DollarPos+1 != AsmString.size() &&
254 (CurVariant == Variant || CurVariant == ~0U)) {
255 if (AsmString[DollarPos+1] == 'n') {
256 AddLiteralString("\\n");
257 } else if (AsmString[DollarPos+1] == 't') {
258 // If the asm writer is not using a columnar layout, \t is not
260 if (FirstOperandColumn == -1 || OperandSpacing == -1) {
261 AddLiteralString("\\t");
265 // We recognize a tab as an operand delimeter.
266 unsigned DestColumn = FirstOperandColumn +
267 CurColumn++ * OperandSpacing;
269 AsmWriterOperand("O.PadToColumn(" + utostr(DestColumn) + ");\n",
270 AsmWriterOperand::isLiteralStatementOperand));
272 } else if (std::string("${|}\\").find(AsmString[DollarPos+1])
273 != std::string::npos) {
274 AddLiteralString(std::string(1, AsmString[DollarPos+1]));
276 throw "Non-supported escaped character found in instruction '" +
277 CGI.TheDef->getName() + "'!";
279 LastEmitted = DollarPos+2;
282 } else if (AsmString[DollarPos] == '{') {
283 if (CurVariant != ~0U)
284 throw "Nested variants found for instruction '" +
285 CGI.TheDef->getName() + "'!";
286 LastEmitted = DollarPos+1;
287 CurVariant = 0; // We are now inside of the variant!
288 } else if (AsmString[DollarPos] == '|') {
289 if (CurVariant == ~0U)
290 throw "'|' character found outside of a variant in instruction '"
291 + CGI.TheDef->getName() + "'!";
294 } else if (AsmString[DollarPos] == '}') {
295 if (CurVariant == ~0U)
296 throw "'}' character found outside of a variant in instruction '"
297 + CGI.TheDef->getName() + "'!";
300 } else if (DollarPos+1 != AsmString.size() &&
301 AsmString[DollarPos+1] == '$') {
302 if (CurVariant == Variant || CurVariant == ~0U) {
303 AddLiteralString("$"); // "$$" -> $
305 LastEmitted = DollarPos+2;
307 // Get the name of the variable.
308 std::string::size_type VarEnd = DollarPos+1;
310 // handle ${foo}bar as $foo by detecting whether the character following
311 // the dollar sign is a curly brace. If so, advance VarEnd and DollarPos
312 // so the variable name does not contain the leading curly brace.
313 bool hasCurlyBraces = false;
314 if (VarEnd < AsmString.size() && '{' == AsmString[VarEnd]) {
315 hasCurlyBraces = true;
320 while (VarEnd < AsmString.size() && isIdentChar(AsmString[VarEnd]))
322 std::string VarName(AsmString.begin()+DollarPos+1,
323 AsmString.begin()+VarEnd);
325 // Modifier - Support ${foo:modifier} syntax, where "modifier" is passed
326 // into printOperand. Also support ${:feature}, which is passed into
328 std::string Modifier;
330 // In order to avoid starting the next string at the terminating curly
331 // brace, advance the end position past it if we found an opening curly
333 if (hasCurlyBraces) {
334 if (VarEnd >= AsmString.size())
335 throw "Reached end of string before terminating curly brace in '"
336 + CGI.TheDef->getName() + "'";
338 // Look for a modifier string.
339 if (AsmString[VarEnd] == ':') {
341 if (VarEnd >= AsmString.size())
342 throw "Reached end of string before terminating curly brace in '"
343 + CGI.TheDef->getName() + "'";
345 unsigned ModifierStart = VarEnd;
346 while (VarEnd < AsmString.size() && isIdentChar(AsmString[VarEnd]))
348 Modifier = std::string(AsmString.begin()+ModifierStart,
349 AsmString.begin()+VarEnd);
350 if (Modifier.empty())
351 throw "Bad operand modifier name in '"+ CGI.TheDef->getName() + "'";
354 if (AsmString[VarEnd] != '}')
355 throw "Variable name beginning with '{' did not end with '}' in '"
356 + CGI.TheDef->getName() + "'";
359 if (VarName.empty() && Modifier.empty())
360 throw "Stray '$' in '" + CGI.TheDef->getName() +
361 "' asm string, maybe you want $$?";
363 if (VarName.empty()) {
364 // Just a modifier, pass this into PrintSpecial.
365 Operands.push_back(AsmWriterOperand("PrintSpecial", ~0U, Modifier));
367 // Otherwise, normal operand.
368 unsigned OpNo = CGI.getOperandNamed(VarName);
369 CodeGenInstruction::OperandInfo OpInfo = CGI.OperandList[OpNo];
371 if (CurVariant == Variant || CurVariant == ~0U) {
372 unsigned MIOp = OpInfo.MIOperandNo;
373 Operands.push_back(AsmWriterOperand(OpInfo.PrinterMethodName, MIOp,
377 LastEmitted = VarEnd;
381 Operands.push_back(AsmWriterOperand("return;",
382 AsmWriterOperand::isLiteralStatementOperand));
385 /// MatchesAllButOneOp - If this instruction is exactly identical to the
386 /// specified instruction except for one differing operand, return the differing
387 /// operand number. If more than one operand mismatches, return ~1, otherwise
388 /// if the instructions are identical return ~0.
389 unsigned AsmWriterInst::MatchesAllButOneOp(const AsmWriterInst &Other)const{
390 if (Operands.size() != Other.Operands.size()) return ~1;
392 unsigned MismatchOperand = ~0U;
393 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
394 if (Operands[i] != Other.Operands[i]) {
395 if (MismatchOperand != ~0U) // Already have one mismatch?
401 return MismatchOperand;
404 static void PrintCases(std::vector<std::pair<std::string,
405 AsmWriterOperand> > &OpsToPrint, raw_ostream &O) {
406 O << " case " << OpsToPrint.back().first << ": ";
407 AsmWriterOperand TheOp = OpsToPrint.back().second;
408 OpsToPrint.pop_back();
410 // Check to see if any other operands are identical in this list, and if so,
411 // emit a case label for them.
412 for (unsigned i = OpsToPrint.size(); i != 0; --i)
413 if (OpsToPrint[i-1].second == TheOp) {
414 O << "\n case " << OpsToPrint[i-1].first << ": ";
415 OpsToPrint.erase(OpsToPrint.begin()+i-1);
418 // Finally, emit the code.
419 O << TheOp.getCode();
424 /// EmitInstructions - Emit the last instruction in the vector and any other
425 /// instructions that are suitably similar to it.
426 static void EmitInstructions(std::vector<AsmWriterInst> &Insts,
428 AsmWriterInst FirstInst = Insts.back();
431 std::vector<AsmWriterInst> SimilarInsts;
432 unsigned DifferingOperand = ~0;
433 for (unsigned i = Insts.size(); i != 0; --i) {
434 unsigned DiffOp = Insts[i-1].MatchesAllButOneOp(FirstInst);
436 if (DifferingOperand == ~0U) // First match!
437 DifferingOperand = DiffOp;
439 // If this differs in the same operand as the rest of the instructions in
440 // this class, move it to the SimilarInsts list.
441 if (DifferingOperand == DiffOp || DiffOp == ~0U) {
442 SimilarInsts.push_back(Insts[i-1]);
443 Insts.erase(Insts.begin()+i-1);
448 O << " case " << FirstInst.CGI->Namespace << "::"
449 << FirstInst.CGI->TheDef->getName() << ":\n";
450 for (unsigned i = 0, e = SimilarInsts.size(); i != e; ++i)
451 O << " case " << SimilarInsts[i].CGI->Namespace << "::"
452 << SimilarInsts[i].CGI->TheDef->getName() << ":\n";
453 for (unsigned i = 0, e = FirstInst.Operands.size(); i != e; ++i) {
454 if (i != DifferingOperand) {
455 // If the operand is the same for all instructions, just print it.
456 O << " " << FirstInst.Operands[i].getCode();
458 // If this is the operand that varies between all of the instructions,
459 // emit a switch for just this operand now.
460 O << " switch (MI->getOpcode()) {\n";
461 std::vector<std::pair<std::string, AsmWriterOperand> > OpsToPrint;
462 OpsToPrint.push_back(std::make_pair(FirstInst.CGI->Namespace + "::" +
463 FirstInst.CGI->TheDef->getName(),
464 FirstInst.Operands[i]));
466 for (unsigned si = 0, e = SimilarInsts.size(); si != e; ++si) {
467 AsmWriterInst &AWI = SimilarInsts[si];
468 OpsToPrint.push_back(std::make_pair(AWI.CGI->Namespace+"::"+
469 AWI.CGI->TheDef->getName(),
472 std::reverse(OpsToPrint.begin(), OpsToPrint.end());
473 while (!OpsToPrint.empty())
474 PrintCases(OpsToPrint, O);
482 void AsmWriterEmitter::
483 FindUniqueOperandCommands(std::vector<std::string> &UniqueOperandCommands,
484 std::vector<unsigned> &InstIdxs,
485 std::vector<unsigned> &InstOpsUsed) const {
486 InstIdxs.assign(NumberedInstructions.size(), ~0U);
488 // This vector parallels UniqueOperandCommands, keeping track of which
489 // instructions each case are used for. It is a comma separated string of
491 std::vector<std::string> InstrsForCase;
492 InstrsForCase.resize(UniqueOperandCommands.size());
493 InstOpsUsed.assign(UniqueOperandCommands.size(), 0);
495 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
496 const AsmWriterInst *Inst = getAsmWriterInstByID(i);
497 if (Inst == 0) continue; // PHI, INLINEASM, DBG_LABEL, etc.
500 if (Inst->Operands.empty())
501 continue; // Instruction already done.
503 Command = " " + Inst->Operands[0].getCode() + "\n";
505 // Check to see if we already have 'Command' in UniqueOperandCommands.
507 bool FoundIt = false;
508 for (unsigned idx = 0, e = UniqueOperandCommands.size(); idx != e; ++idx)
509 if (UniqueOperandCommands[idx] == Command) {
511 InstrsForCase[idx] += ", ";
512 InstrsForCase[idx] += Inst->CGI->TheDef->getName();
517 InstIdxs[i] = UniqueOperandCommands.size();
518 UniqueOperandCommands.push_back(Command);
519 InstrsForCase.push_back(Inst->CGI->TheDef->getName());
521 // This command matches one operand so far.
522 InstOpsUsed.push_back(1);
526 // For each entry of UniqueOperandCommands, there is a set of instructions
527 // that uses it. If the next command of all instructions in the set are
528 // identical, fold it into the command.
529 for (unsigned CommandIdx = 0, e = UniqueOperandCommands.size();
530 CommandIdx != e; ++CommandIdx) {
532 for (unsigned Op = 1; ; ++Op) {
533 // Scan for the first instruction in the set.
534 std::vector<unsigned>::iterator NIT =
535 std::find(InstIdxs.begin(), InstIdxs.end(), CommandIdx);
536 if (NIT == InstIdxs.end()) break; // No commonality.
538 // If this instruction has no more operands, we isn't anything to merge
539 // into this command.
540 const AsmWriterInst *FirstInst =
541 getAsmWriterInstByID(NIT-InstIdxs.begin());
542 if (!FirstInst || FirstInst->Operands.size() == Op)
545 // Otherwise, scan to see if all of the other instructions in this command
546 // set share the operand.
548 // Keep track of the maximum, number of operands or any
549 // instruction we see in the group.
550 size_t MaxSize = FirstInst->Operands.size();
552 for (NIT = std::find(NIT+1, InstIdxs.end(), CommandIdx);
553 NIT != InstIdxs.end();
554 NIT = std::find(NIT+1, InstIdxs.end(), CommandIdx)) {
555 // Okay, found another instruction in this command set. If the operand
556 // matches, we're ok, otherwise bail out.
557 const AsmWriterInst *OtherInst =
558 getAsmWriterInstByID(NIT-InstIdxs.begin());
561 OtherInst->Operands.size() > FirstInst->Operands.size())
562 MaxSize = std::max(MaxSize, OtherInst->Operands.size());
564 if (!OtherInst || OtherInst->Operands.size() == Op ||
565 OtherInst->Operands[Op] != FirstInst->Operands[Op]) {
572 // Okay, everything in this command set has the same next operand. Add it
573 // to UniqueOperandCommands and remember that it was consumed.
574 std::string Command = " " + FirstInst->Operands[Op].getCode() + "\n";
576 UniqueOperandCommands[CommandIdx] += Command;
577 InstOpsUsed[CommandIdx]++;
581 // Prepend some of the instructions each case is used for onto the case val.
582 for (unsigned i = 0, e = InstrsForCase.size(); i != e; ++i) {
583 std::string Instrs = InstrsForCase[i];
584 if (Instrs.size() > 70) {
585 Instrs.erase(Instrs.begin()+70, Instrs.end());
590 UniqueOperandCommands[i] = " // " + Instrs + "\n" +
591 UniqueOperandCommands[i];
596 /// EmitPrintInstruction - Generate the code for the "printInstruction" method
598 void AsmWriterEmitter::EmitPrintInstruction(raw_ostream &O) {
599 CodeGenTarget Target;
600 Record *AsmWriter = Target.getAsmWriter();
601 std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName");
604 "/// printInstruction - This method is automatically generated by tablegen\n"
605 "/// from the instruction set description.\n"
606 "void " << Target.getName() << ClassName
607 << "::printInstruction(const MachineInstr *MI) {\n";
609 std::vector<AsmWriterInst> Instructions;
611 for (CodeGenTarget::inst_iterator I = Target.inst_begin(),
612 E = Target.inst_end(); I != E; ++I)
613 if (!I->second.AsmString.empty() &&
614 I->second.TheDef->getName() != "PHI")
615 Instructions.push_back(AsmWriterInst(I->second, AsmWriter));
617 // Get the instruction numbering.
618 Target.getInstructionsByEnumValue(NumberedInstructions);
620 // Compute the CodeGenInstruction -> AsmWriterInst mapping. Note that not
621 // all machine instructions are necessarily being printed, so there may be
622 // target instructions not in this map.
623 for (unsigned i = 0, e = Instructions.size(); i != e; ++i)
624 CGIAWIMap.insert(std::make_pair(Instructions[i].CGI, &Instructions[i]));
626 // Build an aggregate string, and build a table of offsets into it.
627 StringToOffsetTable StringTable;
629 /// OpcodeInfo - This encodes the index of the string to use for the first
630 /// chunk of the output as well as indices used for operand printing.
631 std::vector<unsigned> OpcodeInfo;
633 unsigned MaxStringIdx = 0;
634 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
635 AsmWriterInst *AWI = CGIAWIMap[NumberedInstructions[i]];
638 // Something not handled by the asmwriter printer.
640 } else if (AWI->Operands[0].OperandType !=
641 AsmWriterOperand::isLiteralTextOperand ||
642 AWI->Operands[0].Str.empty()) {
643 // Something handled by the asmwriter printer, but with no leading string.
644 Idx = StringTable.GetOrAddStringOffset("");
646 std::string Str = AWI->Operands[0].Str;
648 Idx = StringTable.GetOrAddStringOffset(Str);
649 MaxStringIdx = std::max(MaxStringIdx, Idx);
651 // Nuke the string from the operand list. It is now handled!
652 AWI->Operands.erase(AWI->Operands.begin());
655 // Bias offset by one since we want 0 as a sentinel.
656 OpcodeInfo.push_back(Idx+1);
659 // Figure out how many bits we used for the string index.
660 unsigned AsmStrBits = Log2_32_Ceil(MaxStringIdx+2);
662 // To reduce code size, we compactify common instructions into a few bits
663 // in the opcode-indexed table.
664 unsigned BitsLeft = 32-AsmStrBits;
666 std::vector<std::vector<std::string> > TableDrivenOperandPrinters;
669 std::vector<std::string> UniqueOperandCommands;
670 std::vector<unsigned> InstIdxs;
671 std::vector<unsigned> NumInstOpsHandled;
672 FindUniqueOperandCommands(UniqueOperandCommands, InstIdxs,
675 // If we ran out of operands to print, we're done.
676 if (UniqueOperandCommands.empty()) break;
678 // Compute the number of bits we need to represent these cases, this is
679 // ceil(log2(numentries)).
680 unsigned NumBits = Log2_32_Ceil(UniqueOperandCommands.size());
682 // If we don't have enough bits for this operand, don't include it.
683 if (NumBits > BitsLeft) {
684 DEBUG(errs() << "Not enough bits to densely encode " << NumBits
689 // Otherwise, we can include this in the initial lookup table. Add it in.
691 for (unsigned i = 0, e = InstIdxs.size(); i != e; ++i)
692 if (InstIdxs[i] != ~0U)
693 OpcodeInfo[i] |= InstIdxs[i] << (BitsLeft+AsmStrBits);
695 // Remove the info about this operand.
696 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
697 if (AsmWriterInst *Inst = getAsmWriterInstByID(i))
698 if (!Inst->Operands.empty()) {
699 unsigned NumOps = NumInstOpsHandled[InstIdxs[i]];
700 assert(NumOps <= Inst->Operands.size() &&
701 "Can't remove this many ops!");
702 Inst->Operands.erase(Inst->Operands.begin(),
703 Inst->Operands.begin()+NumOps);
707 // Remember the handlers for this set of operands.
708 TableDrivenOperandPrinters.push_back(UniqueOperandCommands);
713 O<<" static const unsigned OpInfo[] = {\n";
714 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
715 O << " " << OpcodeInfo[i] << "U,\t// "
716 << NumberedInstructions[i]->TheDef->getName() << "\n";
718 // Add a dummy entry so the array init doesn't end with a comma.
722 // Emit the string itself.
723 O << " const char *AsmStrs = \n";
724 StringTable.EmitString(O);
727 O << "\n#ifndef NO_ASM_WRITER_BOILERPLATE\n";
729 O << " if (MI->getOpcode() == TargetInstrInfo::INLINEASM) {\n"
730 << " O << \"\\t\";\n"
731 << " printInlineAsm(MI);\n"
733 << " } else if (MI->isLabel()) {\n"
734 << " printLabel(MI);\n"
736 << " } else if (MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF) {\n"
737 << " printImplicitDef(MI);\n"
743 O << " O << \"\\t\";\n\n";
745 O << " // Emit the opcode for the instruction.\n"
746 << " unsigned Bits = OpInfo[MI->getOpcode()];\n"
747 << " assert(Bits != 0 && \"Cannot print this instruction.\");\n"
748 << " O << AsmStrs+(Bits & " << (1 << AsmStrBits)-1 << ")-1;\n\n";
750 // Output the table driven operand information.
751 BitsLeft = 32-AsmStrBits;
752 for (unsigned i = 0, e = TableDrivenOperandPrinters.size(); i != e; ++i) {
753 std::vector<std::string> &Commands = TableDrivenOperandPrinters[i];
755 // Compute the number of bits we need to represent these cases, this is
756 // ceil(log2(numentries)).
757 unsigned NumBits = Log2_32_Ceil(Commands.size());
758 assert(NumBits <= BitsLeft && "consistency error");
760 // Emit code to extract this field from Bits.
763 O << "\n // Fragment " << i << " encoded into " << NumBits
764 << " bits for " << Commands.size() << " unique commands.\n";
766 if (Commands.size() == 2) {
767 // Emit two possibilitys with if/else.
768 O << " if ((Bits >> " << (BitsLeft+AsmStrBits) << ") & "
769 << ((1 << NumBits)-1) << ") {\n"
775 O << " switch ((Bits >> " << (BitsLeft+AsmStrBits) << ") & "
776 << ((1 << NumBits)-1) << ") {\n"
777 << " default: // unreachable.\n";
779 // Print out all the cases.
780 for (unsigned i = 0, e = Commands.size(); i != e; ++i) {
781 O << " case " << i << ":\n";
789 // Okay, delete instructions with no operand info left.
790 for (unsigned i = 0, e = Instructions.size(); i != e; ++i) {
791 // Entire instruction has been emitted?
792 AsmWriterInst &Inst = Instructions[i];
793 if (Inst.Operands.empty()) {
794 Instructions.erase(Instructions.begin()+i);
800 // Because this is a vector, we want to emit from the end. Reverse all of the
801 // elements in the vector.
802 std::reverse(Instructions.begin(), Instructions.end());
804 if (!Instructions.empty()) {
805 // Find the opcode # of inline asm.
806 O << " switch (MI->getOpcode()) {\n";
807 while (!Instructions.empty())
808 EmitInstructions(Instructions, O);
819 void AsmWriterEmitter::EmitGetRegisterName(raw_ostream &O) {
820 CodeGenTarget Target;
821 Record *AsmWriter = Target.getAsmWriter();
822 std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName");
823 const std::vector<CodeGenRegister> &Registers = Target.getRegisters();
826 "\n\n/// getRegisterName - This method is automatically generated by tblgen\n"
827 "/// from the register set description. This returns the assembler name\n"
828 "/// for the specified register.\n"
829 "const char *" << Target.getName() << ClassName
830 << "::getRegisterName(unsigned RegNo) {\n"
831 << " assert(RegNo && RegNo < " << (Registers.size()+1)
832 << " && \"Invalid register number!\");\n"
834 << " static const char *const RegAsmNames[] = {\n";
835 for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
836 const CodeGenRegister &Reg = Registers[i];
838 std::string AsmName = Reg.TheDef->getValueAsString("AsmName");
840 AsmName = Reg.getName();
841 O << " \"" << AsmName << "\",\n";
846 << " return RegAsmNames[RegNo-1];\n"
851 void AsmWriterEmitter::run(raw_ostream &O) {
852 EmitSourceFileHeader("Assembly Writer Source Fragment", O);
854 EmitPrintInstruction(O);
855 EmitGetRegisterName(O);