1 //===- AsmMatcherEmitter.cpp - Generate an assembly matcher ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend emits a target specifier matcher for converting parsed
11 // assembly operands in the MCInst structures. It also emits a matcher for
12 // custom operand parsing.
14 // Converting assembly operands into MCInst structures
15 // ---------------------------------------------------
17 // The input to the target specific matcher is a list of literal tokens and
18 // operands. The target specific parser should generally eliminate any syntax
19 // which is not relevant for matching; for example, comma tokens should have
20 // already been consumed and eliminated by the parser. Most instructions will
21 // end up with a single literal token (the instruction name) and some number of
24 // Some example inputs, for X86:
25 // 'addl' (immediate ...) (register ...)
26 // 'add' (immediate ...) (memory ...)
29 // The assembly matcher is responsible for converting this input into a precise
30 // machine instruction (i.e., an instruction with a well defined encoding). This
31 // mapping has several properties which complicate matching:
33 // - It may be ambiguous; many architectures can legally encode particular
34 // variants of an instruction in different ways (for example, using a smaller
35 // encoding for small immediates). Such ambiguities should never be
36 // arbitrarily resolved by the assembler, the assembler is always responsible
37 // for choosing the "best" available instruction.
39 // - It may depend on the subtarget or the assembler context. Instructions
40 // which are invalid for the current mode, but otherwise unambiguous (e.g.,
41 // an SSE instruction in a file being assembled for i486) should be accepted
42 // and rejected by the assembler front end. However, if the proper encoding
43 // for an instruction is dependent on the assembler context then the matcher
44 // is responsible for selecting the correct machine instruction for the
47 // The core matching algorithm attempts to exploit the regularity in most
48 // instruction sets to quickly determine the set of possibly matching
49 // instructions, and the simplify the generated code. Additionally, this helps
50 // to ensure that the ambiguities are intentionally resolved by the user.
52 // The matching is divided into two distinct phases:
54 // 1. Classification: Each operand is mapped to the unique set which (a)
55 // contains it, and (b) is the largest such subset for which a single
56 // instruction could match all members.
58 // For register classes, we can generate these subgroups automatically. For
59 // arbitrary operands, we expect the user to define the classes and their
60 // relations to one another (for example, 8-bit signed immediates as a
61 // subset of 32-bit immediates).
63 // By partitioning the operands in this way, we guarantee that for any
64 // tuple of classes, any single instruction must match either all or none
65 // of the sets of operands which could classify to that tuple.
67 // In addition, the subset relation amongst classes induces a partial order
68 // on such tuples, which we use to resolve ambiguities.
70 // 2. The input can now be treated as a tuple of classes (static tokens are
71 // simple singleton sets). Each such tuple should generally map to a single
72 // instruction (we currently ignore cases where this isn't true, whee!!!),
73 // which we can emit a simple matcher for.
75 // Custom Operand Parsing
76 // ----------------------
78 // Some targets need a custom way to parse operands, some specific instructions
79 // can contain arguments that can represent processor flags and other kinds of
80 // identifiers that need to be mapped to specific values in the final encoded
81 // instructions. The target specific custom operand parsing works in the
84 // 1. A operand match table is built, each entry contains a mnemonic, an
85 // operand class, a mask for all operand positions for that same
86 // class/mnemonic and target features to be checked while trying to match.
88 // 2. The operand matcher will try every possible entry with the same
89 // mnemonic and will check if the target feature for this mnemonic also
90 // matches. After that, if the operand to be matched has its index
91 // present in the mask, a successful match occurs. Otherwise, fallback
92 // to the regular operand parsing.
94 // 3. For a match success, each operand class that has a 'ParserMethod'
95 // becomes part of a switch from where the custom method is called.
97 //===----------------------------------------------------------------------===//
99 #include "CodeGenTarget.h"
100 #include "llvm/ADT/PointerUnion.h"
101 #include "llvm/ADT/STLExtras.h"
102 #include "llvm/ADT/SmallPtrSet.h"
103 #include "llvm/ADT/SmallVector.h"
104 #include "llvm/ADT/StringExtras.h"
105 #include "llvm/Support/CommandLine.h"
106 #include "llvm/Support/Debug.h"
107 #include "llvm/Support/ErrorHandling.h"
108 #include "llvm/TableGen/Error.h"
109 #include "llvm/TableGen/Record.h"
110 #include "llvm/TableGen/StringMatcher.h"
111 #include "llvm/TableGen/StringToOffsetTable.h"
112 #include "llvm/TableGen/TableGenBackend.h"
118 using namespace llvm;
120 #define DEBUG_TYPE "asm-matcher-emitter"
122 static cl::opt<std::string>
123 MatchPrefix("match-prefix", cl::init(""),
124 cl::desc("Only match instructions with the given prefix"));
127 class AsmMatcherInfo;
128 struct SubtargetFeatureInfo;
130 // Register sets are used as keys in some second-order sets TableGen creates
131 // when generating its data structures. This means that the order of two
132 // RegisterSets can be seen in the outputted AsmMatcher tables occasionally, and
133 // can even affect compiler output (at least seen in diagnostics produced when
134 // all matches fail). So we use a type that sorts them consistently.
135 typedef std::set<Record*, LessRecordByID> RegisterSet;
137 class AsmMatcherEmitter {
138 RecordKeeper &Records;
140 AsmMatcherEmitter(RecordKeeper &R) : Records(R) {}
142 void run(raw_ostream &o);
145 /// ClassInfo - Helper class for storing the information about a particular
146 /// class of operands which can be matched.
149 /// Invalid kind, for use as a sentinel value.
152 /// The class for a particular token.
155 /// The (first) register class, subsequent register classes are
156 /// RegisterClass0+1, and so on.
159 /// The (first) user defined class, subsequent user defined classes are
160 /// UserClass0+1, and so on.
164 /// Kind - The class kind, which is either a predefined kind, or (UserClass0 +
165 /// N) for the Nth user defined class.
168 /// SuperClasses - The super classes of this class. Note that for simplicities
169 /// sake user operands only record their immediate super class, while register
170 /// operands include all superclasses.
171 std::vector<ClassInfo*> SuperClasses;
173 /// Name - The full class name, suitable for use in an enum.
176 /// ClassName - The unadorned generic name for this class (e.g., Token).
177 std::string ClassName;
179 /// ValueName - The name of the value this class represents; for a token this
180 /// is the literal token string, for an operand it is the TableGen class (or
181 /// empty if this is a derived class).
182 std::string ValueName;
184 /// PredicateMethod - The name of the operand method to test whether the
185 /// operand matches this class; this is not valid for Token or register kinds.
186 std::string PredicateMethod;
188 /// RenderMethod - The name of the operand method to add this operand to an
189 /// MCInst; this is not valid for Token or register kinds.
190 std::string RenderMethod;
192 /// ParserMethod - The name of the operand method to do a target specific
193 /// parsing on the operand.
194 std::string ParserMethod;
196 /// For register classes: the records for all the registers in this class.
197 RegisterSet Registers;
199 /// For custom match classes: the diagnostic kind for when the predicate fails.
200 std::string DiagnosticType;
202 /// isRegisterClass() - Check if this is a register class.
203 bool isRegisterClass() const {
204 return Kind >= RegisterClass0 && Kind < UserClass0;
207 /// isUserClass() - Check if this is a user defined class.
208 bool isUserClass() const {
209 return Kind >= UserClass0;
212 /// isRelatedTo - Check whether this class is "related" to \p RHS. Classes
213 /// are related if they are in the same class hierarchy.
214 bool isRelatedTo(const ClassInfo &RHS) const {
215 // Tokens are only related to tokens.
216 if (Kind == Token || RHS.Kind == Token)
217 return Kind == Token && RHS.Kind == Token;
219 // Registers classes are only related to registers classes, and only if
220 // their intersection is non-empty.
221 if (isRegisterClass() || RHS.isRegisterClass()) {
222 if (!isRegisterClass() || !RHS.isRegisterClass())
226 std::insert_iterator<RegisterSet> II(Tmp, Tmp.begin());
227 std::set_intersection(Registers.begin(), Registers.end(),
228 RHS.Registers.begin(), RHS.Registers.end(),
229 II, LessRecordByID());
234 // Otherwise we have two users operands; they are related if they are in the
235 // same class hierarchy.
237 // FIXME: This is an oversimplification, they should only be related if they
238 // intersect, however we don't have that information.
239 assert(isUserClass() && RHS.isUserClass() && "Unexpected class!");
240 const ClassInfo *Root = this;
241 while (!Root->SuperClasses.empty())
242 Root = Root->SuperClasses.front();
244 const ClassInfo *RHSRoot = &RHS;
245 while (!RHSRoot->SuperClasses.empty())
246 RHSRoot = RHSRoot->SuperClasses.front();
248 return Root == RHSRoot;
251 /// isSubsetOf - Test whether this class is a subset of \p RHS.
252 bool isSubsetOf(const ClassInfo &RHS) const {
253 // This is a subset of RHS if it is the same class...
257 // ... or if any of its super classes are a subset of RHS.
258 for (const ClassInfo *CI : SuperClasses)
259 if (CI->isSubsetOf(RHS))
265 /// operator< - Compare two classes.
266 bool operator<(const ClassInfo &RHS) const {
270 // Unrelated classes can be ordered by kind.
271 if (!isRelatedTo(RHS))
272 return Kind < RHS.Kind;
276 llvm_unreachable("Invalid kind!");
279 // This class precedes the RHS if it is a proper subset of the RHS.
282 if (RHS.isSubsetOf(*this))
285 // Otherwise, order by name to ensure we have a total ordering.
286 return ValueName < RHS.ValueName;
291 /// MatchableInfo - Helper class for storing the necessary information for an
292 /// instruction or alias which is capable of being matched.
293 struct MatchableInfo {
295 /// Token - This is the token that the operand came from.
298 /// The unique class instance this operand should match.
301 /// The operand name this is, if anything.
304 /// The suboperand index within SrcOpName, or -1 for the entire operand.
307 /// Register record if this token is singleton register.
308 Record *SingletonReg;
310 explicit AsmOperand(StringRef T) : Token(T), Class(nullptr), SubOpIdx(-1),
311 SingletonReg(nullptr) {}
314 /// ResOperand - This represents a single operand in the result instruction
315 /// generated by the match. In cases (like addressing modes) where a single
316 /// assembler operand expands to multiple MCOperands, this represents the
317 /// single assembler operand, not the MCOperand.
320 /// RenderAsmOperand - This represents an operand result that is
321 /// generated by calling the render method on the assembly operand. The
322 /// corresponding AsmOperand is specified by AsmOperandNum.
325 /// TiedOperand - This represents a result operand that is a duplicate of
326 /// a previous result operand.
329 /// ImmOperand - This represents an immediate value that is dumped into
333 /// RegOperand - This represents a fixed register that is dumped in.
338 /// This is the operand # in the AsmOperands list that this should be
340 unsigned AsmOperandNum;
342 /// TiedOperandNum - This is the (earlier) result operand that should be
344 unsigned TiedOperandNum;
346 /// ImmVal - This is the immediate value added to the instruction.
349 /// Register - This is the register record.
353 /// MINumOperands - The number of MCInst operands populated by this
355 unsigned MINumOperands;
357 static ResOperand getRenderedOp(unsigned AsmOpNum, unsigned NumOperands) {
359 X.Kind = RenderAsmOperand;
360 X.AsmOperandNum = AsmOpNum;
361 X.MINumOperands = NumOperands;
365 static ResOperand getTiedOp(unsigned TiedOperandNum) {
367 X.Kind = TiedOperand;
368 X.TiedOperandNum = TiedOperandNum;
373 static ResOperand getImmOp(int64_t Val) {
381 static ResOperand getRegOp(Record *Reg) {
390 /// AsmVariantID - Target's assembly syntax variant no.
393 /// TheDef - This is the definition of the instruction or InstAlias that this
394 /// matchable came from.
395 Record *const TheDef;
397 /// DefRec - This is the definition that it came from.
398 PointerUnion<const CodeGenInstruction*, const CodeGenInstAlias*> DefRec;
400 const CodeGenInstruction *getResultInst() const {
401 if (DefRec.is<const CodeGenInstruction*>())
402 return DefRec.get<const CodeGenInstruction*>();
403 return DefRec.get<const CodeGenInstAlias*>()->ResultInst;
406 /// ResOperands - This is the operand list that should be built for the result
408 SmallVector<ResOperand, 8> ResOperands;
410 /// AsmString - The assembly string for this instruction (with variants
411 /// removed), e.g. "movsx $src, $dst".
412 std::string AsmString;
414 /// Mnemonic - This is the first token of the matched instruction, its
418 /// AsmOperands - The textual operands that this instruction matches,
419 /// annotated with a class and where in the OperandList they were defined.
420 /// This directly corresponds to the tokenized AsmString after the mnemonic is
422 SmallVector<AsmOperand, 8> AsmOperands;
424 /// Predicates - The required subtarget features to match this instruction.
425 SmallVector<SubtargetFeatureInfo*, 4> RequiredFeatures;
427 /// ConversionFnKind - The enum value which is passed to the generated
428 /// convertToMCInst to convert parsed operands into an MCInst for this
430 std::string ConversionFnKind;
432 /// If this instruction is deprecated in some form.
435 MatchableInfo(const CodeGenInstruction &CGI)
436 : AsmVariantID(0), TheDef(CGI.TheDef), DefRec(&CGI),
437 AsmString(CGI.AsmString) {
440 MatchableInfo(const CodeGenInstAlias *Alias)
441 : AsmVariantID(0), TheDef(Alias->TheDef), DefRec(Alias),
442 AsmString(Alias->AsmString) {
445 // Two-operand aliases clone from the main matchable, but mark the second
446 // operand as a tied operand of the first for purposes of the assembler.
447 void formTwoOperandAlias(StringRef Constraint);
449 void initialize(const AsmMatcherInfo &Info,
450 SmallPtrSetImpl<Record*> &SingletonRegisters,
451 int AsmVariantNo, std::string &RegisterPrefix);
453 /// validate - Return true if this matchable is a valid thing to match against
454 /// and perform a bunch of validity checking.
455 bool validate(StringRef CommentDelimiter, bool Hack) const;
457 /// extractSingletonRegisterForAsmOperand - Extract singleton register,
458 /// if present, from specified token.
460 extractSingletonRegisterForAsmOperand(unsigned i, const AsmMatcherInfo &Info,
461 std::string &RegisterPrefix);
463 /// findAsmOperand - Find the AsmOperand with the specified name and
464 /// suboperand index.
465 int findAsmOperand(StringRef N, int SubOpIdx) const {
466 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i)
467 if (N == AsmOperands[i].SrcOpName &&
468 SubOpIdx == AsmOperands[i].SubOpIdx)
473 /// findAsmOperandNamed - Find the first AsmOperand with the specified name.
474 /// This does not check the suboperand index.
475 int findAsmOperandNamed(StringRef N) const {
476 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i)
477 if (N == AsmOperands[i].SrcOpName)
482 void buildInstructionResultOperands();
483 void buildAliasResultOperands();
485 /// operator< - Compare two matchables.
486 bool operator<(const MatchableInfo &RHS) const {
487 // The primary comparator is the instruction mnemonic.
488 if (Mnemonic != RHS.Mnemonic)
489 return Mnemonic < RHS.Mnemonic;
491 if (AsmOperands.size() != RHS.AsmOperands.size())
492 return AsmOperands.size() < RHS.AsmOperands.size();
494 // Compare lexicographically by operand. The matcher validates that other
495 // orderings wouldn't be ambiguous using \see couldMatchAmbiguouslyWith().
496 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
497 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class)
499 if (*RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
503 // Give matches that require more features higher precedence. This is useful
504 // because we cannot define AssemblerPredicates with the negation of
505 // processor features. For example, ARM v6 "nop" may be either a HINT or
506 // MOV. With v6, we want to match HINT. The assembler has no way to
507 // predicate MOV under "NoV6", but HINT will always match first because it
508 // requires V6 while MOV does not.
509 if (RequiredFeatures.size() != RHS.RequiredFeatures.size())
510 return RequiredFeatures.size() > RHS.RequiredFeatures.size();
515 /// couldMatchAmbiguouslyWith - Check whether this matchable could
516 /// ambiguously match the same set of operands as \p RHS (without being a
517 /// strictly superior match).
518 bool couldMatchAmbiguouslyWith(const MatchableInfo &RHS) const {
519 // The primary comparator is the instruction mnemonic.
520 if (Mnemonic != RHS.Mnemonic)
523 // The number of operands is unambiguous.
524 if (AsmOperands.size() != RHS.AsmOperands.size())
527 // Otherwise, make sure the ordering of the two instructions is unambiguous
528 // by checking that either (a) a token or operand kind discriminates them,
529 // or (b) the ordering among equivalent kinds is consistent.
531 // Tokens and operand kinds are unambiguous (assuming a correct target
533 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i)
534 if (AsmOperands[i].Class->Kind != RHS.AsmOperands[i].Class->Kind ||
535 AsmOperands[i].Class->Kind == ClassInfo::Token)
536 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class ||
537 *RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
540 // Otherwise, this operand could commute if all operands are equivalent, or
541 // there is a pair of operands that compare less than and a pair that
542 // compare greater than.
543 bool HasLT = false, HasGT = false;
544 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
545 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class)
547 if (*RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
551 return !(HasLT ^ HasGT);
557 void tokenizeAsmString(const AsmMatcherInfo &Info);
560 /// SubtargetFeatureInfo - Helper class for storing information on a subtarget
561 /// feature which participates in instruction matching.
562 struct SubtargetFeatureInfo {
563 /// \brief The predicate record for this feature.
566 /// \brief An unique index assigned to represent this feature.
569 SubtargetFeatureInfo(Record *D, uint64_t Idx) : TheDef(D), Index(Idx) {}
571 /// \brief The name of the enumerated constant identifying this feature.
572 std::string getEnumName() const {
573 return "Feature_" + TheDef->getName();
577 errs() << getEnumName() << " " << Index << "\n";
582 struct OperandMatchEntry {
583 unsigned OperandMask;
584 const MatchableInfo* MI;
587 static OperandMatchEntry create(const MatchableInfo *mi, ClassInfo *ci,
590 X.OperandMask = opMask;
598 class AsmMatcherInfo {
601 RecordKeeper &Records;
603 /// The tablegen AsmParser record.
606 /// Target - The target information.
607 CodeGenTarget &Target;
609 /// The classes which are needed for matching.
610 std::vector<ClassInfo*> Classes;
612 /// The information on the matchables to match.
613 std::vector<MatchableInfo*> Matchables;
615 /// Info for custom matching operands by user defined methods.
616 std::vector<OperandMatchEntry> OperandMatchInfo;
618 /// Map of Register records to their class information.
619 typedef std::map<Record*, ClassInfo*, LessRecordByID> RegisterClassesTy;
620 RegisterClassesTy RegisterClasses;
622 /// Map of Predicate records to their subtarget information.
623 std::map<Record*, SubtargetFeatureInfo*, LessRecordByID> SubtargetFeatures;
625 /// Map of AsmOperandClass records to their class information.
626 std::map<Record*, ClassInfo*> AsmOperandClasses;
629 /// Map of token to class information which has already been constructed.
630 std::map<std::string, ClassInfo*> TokenClasses;
632 /// Map of RegisterClass records to their class information.
633 std::map<Record*, ClassInfo*> RegisterClassClasses;
636 /// getTokenClass - Lookup or create the class for the given token.
637 ClassInfo *getTokenClass(StringRef Token);
639 /// getOperandClass - Lookup or create the class for the given operand.
640 ClassInfo *getOperandClass(const CGIOperandList::OperandInfo &OI,
642 ClassInfo *getOperandClass(Record *Rec, int SubOpIdx);
644 /// buildRegisterClasses - Build the ClassInfo* instances for register
646 void buildRegisterClasses(SmallPtrSetImpl<Record*> &SingletonRegisters);
648 /// buildOperandClasses - Build the ClassInfo* instances for user defined
650 void buildOperandClasses();
652 void buildInstructionOperandReference(MatchableInfo *II, StringRef OpName,
654 void buildAliasOperandReference(MatchableInfo *II, StringRef OpName,
655 MatchableInfo::AsmOperand &Op);
658 AsmMatcherInfo(Record *AsmParser,
659 CodeGenTarget &Target,
660 RecordKeeper &Records);
662 /// buildInfo - Construct the various tables used during matching.
665 /// buildOperandMatchInfo - Build the necessary information to handle user
666 /// defined operand parsing methods.
667 void buildOperandMatchInfo();
669 /// getSubtargetFeature - Lookup or create the subtarget feature info for the
671 SubtargetFeatureInfo *getSubtargetFeature(Record *Def) const {
672 assert(Def->isSubClassOf("Predicate") && "Invalid predicate type!");
673 const auto &I = SubtargetFeatures.find(Def);
674 return I == SubtargetFeatures.end() ? nullptr : I->second;
677 RecordKeeper &getRecords() const {
682 } // End anonymous namespace
684 void MatchableInfo::dump() const {
685 errs() << TheDef->getName() << " -- " << "flattened:\"" << AsmString <<"\"\n";
687 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
688 const AsmOperand &Op = AsmOperands[i];
689 errs() << " op[" << i << "] = " << Op.Class->ClassName << " - ";
690 errs() << '\"' << Op.Token << "\"\n";
694 static std::pair<StringRef, StringRef>
695 parseTwoOperandConstraint(StringRef S, ArrayRef<SMLoc> Loc) {
696 // Split via the '='.
697 std::pair<StringRef, StringRef> Ops = S.split('=');
698 if (Ops.second == "")
699 PrintFatalError(Loc, "missing '=' in two-operand alias constraint");
700 // Trim whitespace and the leading '$' on the operand names.
701 size_t start = Ops.first.find_first_of('$');
702 if (start == std::string::npos)
703 PrintFatalError(Loc, "expected '$' prefix on asm operand name");
704 Ops.first = Ops.first.slice(start + 1, std::string::npos);
705 size_t end = Ops.first.find_last_of(" \t");
706 Ops.first = Ops.first.slice(0, end);
707 // Now the second operand.
708 start = Ops.second.find_first_of('$');
709 if (start == std::string::npos)
710 PrintFatalError(Loc, "expected '$' prefix on asm operand name");
711 Ops.second = Ops.second.slice(start + 1, std::string::npos);
712 end = Ops.second.find_last_of(" \t");
713 Ops.first = Ops.first.slice(0, end);
717 void MatchableInfo::formTwoOperandAlias(StringRef Constraint) {
718 // Figure out which operands are aliased and mark them as tied.
719 std::pair<StringRef, StringRef> Ops =
720 parseTwoOperandConstraint(Constraint, TheDef->getLoc());
722 // Find the AsmOperands that refer to the operands we're aliasing.
723 int SrcAsmOperand = findAsmOperandNamed(Ops.first);
724 int DstAsmOperand = findAsmOperandNamed(Ops.second);
725 if (SrcAsmOperand == -1)
726 PrintFatalError(TheDef->getLoc(),
727 "unknown source two-operand alias operand '" + Ops.first +
729 if (DstAsmOperand == -1)
730 PrintFatalError(TheDef->getLoc(),
731 "unknown destination two-operand alias operand '" +
734 // Find the ResOperand that refers to the operand we're aliasing away
735 // and update it to refer to the combined operand instead.
736 for (unsigned i = 0, e = ResOperands.size(); i != e; ++i) {
737 ResOperand &Op = ResOperands[i];
738 if (Op.Kind == ResOperand::RenderAsmOperand &&
739 Op.AsmOperandNum == (unsigned)SrcAsmOperand) {
740 Op.AsmOperandNum = DstAsmOperand;
744 // Remove the AsmOperand for the alias operand.
745 AsmOperands.erase(AsmOperands.begin() + SrcAsmOperand);
746 // Adjust the ResOperand references to any AsmOperands that followed
747 // the one we just deleted.
748 for (unsigned i = 0, e = ResOperands.size(); i != e; ++i) {
749 ResOperand &Op = ResOperands[i];
752 // Nothing to do for operands that don't reference AsmOperands.
754 case ResOperand::RenderAsmOperand:
755 if (Op.AsmOperandNum > (unsigned)SrcAsmOperand)
758 case ResOperand::TiedOperand:
759 if (Op.TiedOperandNum > (unsigned)SrcAsmOperand)
766 void MatchableInfo::initialize(const AsmMatcherInfo &Info,
767 SmallPtrSetImpl<Record*> &SingletonRegisters,
768 int AsmVariantNo, std::string &RegisterPrefix) {
769 AsmVariantID = AsmVariantNo;
771 CodeGenInstruction::FlattenAsmStringVariants(AsmString, AsmVariantNo);
773 tokenizeAsmString(Info);
775 // Compute the require features.
776 std::vector<Record*> Predicates =TheDef->getValueAsListOfDefs("Predicates");
777 for (unsigned i = 0, e = Predicates.size(); i != e; ++i)
778 if (SubtargetFeatureInfo *Feature =
779 Info.getSubtargetFeature(Predicates[i]))
780 RequiredFeatures.push_back(Feature);
782 // Collect singleton registers, if used.
783 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
784 extractSingletonRegisterForAsmOperand(i, Info, RegisterPrefix);
785 if (Record *Reg = AsmOperands[i].SingletonReg)
786 SingletonRegisters.insert(Reg);
789 const RecordVal *DepMask = TheDef->getValue("DeprecatedFeatureMask");
791 DepMask = TheDef->getValue("ComplexDeprecationPredicate");
794 DepMask ? !DepMask->getValue()->getAsUnquotedString().empty() : false;
797 /// tokenizeAsmString - Tokenize a simplified assembly string.
798 void MatchableInfo::tokenizeAsmString(const AsmMatcherInfo &Info) {
799 StringRef String = AsmString;
802 for (unsigned i = 0, e = String.size(); i != e; ++i) {
812 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
815 if (!isspace(String[i]) && String[i] != ',')
816 AsmOperands.push_back(AsmOperand(String.substr(i, 1)));
822 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
826 assert(i != String.size() && "Invalid quoted character");
827 AsmOperands.push_back(AsmOperand(String.substr(i, 1)));
833 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
837 // If this isn't "${", treat like a normal token.
838 if (i + 1 == String.size() || String[i + 1] != '{') {
843 StringRef::iterator End = std::find(String.begin() + i, String.end(),'}');
844 assert(End != String.end() && "Missing brace in operand reference!");
845 size_t EndPos = End - String.begin();
846 AsmOperands.push_back(AsmOperand(String.slice(i, EndPos+1)));
853 if (!Info.AsmParser->getValueAsBit("MnemonicContainsDot")) {
855 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
865 if (InTok && Prev != String.size())
866 AsmOperands.push_back(AsmOperand(String.substr(Prev)));
868 // The first token of the instruction is the mnemonic, which must be a
869 // simple string, not a $foo variable or a singleton register.
870 if (AsmOperands.empty())
871 PrintFatalError(TheDef->getLoc(),
872 "Instruction '" + TheDef->getName() + "' has no tokens");
873 Mnemonic = AsmOperands[0].Token;
874 if (Mnemonic.empty())
875 PrintFatalError(TheDef->getLoc(),
876 "Missing instruction mnemonic");
877 // FIXME : Check and raise an error if it is a register.
878 if (Mnemonic[0] == '$')
879 PrintFatalError(TheDef->getLoc(),
880 "Invalid instruction mnemonic '" + Mnemonic + "'!");
882 // Remove the first operand, it is tracked in the mnemonic field.
883 AsmOperands.erase(AsmOperands.begin());
886 bool MatchableInfo::validate(StringRef CommentDelimiter, bool Hack) const {
887 // Reject matchables with no .s string.
888 if (AsmString.empty())
889 PrintFatalError(TheDef->getLoc(), "instruction with empty asm string");
891 // Reject any matchables with a newline in them, they should be marked
892 // isCodeGenOnly if they are pseudo instructions.
893 if (AsmString.find('\n') != std::string::npos)
894 PrintFatalError(TheDef->getLoc(),
895 "multiline instruction is not valid for the asmparser, "
896 "mark it isCodeGenOnly");
898 // Remove comments from the asm string. We know that the asmstring only
900 if (!CommentDelimiter.empty() &&
901 StringRef(AsmString).find(CommentDelimiter) != StringRef::npos)
902 PrintFatalError(TheDef->getLoc(),
903 "asmstring for instruction has comment character in it, "
904 "mark it isCodeGenOnly");
906 // Reject matchables with operand modifiers, these aren't something we can
907 // handle, the target should be refactored to use operands instead of
910 // Also, check for instructions which reference the operand multiple times;
911 // this implies a constraint we would not honor.
912 std::set<std::string> OperandNames;
913 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
914 StringRef Tok = AsmOperands[i].Token;
915 if (Tok[0] == '$' && Tok.find(':') != StringRef::npos)
916 PrintFatalError(TheDef->getLoc(),
917 "matchable with operand modifier '" + Tok +
918 "' not supported by asm matcher. Mark isCodeGenOnly!");
920 // Verify that any operand is only mentioned once.
921 // We reject aliases and ignore instructions for now.
922 if (Tok[0] == '$' && !OperandNames.insert(Tok).second) {
924 PrintFatalError(TheDef->getLoc(),
925 "ERROR: matchable with tied operand '" + Tok +
926 "' can never be matched!");
927 // FIXME: Should reject these. The ARM backend hits this with $lane in a
928 // bunch of instructions. It is unclear what the right answer is.
930 errs() << "warning: '" << TheDef->getName() << "': "
931 << "ignoring instruction with tied operand '"
941 /// extractSingletonRegisterForAsmOperand - Extract singleton register,
942 /// if present, from specified token.
944 extractSingletonRegisterForAsmOperand(unsigned OperandNo,
945 const AsmMatcherInfo &Info,
946 std::string &RegisterPrefix) {
947 StringRef Tok = AsmOperands[OperandNo].Token;
948 if (RegisterPrefix.empty()) {
949 std::string LoweredTok = Tok.lower();
950 if (const CodeGenRegister *Reg = Info.Target.getRegisterByName(LoweredTok))
951 AsmOperands[OperandNo].SingletonReg = Reg->TheDef;
955 if (!Tok.startswith(RegisterPrefix))
958 StringRef RegName = Tok.substr(RegisterPrefix.size());
959 if (const CodeGenRegister *Reg = Info.Target.getRegisterByName(RegName))
960 AsmOperands[OperandNo].SingletonReg = Reg->TheDef;
962 // If there is no register prefix (i.e. "%" in "%eax"), then this may
963 // be some random non-register token, just ignore it.
967 static std::string getEnumNameForToken(StringRef Str) {
970 for (StringRef::iterator it = Str.begin(), ie = Str.end(); it != ie; ++it) {
972 case '*': Res += "_STAR_"; break;
973 case '%': Res += "_PCT_"; break;
974 case ':': Res += "_COLON_"; break;
975 case '!': Res += "_EXCLAIM_"; break;
976 case '.': Res += "_DOT_"; break;
977 case '<': Res += "_LT_"; break;
978 case '>': Res += "_GT_"; break;
980 if ((*it >= 'A' && *it <= 'Z') ||
981 (*it >= 'a' && *it <= 'z') ||
982 (*it >= '0' && *it <= '9'))
985 Res += "_" + utostr((unsigned) *it) + "_";
992 ClassInfo *AsmMatcherInfo::getTokenClass(StringRef Token) {
993 ClassInfo *&Entry = TokenClasses[Token];
996 Entry = new ClassInfo();
997 Entry->Kind = ClassInfo::Token;
998 Entry->ClassName = "Token";
999 Entry->Name = "MCK_" + getEnumNameForToken(Token);
1000 Entry->ValueName = Token;
1001 Entry->PredicateMethod = "<invalid>";
1002 Entry->RenderMethod = "<invalid>";
1003 Entry->ParserMethod = "";
1004 Entry->DiagnosticType = "";
1005 Classes.push_back(Entry);
1012 AsmMatcherInfo::getOperandClass(const CGIOperandList::OperandInfo &OI,
1014 Record *Rec = OI.Rec;
1016 Rec = cast<DefInit>(OI.MIOperandInfo->getArg(SubOpIdx))->getDef();
1017 return getOperandClass(Rec, SubOpIdx);
1021 AsmMatcherInfo::getOperandClass(Record *Rec, int SubOpIdx) {
1022 if (Rec->isSubClassOf("RegisterOperand")) {
1023 // RegisterOperand may have an associated ParserMatchClass. If it does,
1024 // use it, else just fall back to the underlying register class.
1025 const RecordVal *R = Rec->getValue("ParserMatchClass");
1026 if (!R || !R->getValue())
1027 PrintFatalError("Record `" + Rec->getName() +
1028 "' does not have a ParserMatchClass!\n");
1030 if (DefInit *DI= dyn_cast<DefInit>(R->getValue())) {
1031 Record *MatchClass = DI->getDef();
1032 if (ClassInfo *CI = AsmOperandClasses[MatchClass])
1036 // No custom match class. Just use the register class.
1037 Record *ClassRec = Rec->getValueAsDef("RegClass");
1039 PrintFatalError(Rec->getLoc(), "RegisterOperand `" + Rec->getName() +
1040 "' has no associated register class!\n");
1041 if (ClassInfo *CI = RegisterClassClasses[ClassRec])
1043 PrintFatalError(Rec->getLoc(), "register class has no class info!");
1047 if (Rec->isSubClassOf("RegisterClass")) {
1048 if (ClassInfo *CI = RegisterClassClasses[Rec])
1050 PrintFatalError(Rec->getLoc(), "register class has no class info!");
1053 if (!Rec->isSubClassOf("Operand"))
1054 PrintFatalError(Rec->getLoc(), "Operand `" + Rec->getName() +
1055 "' does not derive from class Operand!\n");
1056 Record *MatchClass = Rec->getValueAsDef("ParserMatchClass");
1057 if (ClassInfo *CI = AsmOperandClasses[MatchClass])
1060 PrintFatalError(Rec->getLoc(), "operand has no match class!");
1063 struct LessRegisterSet {
1064 bool operator() (const RegisterSet &LHS, const RegisterSet & RHS) const {
1065 // std::set<T> defines its own compariso "operator<", but it
1066 // performs a lexicographical comparison by T's innate comparison
1067 // for some reason. We don't want non-deterministic pointer
1068 // comparisons so use this instead.
1069 return std::lexicographical_compare(LHS.begin(), LHS.end(),
1070 RHS.begin(), RHS.end(),
1075 void AsmMatcherInfo::
1076 buildRegisterClasses(SmallPtrSetImpl<Record*> &SingletonRegisters) {
1077 const std::vector<CodeGenRegister*> &Registers =
1078 Target.getRegBank().getRegisters();
1079 ArrayRef<CodeGenRegisterClass*> RegClassList =
1080 Target.getRegBank().getRegClasses();
1082 typedef std::set<RegisterSet, LessRegisterSet> RegisterSetSet;
1084 // The register sets used for matching.
1085 RegisterSetSet RegisterSets;
1087 // Gather the defined sets.
1088 for (const CodeGenRegisterClass *RC : RegClassList)
1089 RegisterSets.insert(RegisterSet(RC->getOrder().begin(),
1090 RC->getOrder().end()));
1092 // Add any required singleton sets.
1093 for (Record *Rec : SingletonRegisters) {
1094 RegisterSets.insert(RegisterSet(&Rec, &Rec + 1));
1097 // Introduce derived sets where necessary (when a register does not determine
1098 // a unique register set class), and build the mapping of registers to the set
1099 // they should classify to.
1100 std::map<Record*, RegisterSet> RegisterMap;
1101 for (const CodeGenRegister *CGR : Registers) {
1102 // Compute the intersection of all sets containing this register.
1103 RegisterSet ContainingSet;
1105 for (const RegisterSet &RS : RegisterSets) {
1106 if (!RS.count(CGR->TheDef))
1109 if (ContainingSet.empty()) {
1115 std::swap(Tmp, ContainingSet);
1116 std::insert_iterator<RegisterSet> II(ContainingSet,
1117 ContainingSet.begin());
1118 std::set_intersection(Tmp.begin(), Tmp.end(), RS.begin(), RS.end(), II,
1122 if (!ContainingSet.empty()) {
1123 RegisterSets.insert(ContainingSet);
1124 RegisterMap.insert(std::make_pair(CGR->TheDef, ContainingSet));
1128 // Construct the register classes.
1129 std::map<RegisterSet, ClassInfo*, LessRegisterSet> RegisterSetClasses;
1131 for (const RegisterSet &RS : RegisterSets) {
1132 ClassInfo *CI = new ClassInfo();
1133 CI->Kind = ClassInfo::RegisterClass0 + Index;
1134 CI->ClassName = "Reg" + utostr(Index);
1135 CI->Name = "MCK_Reg" + utostr(Index);
1137 CI->PredicateMethod = ""; // unused
1138 CI->RenderMethod = "addRegOperands";
1140 // FIXME: diagnostic type.
1141 CI->DiagnosticType = "";
1142 Classes.push_back(CI);
1143 RegisterSetClasses.insert(std::make_pair(RS, CI));
1147 // Find the superclasses; we could compute only the subgroup lattice edges,
1148 // but there isn't really a point.
1149 for (const RegisterSet &RS : RegisterSets) {
1150 ClassInfo *CI = RegisterSetClasses[RS];
1151 for (const RegisterSet &RS2 : RegisterSets)
1153 std::includes(RS2.begin(), RS2.end(), RS.begin(), RS.end(),
1155 CI->SuperClasses.push_back(RegisterSetClasses[RS2]);
1158 // Name the register classes which correspond to a user defined RegisterClass.
1159 for (const CodeGenRegisterClass *RC : RegClassList) {
1160 // Def will be NULL for non-user defined register classes.
1161 Record *Def = RC->getDef();
1164 ClassInfo *CI = RegisterSetClasses[RegisterSet(RC->getOrder().begin(),
1165 RC->getOrder().end())];
1166 if (CI->ValueName.empty()) {
1167 CI->ClassName = RC->getName();
1168 CI->Name = "MCK_" + RC->getName();
1169 CI->ValueName = RC->getName();
1171 CI->ValueName = CI->ValueName + "," + RC->getName();
1173 RegisterClassClasses.insert(std::make_pair(Def, CI));
1176 // Populate the map for individual registers.
1177 for (std::map<Record*, RegisterSet>::iterator it = RegisterMap.begin(),
1178 ie = RegisterMap.end(); it != ie; ++it)
1179 RegisterClasses[it->first] = RegisterSetClasses[it->second];
1181 // Name the register classes which correspond to singleton registers.
1182 for (Record *Rec : SingletonRegisters) {
1183 ClassInfo *CI = RegisterClasses[Rec];
1184 assert(CI && "Missing singleton register class info!");
1186 if (CI->ValueName.empty()) {
1187 CI->ClassName = Rec->getName();
1188 CI->Name = "MCK_" + Rec->getName();
1189 CI->ValueName = Rec->getName();
1191 CI->ValueName = CI->ValueName + "," + Rec->getName();
1195 void AsmMatcherInfo::buildOperandClasses() {
1196 std::vector<Record*> AsmOperands =
1197 Records.getAllDerivedDefinitions("AsmOperandClass");
1199 // Pre-populate AsmOperandClasses map.
1200 for (Record *Rec : AsmOperands)
1201 AsmOperandClasses[Rec] = new ClassInfo();
1204 for (Record *Rec : AsmOperands) {
1205 ClassInfo *CI = AsmOperandClasses[Rec];
1206 CI->Kind = ClassInfo::UserClass0 + Index;
1208 ListInit *Supers = Rec->getValueAsListInit("SuperClasses");
1209 for (unsigned i = 0, e = Supers->getSize(); i != e; ++i) {
1210 DefInit *DI = dyn_cast<DefInit>(Supers->getElement(i));
1212 PrintError(Rec->getLoc(), "Invalid super class reference!");
1216 ClassInfo *SC = AsmOperandClasses[DI->getDef()];
1218 PrintError(Rec->getLoc(), "Invalid super class reference!");
1220 CI->SuperClasses.push_back(SC);
1222 CI->ClassName = Rec->getValueAsString("Name");
1223 CI->Name = "MCK_" + CI->ClassName;
1224 CI->ValueName = Rec->getName();
1226 // Get or construct the predicate method name.
1227 Init *PMName = Rec->getValueInit("PredicateMethod");
1228 if (StringInit *SI = dyn_cast<StringInit>(PMName)) {
1229 CI->PredicateMethod = SI->getValue();
1231 assert(isa<UnsetInit>(PMName) && "Unexpected PredicateMethod field!");
1232 CI->PredicateMethod = "is" + CI->ClassName;
1235 // Get or construct the render method name.
1236 Init *RMName = Rec->getValueInit("RenderMethod");
1237 if (StringInit *SI = dyn_cast<StringInit>(RMName)) {
1238 CI->RenderMethod = SI->getValue();
1240 assert(isa<UnsetInit>(RMName) && "Unexpected RenderMethod field!");
1241 CI->RenderMethod = "add" + CI->ClassName + "Operands";
1244 // Get the parse method name or leave it as empty.
1245 Init *PRMName = Rec->getValueInit("ParserMethod");
1246 if (StringInit *SI = dyn_cast<StringInit>(PRMName))
1247 CI->ParserMethod = SI->getValue();
1249 // Get the diagnostic type or leave it as empty.
1250 // Get the parse method name or leave it as empty.
1251 Init *DiagnosticType = Rec->getValueInit("DiagnosticType");
1252 if (StringInit *SI = dyn_cast<StringInit>(DiagnosticType))
1253 CI->DiagnosticType = SI->getValue();
1255 AsmOperandClasses[Rec] = CI;
1256 Classes.push_back(CI);
1261 AsmMatcherInfo::AsmMatcherInfo(Record *asmParser,
1262 CodeGenTarget &target,
1263 RecordKeeper &records)
1264 : Records(records), AsmParser(asmParser), Target(target) {
1267 /// buildOperandMatchInfo - Build the necessary information to handle user
1268 /// defined operand parsing methods.
1269 void AsmMatcherInfo::buildOperandMatchInfo() {
1271 /// Map containing a mask with all operands indices that can be found for
1272 /// that class inside a instruction.
1273 typedef std::map<ClassInfo *, unsigned, less_ptr<ClassInfo>> OpClassMaskTy;
1274 OpClassMaskTy OpClassMask;
1276 for (const MatchableInfo *MI : Matchables) {
1277 OpClassMask.clear();
1279 // Keep track of all operands of this instructions which belong to the
1281 for (unsigned i = 0, e = MI->AsmOperands.size(); i != e; ++i) {
1282 const MatchableInfo::AsmOperand &Op = MI->AsmOperands[i];
1283 if (Op.Class->ParserMethod.empty())
1285 unsigned &OperandMask = OpClassMask[Op.Class];
1286 OperandMask |= (1 << i);
1289 // Generate operand match info for each mnemonic/operand class pair.
1290 for (const auto &OCM : OpClassMask) {
1291 unsigned OpMask = OCM.second;
1292 ClassInfo *CI = OCM.first;
1293 OperandMatchInfo.push_back(OperandMatchEntry::create(MI, CI, OpMask));
1298 void AsmMatcherInfo::buildInfo() {
1299 // Build information about all of the AssemblerPredicates.
1300 std::vector<Record*> AllPredicates =
1301 Records.getAllDerivedDefinitions("Predicate");
1302 for (unsigned i = 0, e = AllPredicates.size(); i != e; ++i) {
1303 Record *Pred = AllPredicates[i];
1304 // Ignore predicates that are not intended for the assembler.
1305 if (!Pred->getValueAsBit("AssemblerMatcherPredicate"))
1308 if (Pred->getName().empty())
1309 PrintFatalError(Pred->getLoc(), "Predicate has no name!");
1311 uint64_t FeatureNo = SubtargetFeatures.size();
1312 SubtargetFeatures[Pred] = new SubtargetFeatureInfo(Pred, FeatureNo);
1313 DEBUG(SubtargetFeatures[Pred]->dump());
1314 assert(FeatureNo < 64 && "Too many subtarget features!");
1317 // Parse the instructions; we need to do this first so that we can gather the
1318 // singleton register classes.
1319 SmallPtrSet<Record*, 16> SingletonRegisters;
1320 unsigned VariantCount = Target.getAsmParserVariantCount();
1321 for (unsigned VC = 0; VC != VariantCount; ++VC) {
1322 Record *AsmVariant = Target.getAsmParserVariant(VC);
1323 std::string CommentDelimiter =
1324 AsmVariant->getValueAsString("CommentDelimiter");
1325 std::string RegisterPrefix = AsmVariant->getValueAsString("RegisterPrefix");
1326 int AsmVariantNo = AsmVariant->getValueAsInt("Variant");
1328 for (const CodeGenInstruction *CGI : Target.instructions()) {
1330 // If the tblgen -match-prefix option is specified (for tblgen hackers),
1331 // filter the set of instructions we consider.
1332 if (!StringRef(CGI->TheDef->getName()).startswith(MatchPrefix))
1335 // Ignore "codegen only" instructions.
1336 if (CGI->TheDef->getValueAsBit("isCodeGenOnly"))
1339 std::unique_ptr<MatchableInfo> II(new MatchableInfo(*CGI));
1341 II->initialize(*this, SingletonRegisters, AsmVariantNo, RegisterPrefix);
1343 // Ignore instructions which shouldn't be matched and diagnose invalid
1344 // instruction definitions with an error.
1345 if (!II->validate(CommentDelimiter, true))
1348 Matchables.push_back(II.release());
1351 // Parse all of the InstAlias definitions and stick them in the list of
1353 std::vector<Record*> AllInstAliases =
1354 Records.getAllDerivedDefinitions("InstAlias");
1355 for (unsigned i = 0, e = AllInstAliases.size(); i != e; ++i) {
1356 CodeGenInstAlias *Alias =
1357 new CodeGenInstAlias(AllInstAliases[i], AsmVariantNo, Target);
1359 // If the tblgen -match-prefix option is specified (for tblgen hackers),
1360 // filter the set of instruction aliases we consider, based on the target
1362 if (!StringRef(Alias->ResultInst->TheDef->getName())
1363 .startswith( MatchPrefix))
1366 std::unique_ptr<MatchableInfo> II(new MatchableInfo(Alias));
1368 II->initialize(*this, SingletonRegisters, AsmVariantNo, RegisterPrefix);
1370 // Validate the alias definitions.
1371 II->validate(CommentDelimiter, false);
1373 Matchables.push_back(II.release());
1377 // Build info for the register classes.
1378 buildRegisterClasses(SingletonRegisters);
1380 // Build info for the user defined assembly operand classes.
1381 buildOperandClasses();
1383 // Build the information about matchables, now that we have fully formed
1385 std::vector<MatchableInfo*> NewMatchables;
1386 for (MatchableInfo *II : Matchables) {
1387 // Parse the tokens after the mnemonic.
1388 // Note: buildInstructionOperandReference may insert new AsmOperands, so
1389 // don't precompute the loop bound.
1390 for (unsigned i = 0; i != II->AsmOperands.size(); ++i) {
1391 MatchableInfo::AsmOperand &Op = II->AsmOperands[i];
1392 StringRef Token = Op.Token;
1394 // Check for singleton registers.
1395 if (Record *RegRecord = II->AsmOperands[i].SingletonReg) {
1396 Op.Class = RegisterClasses[RegRecord];
1397 assert(Op.Class && Op.Class->Registers.size() == 1 &&
1398 "Unexpected class for singleton register");
1402 // Check for simple tokens.
1403 if (Token[0] != '$') {
1404 Op.Class = getTokenClass(Token);
1408 if (Token.size() > 1 && isdigit(Token[1])) {
1409 Op.Class = getTokenClass(Token);
1413 // Otherwise this is an operand reference.
1414 StringRef OperandName;
1415 if (Token[1] == '{')
1416 OperandName = Token.substr(2, Token.size() - 3);
1418 OperandName = Token.substr(1);
1420 if (II->DefRec.is<const CodeGenInstruction*>())
1421 buildInstructionOperandReference(II, OperandName, i);
1423 buildAliasOperandReference(II, OperandName, Op);
1426 if (II->DefRec.is<const CodeGenInstruction*>()) {
1427 II->buildInstructionResultOperands();
1428 // If the instruction has a two-operand alias, build up the
1429 // matchable here. We'll add them in bulk at the end to avoid
1430 // confusing this loop.
1431 std::string Constraint =
1432 II->TheDef->getValueAsString("TwoOperandAliasConstraint");
1433 if (Constraint != "") {
1434 // Start by making a copy of the original matchable.
1435 std::unique_ptr<MatchableInfo> AliasII(new MatchableInfo(*II));
1437 // Adjust it to be a two-operand alias.
1438 AliasII->formTwoOperandAlias(Constraint);
1440 // Add the alias to the matchables list.
1441 NewMatchables.push_back(AliasII.release());
1444 II->buildAliasResultOperands();
1446 if (!NewMatchables.empty())
1447 Matchables.insert(Matchables.end(), NewMatchables.begin(),
1448 NewMatchables.end());
1450 // Process token alias definitions and set up the associated superclass
1452 std::vector<Record*> AllTokenAliases =
1453 Records.getAllDerivedDefinitions("TokenAlias");
1454 for (unsigned i = 0, e = AllTokenAliases.size(); i != e; ++i) {
1455 Record *Rec = AllTokenAliases[i];
1456 ClassInfo *FromClass = getTokenClass(Rec->getValueAsString("FromToken"));
1457 ClassInfo *ToClass = getTokenClass(Rec->getValueAsString("ToToken"));
1458 if (FromClass == ToClass)
1459 PrintFatalError(Rec->getLoc(),
1460 "error: Destination value identical to source value.");
1461 FromClass->SuperClasses.push_back(ToClass);
1464 // Reorder classes so that classes precede super classes.
1465 std::sort(Classes.begin(), Classes.end(), less_ptr<ClassInfo>());
1468 /// buildInstructionOperandReference - The specified operand is a reference to a
1469 /// named operand such as $src. Resolve the Class and OperandInfo pointers.
1470 void AsmMatcherInfo::
1471 buildInstructionOperandReference(MatchableInfo *II,
1472 StringRef OperandName,
1473 unsigned AsmOpIdx) {
1474 const CodeGenInstruction &CGI = *II->DefRec.get<const CodeGenInstruction*>();
1475 const CGIOperandList &Operands = CGI.Operands;
1476 MatchableInfo::AsmOperand *Op = &II->AsmOperands[AsmOpIdx];
1478 // Map this token to an operand.
1480 if (!Operands.hasOperandNamed(OperandName, Idx))
1481 PrintFatalError(II->TheDef->getLoc(),
1482 "error: unable to find operand: '" + OperandName + "'");
1484 // If the instruction operand has multiple suboperands, but the parser
1485 // match class for the asm operand is still the default "ImmAsmOperand",
1486 // then handle each suboperand separately.
1487 if (Op->SubOpIdx == -1 && Operands[Idx].MINumOperands > 1) {
1488 Record *Rec = Operands[Idx].Rec;
1489 assert(Rec->isSubClassOf("Operand") && "Unexpected operand!");
1490 Record *MatchClass = Rec->getValueAsDef("ParserMatchClass");
1491 if (MatchClass && MatchClass->getValueAsString("Name") == "Imm") {
1492 // Insert remaining suboperands after AsmOpIdx in II->AsmOperands.
1493 StringRef Token = Op->Token; // save this in case Op gets moved
1494 for (unsigned SI = 1, SE = Operands[Idx].MINumOperands; SI != SE; ++SI) {
1495 MatchableInfo::AsmOperand NewAsmOp(Token);
1496 NewAsmOp.SubOpIdx = SI;
1497 II->AsmOperands.insert(II->AsmOperands.begin()+AsmOpIdx+SI, NewAsmOp);
1499 // Replace Op with first suboperand.
1500 Op = &II->AsmOperands[AsmOpIdx]; // update the pointer in case it moved
1505 // Set up the operand class.
1506 Op->Class = getOperandClass(Operands[Idx], Op->SubOpIdx);
1508 // If the named operand is tied, canonicalize it to the untied operand.
1509 // For example, something like:
1510 // (outs GPR:$dst), (ins GPR:$src)
1511 // with an asmstring of
1513 // we want to canonicalize to:
1515 // so that we know how to provide the $dst operand when filling in the result.
1517 if (Operands[Idx].MINumOperands == 1)
1518 OITied = Operands[Idx].getTiedRegister();
1520 // The tied operand index is an MIOperand index, find the operand that
1522 std::pair<unsigned, unsigned> Idx = Operands.getSubOperandNumber(OITied);
1523 OperandName = Operands[Idx.first].Name;
1524 Op->SubOpIdx = Idx.second;
1527 Op->SrcOpName = OperandName;
1530 /// buildAliasOperandReference - When parsing an operand reference out of the
1531 /// matching string (e.g. "movsx $src, $dst"), determine what the class of the
1532 /// operand reference is by looking it up in the result pattern definition.
1533 void AsmMatcherInfo::buildAliasOperandReference(MatchableInfo *II,
1534 StringRef OperandName,
1535 MatchableInfo::AsmOperand &Op) {
1536 const CodeGenInstAlias &CGA = *II->DefRec.get<const CodeGenInstAlias*>();
1538 // Set up the operand class.
1539 for (unsigned i = 0, e = CGA.ResultOperands.size(); i != e; ++i)
1540 if (CGA.ResultOperands[i].isRecord() &&
1541 CGA.ResultOperands[i].getName() == OperandName) {
1542 // It's safe to go with the first one we find, because CodeGenInstAlias
1543 // validates that all operands with the same name have the same record.
1544 Op.SubOpIdx = CGA.ResultInstOperandIndex[i].second;
1545 // Use the match class from the Alias definition, not the
1546 // destination instruction, as we may have an immediate that's
1547 // being munged by the match class.
1548 Op.Class = getOperandClass(CGA.ResultOperands[i].getRecord(),
1550 Op.SrcOpName = OperandName;
1554 PrintFatalError(II->TheDef->getLoc(),
1555 "error: unable to find operand: '" + OperandName + "'");
1558 void MatchableInfo::buildInstructionResultOperands() {
1559 const CodeGenInstruction *ResultInst = getResultInst();
1561 // Loop over all operands of the result instruction, determining how to
1563 for (unsigned i = 0, e = ResultInst->Operands.size(); i != e; ++i) {
1564 const CGIOperandList::OperandInfo &OpInfo = ResultInst->Operands[i];
1566 // If this is a tied operand, just copy from the previously handled operand.
1568 if (OpInfo.MINumOperands == 1)
1569 TiedOp = OpInfo.getTiedRegister();
1571 ResOperands.push_back(ResOperand::getTiedOp(TiedOp));
1575 // Find out what operand from the asmparser this MCInst operand comes from.
1576 int SrcOperand = findAsmOperandNamed(OpInfo.Name);
1577 if (OpInfo.Name.empty() || SrcOperand == -1) {
1578 // This may happen for operands that are tied to a suboperand of a
1579 // complex operand. Simply use a dummy value here; nobody should
1580 // use this operand slot.
1581 // FIXME: The long term goal is for the MCOperand list to not contain
1582 // tied operands at all.
1583 ResOperands.push_back(ResOperand::getImmOp(0));
1587 // Check if the one AsmOperand populates the entire operand.
1588 unsigned NumOperands = OpInfo.MINumOperands;
1589 if (AsmOperands[SrcOperand].SubOpIdx == -1) {
1590 ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand, NumOperands));
1594 // Add a separate ResOperand for each suboperand.
1595 for (unsigned AI = 0; AI < NumOperands; ++AI) {
1596 assert(AsmOperands[SrcOperand+AI].SubOpIdx == (int)AI &&
1597 AsmOperands[SrcOperand+AI].SrcOpName == OpInfo.Name &&
1598 "unexpected AsmOperands for suboperands");
1599 ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand + AI, 1));
1604 void MatchableInfo::buildAliasResultOperands() {
1605 const CodeGenInstAlias &CGA = *DefRec.get<const CodeGenInstAlias*>();
1606 const CodeGenInstruction *ResultInst = getResultInst();
1608 // Loop over all operands of the result instruction, determining how to
1610 unsigned AliasOpNo = 0;
1611 unsigned LastOpNo = CGA.ResultInstOperandIndex.size();
1612 for (unsigned i = 0, e = ResultInst->Operands.size(); i != e; ++i) {
1613 const CGIOperandList::OperandInfo *OpInfo = &ResultInst->Operands[i];
1615 // If this is a tied operand, just copy from the previously handled operand.
1617 if (OpInfo->MINumOperands == 1)
1618 TiedOp = OpInfo->getTiedRegister();
1620 ResOperands.push_back(ResOperand::getTiedOp(TiedOp));
1624 // Handle all the suboperands for this operand.
1625 const std::string &OpName = OpInfo->Name;
1626 for ( ; AliasOpNo < LastOpNo &&
1627 CGA.ResultInstOperandIndex[AliasOpNo].first == i; ++AliasOpNo) {
1628 int SubIdx = CGA.ResultInstOperandIndex[AliasOpNo].second;
1630 // Find out what operand from the asmparser that this MCInst operand
1632 switch (CGA.ResultOperands[AliasOpNo].Kind) {
1633 case CodeGenInstAlias::ResultOperand::K_Record: {
1634 StringRef Name = CGA.ResultOperands[AliasOpNo].getName();
1635 int SrcOperand = findAsmOperand(Name, SubIdx);
1636 if (SrcOperand == -1)
1637 PrintFatalError(TheDef->getLoc(), "Instruction '" +
1638 TheDef->getName() + "' has operand '" + OpName +
1639 "' that doesn't appear in asm string!");
1640 unsigned NumOperands = (SubIdx == -1 ? OpInfo->MINumOperands : 1);
1641 ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand,
1645 case CodeGenInstAlias::ResultOperand::K_Imm: {
1646 int64_t ImmVal = CGA.ResultOperands[AliasOpNo].getImm();
1647 ResOperands.push_back(ResOperand::getImmOp(ImmVal));
1650 case CodeGenInstAlias::ResultOperand::K_Reg: {
1651 Record *Reg = CGA.ResultOperands[AliasOpNo].getRegister();
1652 ResOperands.push_back(ResOperand::getRegOp(Reg));
1660 static unsigned getConverterOperandID(const std::string &Name,
1661 SetVector<std::string> &Table,
1663 IsNew = Table.insert(Name);
1665 unsigned ID = IsNew ? Table.size() - 1 :
1666 std::find(Table.begin(), Table.end(), Name) - Table.begin();
1668 assert(ID < Table.size());
1674 static void emitConvertFuncs(CodeGenTarget &Target, StringRef ClassName,
1675 std::vector<MatchableInfo*> &Infos,
1677 SetVector<std::string> OperandConversionKinds;
1678 SetVector<std::string> InstructionConversionKinds;
1679 std::vector<std::vector<uint8_t> > ConversionTable;
1680 size_t MaxRowLength = 2; // minimum is custom converter plus terminator.
1682 // TargetOperandClass - This is the target's operand class, like X86Operand.
1683 std::string TargetOperandClass = Target.getName() + "Operand";
1685 // Write the convert function to a separate stream, so we can drop it after
1686 // the enum. We'll build up the conversion handlers for the individual
1687 // operand types opportunistically as we encounter them.
1688 std::string ConvertFnBody;
1689 raw_string_ostream CvtOS(ConvertFnBody);
1690 // Start the unified conversion function.
1691 CvtOS << "void " << Target.getName() << ClassName << "::\n"
1692 << "convertToMCInst(unsigned Kind, MCInst &Inst, "
1693 << "unsigned Opcode,\n"
1694 << " const OperandVector"
1695 << " &Operands) {\n"
1696 << " assert(Kind < CVT_NUM_SIGNATURES && \"Invalid signature!\");\n"
1697 << " const uint8_t *Converter = ConversionTable[Kind];\n"
1698 << " Inst.setOpcode(Opcode);\n"
1699 << " for (const uint8_t *p = Converter; *p; p+= 2) {\n"
1700 << " switch (*p) {\n"
1701 << " default: llvm_unreachable(\"invalid conversion entry!\");\n"
1702 << " case CVT_Reg:\n"
1703 << " static_cast<" << TargetOperandClass
1704 << "&>(*Operands[*(p + 1)]).addRegOperands(Inst, 1);\n"
1706 << " case CVT_Tied:\n"
1707 << " Inst.addOperand(Inst.getOperand(*(p + 1)));\n"
1710 std::string OperandFnBody;
1711 raw_string_ostream OpOS(OperandFnBody);
1712 // Start the operand number lookup function.
1713 OpOS << "void " << Target.getName() << ClassName << "::\n"
1714 << "convertToMapAndConstraints(unsigned Kind,\n";
1716 OpOS << "const OperandVector &Operands) {\n"
1717 << " assert(Kind < CVT_NUM_SIGNATURES && \"Invalid signature!\");\n"
1718 << " unsigned NumMCOperands = 0;\n"
1719 << " const uint8_t *Converter = ConversionTable[Kind];\n"
1720 << " for (const uint8_t *p = Converter; *p; p+= 2) {\n"
1721 << " switch (*p) {\n"
1722 << " default: llvm_unreachable(\"invalid conversion entry!\");\n"
1723 << " case CVT_Reg:\n"
1724 << " Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n"
1725 << " Operands[*(p + 1)]->setConstraint(\"r\");\n"
1726 << " ++NumMCOperands;\n"
1728 << " case CVT_Tied:\n"
1729 << " ++NumMCOperands;\n"
1732 // Pre-populate the operand conversion kinds with the standard always
1733 // available entries.
1734 OperandConversionKinds.insert("CVT_Done");
1735 OperandConversionKinds.insert("CVT_Reg");
1736 OperandConversionKinds.insert("CVT_Tied");
1737 enum { CVT_Done, CVT_Reg, CVT_Tied };
1739 for (MatchableInfo *II : Infos) {
1740 // Check if we have a custom match function.
1741 std::string AsmMatchConverter =
1742 II->getResultInst()->TheDef->getValueAsString("AsmMatchConverter");
1743 if (!AsmMatchConverter.empty()) {
1744 std::string Signature = "ConvertCustom_" + AsmMatchConverter;
1745 II->ConversionFnKind = Signature;
1747 // Check if we have already generated this signature.
1748 if (!InstructionConversionKinds.insert(Signature))
1751 // Remember this converter for the kind enum.
1752 unsigned KindID = OperandConversionKinds.size();
1753 OperandConversionKinds.insert("CVT_" +
1754 getEnumNameForToken(AsmMatchConverter));
1756 // Add the converter row for this instruction.
1757 ConversionTable.push_back(std::vector<uint8_t>());
1758 ConversionTable.back().push_back(KindID);
1759 ConversionTable.back().push_back(CVT_Done);
1761 // Add the handler to the conversion driver function.
1762 CvtOS << " case CVT_"
1763 << getEnumNameForToken(AsmMatchConverter) << ":\n"
1764 << " " << AsmMatchConverter << "(Inst, Operands);\n"
1767 // FIXME: Handle the operand number lookup for custom match functions.
1771 // Build the conversion function signature.
1772 std::string Signature = "Convert";
1774 std::vector<uint8_t> ConversionRow;
1776 // Compute the convert enum and the case body.
1777 MaxRowLength = std::max(MaxRowLength, II->ResOperands.size()*2 + 1 );
1779 for (unsigned i = 0, e = II->ResOperands.size(); i != e; ++i) {
1780 const MatchableInfo::ResOperand &OpInfo = II->ResOperands[i];
1782 // Generate code to populate each result operand.
1783 switch (OpInfo.Kind) {
1784 case MatchableInfo::ResOperand::RenderAsmOperand: {
1785 // This comes from something we parsed.
1786 const MatchableInfo::AsmOperand &Op =
1787 II->AsmOperands[OpInfo.AsmOperandNum];
1789 // Registers are always converted the same, don't duplicate the
1790 // conversion function based on them.
1793 Class = Op.Class->isRegisterClass() ? "Reg" : Op.Class->ClassName;
1795 Signature += utostr(OpInfo.MINumOperands);
1796 Signature += "_" + itostr(OpInfo.AsmOperandNum);
1798 // Add the conversion kind, if necessary, and get the associated ID
1799 // the index of its entry in the vector).
1800 std::string Name = "CVT_" + (Op.Class->isRegisterClass() ? "Reg" :
1801 Op.Class->RenderMethod);
1802 Name = getEnumNameForToken(Name);
1804 bool IsNewConverter = false;
1805 unsigned ID = getConverterOperandID(Name, OperandConversionKinds,
1808 // Add the operand entry to the instruction kind conversion row.
1809 ConversionRow.push_back(ID);
1810 ConversionRow.push_back(OpInfo.AsmOperandNum + 1);
1812 if (!IsNewConverter)
1815 // This is a new operand kind. Add a handler for it to the
1816 // converter driver.
1817 CvtOS << " case " << Name << ":\n"
1818 << " static_cast<" << TargetOperandClass
1819 << "&>(*Operands[*(p + 1)])." << Op.Class->RenderMethod
1820 << "(Inst, " << OpInfo.MINumOperands << ");\n"
1823 // Add a handler for the operand number lookup.
1824 OpOS << " case " << Name << ":\n"
1825 << " Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n";
1827 if (Op.Class->isRegisterClass())
1828 OpOS << " Operands[*(p + 1)]->setConstraint(\"r\");\n";
1830 OpOS << " Operands[*(p + 1)]->setConstraint(\"m\");\n";
1831 OpOS << " NumMCOperands += " << OpInfo.MINumOperands << ";\n"
1835 case MatchableInfo::ResOperand::TiedOperand: {
1836 // If this operand is tied to a previous one, just copy the MCInst
1837 // operand from the earlier one.We can only tie single MCOperand values.
1838 assert(OpInfo.MINumOperands == 1 && "Not a singular MCOperand");
1839 unsigned TiedOp = OpInfo.TiedOperandNum;
1840 assert(i > TiedOp && "Tied operand precedes its target!");
1841 Signature += "__Tie" + utostr(TiedOp);
1842 ConversionRow.push_back(CVT_Tied);
1843 ConversionRow.push_back(TiedOp);
1846 case MatchableInfo::ResOperand::ImmOperand: {
1847 int64_t Val = OpInfo.ImmVal;
1848 std::string Ty = "imm_" + itostr(Val);
1849 Signature += "__" + Ty;
1851 std::string Name = "CVT_" + Ty;
1852 bool IsNewConverter = false;
1853 unsigned ID = getConverterOperandID(Name, OperandConversionKinds,
1855 // Add the operand entry to the instruction kind conversion row.
1856 ConversionRow.push_back(ID);
1857 ConversionRow.push_back(0);
1859 if (!IsNewConverter)
1862 CvtOS << " case " << Name << ":\n"
1863 << " Inst.addOperand(MCOperand::CreateImm(" << Val << "));\n"
1866 OpOS << " case " << Name << ":\n"
1867 << " Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n"
1868 << " Operands[*(p + 1)]->setConstraint(\"\");\n"
1869 << " ++NumMCOperands;\n"
1873 case MatchableInfo::ResOperand::RegOperand: {
1874 std::string Reg, Name;
1875 if (!OpInfo.Register) {
1879 Reg = getQualifiedName(OpInfo.Register);
1880 Name = "reg" + OpInfo.Register->getName();
1882 Signature += "__" + Name;
1883 Name = "CVT_" + Name;
1884 bool IsNewConverter = false;
1885 unsigned ID = getConverterOperandID(Name, OperandConversionKinds,
1887 // Add the operand entry to the instruction kind conversion row.
1888 ConversionRow.push_back(ID);
1889 ConversionRow.push_back(0);
1891 if (!IsNewConverter)
1893 CvtOS << " case " << Name << ":\n"
1894 << " Inst.addOperand(MCOperand::CreateReg(" << Reg << "));\n"
1897 OpOS << " case " << Name << ":\n"
1898 << " Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n"
1899 << " Operands[*(p + 1)]->setConstraint(\"m\");\n"
1900 << " ++NumMCOperands;\n"
1906 // If there were no operands, add to the signature to that effect
1907 if (Signature == "Convert")
1908 Signature += "_NoOperands";
1910 II->ConversionFnKind = Signature;
1912 // Save the signature. If we already have it, don't add a new row
1914 if (!InstructionConversionKinds.insert(Signature))
1917 // Add the row to the table.
1918 ConversionTable.push_back(ConversionRow);
1921 // Finish up the converter driver function.
1922 CvtOS << " }\n }\n}\n\n";
1924 // Finish up the operand number lookup function.
1925 OpOS << " }\n }\n}\n\n";
1927 OS << "namespace {\n";
1929 // Output the operand conversion kind enum.
1930 OS << "enum OperatorConversionKind {\n";
1931 for (unsigned i = 0, e = OperandConversionKinds.size(); i != e; ++i)
1932 OS << " " << OperandConversionKinds[i] << ",\n";
1933 OS << " CVT_NUM_CONVERTERS\n";
1936 // Output the instruction conversion kind enum.
1937 OS << "enum InstructionConversionKind {\n";
1938 for (SetVector<std::string>::const_iterator
1939 i = InstructionConversionKinds.begin(),
1940 e = InstructionConversionKinds.end(); i != e; ++i)
1941 OS << " " << *i << ",\n";
1942 OS << " CVT_NUM_SIGNATURES\n";
1946 OS << "} // end anonymous namespace\n\n";
1948 // Output the conversion table.
1949 OS << "static const uint8_t ConversionTable[CVT_NUM_SIGNATURES]["
1950 << MaxRowLength << "] = {\n";
1952 for (unsigned Row = 0, ERow = ConversionTable.size(); Row != ERow; ++Row) {
1953 assert(ConversionTable[Row].size() % 2 == 0 && "bad conversion row!");
1954 OS << " // " << InstructionConversionKinds[Row] << "\n";
1956 for (unsigned i = 0, e = ConversionTable[Row].size(); i != e; i += 2)
1957 OS << OperandConversionKinds[ConversionTable[Row][i]] << ", "
1958 << (unsigned)(ConversionTable[Row][i + 1]) << ", ";
1959 OS << "CVT_Done },\n";
1964 // Spit out the conversion driver function.
1967 // Spit out the operand number lookup function.
1971 /// emitMatchClassEnumeration - Emit the enumeration for match class kinds.
1972 static void emitMatchClassEnumeration(CodeGenTarget &Target,
1973 std::vector<ClassInfo*> &Infos,
1975 OS << "namespace {\n\n";
1977 OS << "/// MatchClassKind - The kinds of classes which participate in\n"
1978 << "/// instruction matching.\n";
1979 OS << "enum MatchClassKind {\n";
1980 OS << " InvalidMatchClass = 0,\n";
1981 for (const ClassInfo *CI : Infos) {
1982 OS << " " << CI->Name << ", // ";
1983 if (CI->Kind == ClassInfo::Token) {
1984 OS << "'" << CI->ValueName << "'\n";
1985 } else if (CI->isRegisterClass()) {
1986 if (!CI->ValueName.empty())
1987 OS << "register class '" << CI->ValueName << "'\n";
1989 OS << "derived register class\n";
1991 OS << "user defined class '" << CI->ValueName << "'\n";
1994 OS << " NumMatchClassKinds\n";
2000 /// emitValidateOperandClass - Emit the function to validate an operand class.
2001 static void emitValidateOperandClass(AsmMatcherInfo &Info,
2003 OS << "static unsigned validateOperandClass(MCParsedAsmOperand &GOp, "
2004 << "MatchClassKind Kind) {\n";
2005 OS << " " << Info.Target.getName() << "Operand &Operand = ("
2006 << Info.Target.getName() << "Operand&)GOp;\n";
2008 // The InvalidMatchClass is not to match any operand.
2009 OS << " if (Kind == InvalidMatchClass)\n";
2010 OS << " return MCTargetAsmParser::Match_InvalidOperand;\n\n";
2012 // Check for Token operands first.
2013 // FIXME: Use a more specific diagnostic type.
2014 OS << " if (Operand.isToken())\n";
2015 OS << " return isSubclass(matchTokenString(Operand.getToken()), Kind) ?\n"
2016 << " MCTargetAsmParser::Match_Success :\n"
2017 << " MCTargetAsmParser::Match_InvalidOperand;\n\n";
2019 // Check the user classes. We don't care what order since we're only
2020 // actually matching against one of them.
2021 for (const ClassInfo *CI : Info.Classes) {
2022 if (!CI->isUserClass())
2025 OS << " // '" << CI->ClassName << "' class\n";
2026 OS << " if (Kind == " << CI->Name << ") {\n";
2027 OS << " if (Operand." << CI->PredicateMethod << "())\n";
2028 OS << " return MCTargetAsmParser::Match_Success;\n";
2029 if (!CI->DiagnosticType.empty())
2030 OS << " return " << Info.Target.getName() << "AsmParser::Match_"
2031 << CI->DiagnosticType << ";\n";
2035 // Check for register operands, including sub-classes.
2036 OS << " if (Operand.isReg()) {\n";
2037 OS << " MatchClassKind OpKind;\n";
2038 OS << " switch (Operand.getReg()) {\n";
2039 OS << " default: OpKind = InvalidMatchClass; break;\n";
2040 for (const auto &RC : Info.RegisterClasses)
2041 OS << " case " << Info.Target.getName() << "::"
2042 << RC.first->getName() << ": OpKind = " << RC.second->Name
2045 OS << " return isSubclass(OpKind, Kind) ? "
2046 << "MCTargetAsmParser::Match_Success :\n "
2047 << " MCTargetAsmParser::Match_InvalidOperand;\n }\n\n";
2049 // Generic fallthrough match failure case for operands that don't have
2050 // specialized diagnostic types.
2051 OS << " return MCTargetAsmParser::Match_InvalidOperand;\n";
2055 /// emitIsSubclass - Emit the subclass predicate function.
2056 static void emitIsSubclass(CodeGenTarget &Target,
2057 std::vector<ClassInfo*> &Infos,
2059 OS << "/// isSubclass - Compute whether \\p A is a subclass of \\p B.\n";
2060 OS << "static bool isSubclass(MatchClassKind A, MatchClassKind B) {\n";
2061 OS << " if (A == B)\n";
2062 OS << " return true;\n\n";
2065 raw_string_ostream SS(OStr);
2067 SS << " switch (A) {\n";
2068 SS << " default:\n";
2069 SS << " return false;\n";
2070 for (const ClassInfo *A : Infos) {
2071 std::vector<StringRef> SuperClasses;
2072 for (const ClassInfo *B : Infos) {
2073 if (A != B && A->isSubsetOf(*B))
2074 SuperClasses.push_back(B->Name);
2077 if (SuperClasses.empty())
2081 SS << "\n case " << A->Name << ":\n";
2083 if (SuperClasses.size() == 1) {
2084 SS << " return B == " << SuperClasses.back().str() << ";\n";
2088 if (!SuperClasses.empty()) {
2089 SS << " switch (B) {\n";
2090 SS << " default: return false;\n";
2091 for (unsigned i = 0, e = SuperClasses.size(); i != e; ++i)
2092 SS << " case " << SuperClasses[i].str() << ": return true;\n";
2095 // No case statement to emit
2096 SS << " return false;\n";
2101 // If there were case statements emitted into the string stream, write them
2102 // to the output stream, otherwise write the default.
2106 OS << " return false;\n";
2111 /// emitMatchTokenString - Emit the function to match a token string to the
2112 /// appropriate match class value.
2113 static void emitMatchTokenString(CodeGenTarget &Target,
2114 std::vector<ClassInfo*> &Infos,
2116 // Construct the match list.
2117 std::vector<StringMatcher::StringPair> Matches;
2118 for (const ClassInfo *CI : Infos) {
2119 if (CI->Kind == ClassInfo::Token)
2120 Matches.push_back(StringMatcher::StringPair(CI->ValueName,
2121 "return " + CI->Name + ";"));
2124 OS << "static MatchClassKind matchTokenString(StringRef Name) {\n";
2126 StringMatcher("Name", Matches, OS).Emit();
2128 OS << " return InvalidMatchClass;\n";
2132 /// emitMatchRegisterName - Emit the function to match a string to the target
2133 /// specific register enum.
2134 static void emitMatchRegisterName(CodeGenTarget &Target, Record *AsmParser,
2136 // Construct the match list.
2137 std::vector<StringMatcher::StringPair> Matches;
2138 const std::vector<CodeGenRegister*> &Regs =
2139 Target.getRegBank().getRegisters();
2140 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
2141 const CodeGenRegister *Reg = Regs[i];
2142 if (Reg->TheDef->getValueAsString("AsmName").empty())
2145 Matches.push_back(StringMatcher::StringPair(
2146 Reg->TheDef->getValueAsString("AsmName"),
2147 "return " + utostr(Reg->EnumValue) + ";"));
2150 OS << "static unsigned MatchRegisterName(StringRef Name) {\n";
2152 StringMatcher("Name", Matches, OS).Emit();
2154 OS << " return 0;\n";
2158 static const char *getMinimalTypeForRange(uint64_t Range) {
2159 assert(Range <= 0xFFFFFFFFFFFFFFFFULL && "Enum too large");
2160 if (Range > 0xFFFFFFFFULL)
2169 static const char *getMinimalRequiredFeaturesType(const AsmMatcherInfo &Info) {
2170 uint64_t MaxIndex = Info.SubtargetFeatures.size();
2173 return getMinimalTypeForRange(1ULL << MaxIndex);
2176 /// emitSubtargetFeatureFlagEnumeration - Emit the subtarget feature flag
2178 static void emitSubtargetFeatureFlagEnumeration(AsmMatcherInfo &Info,
2180 OS << "// Flags for subtarget features that participate in "
2181 << "instruction matching.\n";
2182 OS << "enum SubtargetFeatureFlag : " << getMinimalRequiredFeaturesType(Info)
2184 for (const auto &SF : Info.SubtargetFeatures) {
2185 SubtargetFeatureInfo &SFI = *SF.second;
2186 OS << " " << SFI.getEnumName() << " = (1ULL << " << SFI.Index << "),\n";
2188 OS << " Feature_None = 0\n";
2192 /// emitOperandDiagnosticTypes - Emit the operand matching diagnostic types.
2193 static void emitOperandDiagnosticTypes(AsmMatcherInfo &Info, raw_ostream &OS) {
2194 // Get the set of diagnostic types from all of the operand classes.
2195 std::set<StringRef> Types;
2196 for (std::map<Record*, ClassInfo*>::const_iterator
2197 I = Info.AsmOperandClasses.begin(),
2198 E = Info.AsmOperandClasses.end(); I != E; ++I) {
2199 if (!I->second->DiagnosticType.empty())
2200 Types.insert(I->second->DiagnosticType);
2203 if (Types.empty()) return;
2205 // Now emit the enum entries.
2206 for (std::set<StringRef>::const_iterator I = Types.begin(), E = Types.end();
2208 OS << " Match_" << *I << ",\n";
2209 OS << " END_OPERAND_DIAGNOSTIC_TYPES\n";
2212 /// emitGetSubtargetFeatureName - Emit the helper function to get the
2213 /// user-level name for a subtarget feature.
2214 static void emitGetSubtargetFeatureName(AsmMatcherInfo &Info, raw_ostream &OS) {
2215 OS << "// User-level names for subtarget features that participate in\n"
2216 << "// instruction matching.\n"
2217 << "static const char *getSubtargetFeatureName(uint64_t Val) {\n";
2218 if (!Info.SubtargetFeatures.empty()) {
2219 OS << " switch(Val) {\n";
2220 for (const auto &SF : Info.SubtargetFeatures) {
2221 SubtargetFeatureInfo &SFI = *SF.second;
2222 // FIXME: Totally just a placeholder name to get the algorithm working.
2223 OS << " case " << SFI.getEnumName() << ": return \""
2224 << SFI.TheDef->getValueAsString("PredicateName") << "\";\n";
2226 OS << " default: return \"(unknown)\";\n";
2229 // Nothing to emit, so skip the switch
2230 OS << " return \"(unknown)\";\n";
2235 /// emitComputeAvailableFeatures - Emit the function to compute the list of
2236 /// available features given a subtarget.
2237 static void emitComputeAvailableFeatures(AsmMatcherInfo &Info,
2239 std::string ClassName =
2240 Info.AsmParser->getValueAsString("AsmParserClassName");
2242 OS << "uint64_t " << Info.Target.getName() << ClassName << "::\n"
2243 << "ComputeAvailableFeatures(uint64_t FB) const {\n";
2244 OS << " uint64_t Features = 0;\n";
2245 for (const auto &SF : Info.SubtargetFeatures) {
2246 SubtargetFeatureInfo &SFI = *SF.second;
2249 std::string CondStorage =
2250 SFI.TheDef->getValueAsString("AssemblerCondString");
2251 StringRef Conds = CondStorage;
2252 std::pair<StringRef,StringRef> Comma = Conds.split(',');
2259 StringRef Cond = Comma.first;
2260 if (Cond[0] == '!') {
2262 Cond = Cond.substr(1);
2265 OS << "((FB & " << Info.Target.getName() << "::" << Cond << ")";
2272 if (Comma.second.empty())
2276 Comma = Comma.second.split(',');
2280 OS << " Features |= " << SFI.getEnumName() << ";\n";
2282 OS << " return Features;\n";
2286 static std::string GetAliasRequiredFeatures(Record *R,
2287 const AsmMatcherInfo &Info) {
2288 std::vector<Record*> ReqFeatures = R->getValueAsListOfDefs("Predicates");
2290 unsigned NumFeatures = 0;
2291 for (unsigned i = 0, e = ReqFeatures.size(); i != e; ++i) {
2292 SubtargetFeatureInfo *F = Info.getSubtargetFeature(ReqFeatures[i]);
2295 PrintFatalError(R->getLoc(), "Predicate '" + ReqFeatures[i]->getName() +
2296 "' is not marked as an AssemblerPredicate!");
2301 Result += F->getEnumName();
2305 if (NumFeatures > 1)
2306 Result = '(' + Result + ')';
2310 static void emitMnemonicAliasVariant(raw_ostream &OS,const AsmMatcherInfo &Info,
2311 std::vector<Record*> &Aliases,
2312 unsigned Indent = 0,
2313 StringRef AsmParserVariantName = StringRef()){
2314 // Keep track of all the aliases from a mnemonic. Use an std::map so that the
2315 // iteration order of the map is stable.
2316 std::map<std::string, std::vector<Record*> > AliasesFromMnemonic;
2318 for (unsigned i = 0, e = Aliases.size(); i != e; ++i) {
2319 Record *R = Aliases[i];
2320 // FIXME: Allow AssemblerVariantName to be a comma separated list.
2321 std::string AsmVariantName = R->getValueAsString("AsmVariantName");
2322 if (AsmVariantName != AsmParserVariantName)
2324 AliasesFromMnemonic[R->getValueAsString("FromMnemonic")].push_back(R);
2326 if (AliasesFromMnemonic.empty())
2329 // Process each alias a "from" mnemonic at a time, building the code executed
2330 // by the string remapper.
2331 std::vector<StringMatcher::StringPair> Cases;
2332 for (std::map<std::string, std::vector<Record*> >::iterator
2333 I = AliasesFromMnemonic.begin(), E = AliasesFromMnemonic.end();
2335 const std::vector<Record*> &ToVec = I->second;
2337 // Loop through each alias and emit code that handles each case. If there
2338 // are two instructions without predicates, emit an error. If there is one,
2340 std::string MatchCode;
2341 int AliasWithNoPredicate = -1;
2343 for (unsigned i = 0, e = ToVec.size(); i != e; ++i) {
2344 Record *R = ToVec[i];
2345 std::string FeatureMask = GetAliasRequiredFeatures(R, Info);
2347 // If this unconditionally matches, remember it for later and diagnose
2349 if (FeatureMask.empty()) {
2350 if (AliasWithNoPredicate != -1) {
2351 // We can't have two aliases from the same mnemonic with no predicate.
2352 PrintError(ToVec[AliasWithNoPredicate]->getLoc(),
2353 "two MnemonicAliases with the same 'from' mnemonic!");
2354 PrintFatalError(R->getLoc(), "this is the other MnemonicAlias.");
2357 AliasWithNoPredicate = i;
2360 if (R->getValueAsString("ToMnemonic") == I->first)
2361 PrintFatalError(R->getLoc(), "MnemonicAlias to the same string");
2363 if (!MatchCode.empty())
2364 MatchCode += "else ";
2365 MatchCode += "if ((Features & " + FeatureMask + ") == "+FeatureMask+")\n";
2366 MatchCode += " Mnemonic = \"" +R->getValueAsString("ToMnemonic")+"\";\n";
2369 if (AliasWithNoPredicate != -1) {
2370 Record *R = ToVec[AliasWithNoPredicate];
2371 if (!MatchCode.empty())
2372 MatchCode += "else\n ";
2373 MatchCode += "Mnemonic = \"" + R->getValueAsString("ToMnemonic")+"\";\n";
2376 MatchCode += "return;";
2378 Cases.push_back(std::make_pair(I->first, MatchCode));
2380 StringMatcher("Mnemonic", Cases, OS).Emit(Indent);
2383 /// emitMnemonicAliases - If the target has any MnemonicAlias<> definitions,
2384 /// emit a function for them and return true, otherwise return false.
2385 static bool emitMnemonicAliases(raw_ostream &OS, const AsmMatcherInfo &Info,
2386 CodeGenTarget &Target) {
2387 // Ignore aliases when match-prefix is set.
2388 if (!MatchPrefix.empty())
2391 std::vector<Record*> Aliases =
2392 Info.getRecords().getAllDerivedDefinitions("MnemonicAlias");
2393 if (Aliases.empty()) return false;
2395 OS << "static void applyMnemonicAliases(StringRef &Mnemonic, "
2396 "uint64_t Features, unsigned VariantID) {\n";
2397 OS << " switch (VariantID) {\n";
2398 unsigned VariantCount = Target.getAsmParserVariantCount();
2399 for (unsigned VC = 0; VC != VariantCount; ++VC) {
2400 Record *AsmVariant = Target.getAsmParserVariant(VC);
2401 int AsmParserVariantNo = AsmVariant->getValueAsInt("Variant");
2402 std::string AsmParserVariantName = AsmVariant->getValueAsString("Name");
2403 OS << " case " << AsmParserVariantNo << ":\n";
2404 emitMnemonicAliasVariant(OS, Info, Aliases, /*Indent=*/2,
2405 AsmParserVariantName);
2410 // Emit aliases that apply to all variants.
2411 emitMnemonicAliasVariant(OS, Info, Aliases);
2418 static void emitCustomOperandParsing(raw_ostream &OS, CodeGenTarget &Target,
2419 const AsmMatcherInfo &Info, StringRef ClassName,
2420 StringToOffsetTable &StringTable,
2421 unsigned MaxMnemonicIndex) {
2422 unsigned MaxMask = 0;
2423 for (std::vector<OperandMatchEntry>::const_iterator it =
2424 Info.OperandMatchInfo.begin(), ie = Info.OperandMatchInfo.end();
2426 MaxMask |= it->OperandMask;
2429 // Emit the static custom operand parsing table;
2430 OS << "namespace {\n";
2431 OS << " struct OperandMatchEntry {\n";
2432 OS << " " << getMinimalRequiredFeaturesType(Info)
2433 << " RequiredFeatures;\n";
2434 OS << " " << getMinimalTypeForRange(MaxMnemonicIndex)
2436 OS << " " << getMinimalTypeForRange(Info.Classes.size())
2438 OS << " " << getMinimalTypeForRange(MaxMask)
2439 << " OperandMask;\n\n";
2440 OS << " StringRef getMnemonic() const {\n";
2441 OS << " return StringRef(MnemonicTable + Mnemonic + 1,\n";
2442 OS << " MnemonicTable[Mnemonic]);\n";
2446 OS << " // Predicate for searching for an opcode.\n";
2447 OS << " struct LessOpcodeOperand {\n";
2448 OS << " bool operator()(const OperandMatchEntry &LHS, StringRef RHS) {\n";
2449 OS << " return LHS.getMnemonic() < RHS;\n";
2451 OS << " bool operator()(StringRef LHS, const OperandMatchEntry &RHS) {\n";
2452 OS << " return LHS < RHS.getMnemonic();\n";
2454 OS << " bool operator()(const OperandMatchEntry &LHS,";
2455 OS << " const OperandMatchEntry &RHS) {\n";
2456 OS << " return LHS.getMnemonic() < RHS.getMnemonic();\n";
2460 OS << "} // end anonymous namespace.\n\n";
2462 OS << "static const OperandMatchEntry OperandMatchTable["
2463 << Info.OperandMatchInfo.size() << "] = {\n";
2465 OS << " /* Operand List Mask, Mnemonic, Operand Class, Features */\n";
2466 for (std::vector<OperandMatchEntry>::const_iterator it =
2467 Info.OperandMatchInfo.begin(), ie = Info.OperandMatchInfo.end();
2469 const OperandMatchEntry &OMI = *it;
2470 const MatchableInfo &II = *OMI.MI;
2474 // Write the required features mask.
2475 if (!II.RequiredFeatures.empty()) {
2476 for (unsigned i = 0, e = II.RequiredFeatures.size(); i != e; ++i) {
2478 OS << II.RequiredFeatures[i]->getEnumName();
2483 // Store a pascal-style length byte in the mnemonic.
2484 std::string LenMnemonic = char(II.Mnemonic.size()) + II.Mnemonic.str();
2485 OS << ", " << StringTable.GetOrAddStringOffset(LenMnemonic, false)
2486 << " /* " << II.Mnemonic << " */, ";
2490 OS << ", " << OMI.OperandMask;
2492 bool printComma = false;
2493 for (int i = 0, e = 31; i !=e; ++i)
2494 if (OMI.OperandMask & (1 << i)) {
2506 // Emit the operand class switch to call the correct custom parser for
2507 // the found operand class.
2508 OS << Target.getName() << ClassName << "::OperandMatchResultTy "
2509 << Target.getName() << ClassName << "::\n"
2510 << "tryCustomParseOperand(OperandVector"
2511 << " &Operands,\n unsigned MCK) {\n\n"
2512 << " switch(MCK) {\n";
2514 for (const ClassInfo *CI : Info.Classes) {
2515 if (CI->ParserMethod.empty())
2517 OS << " case " << CI->Name << ":\n"
2518 << " return " << CI->ParserMethod << "(Operands);\n";
2521 OS << " default:\n";
2522 OS << " return MatchOperand_NoMatch;\n";
2524 OS << " return MatchOperand_NoMatch;\n";
2527 // Emit the static custom operand parser. This code is very similar with
2528 // the other matcher. Also use MatchResultTy here just in case we go for
2529 // a better error handling.
2530 OS << Target.getName() << ClassName << "::OperandMatchResultTy "
2531 << Target.getName() << ClassName << "::\n"
2532 << "MatchOperandParserImpl(OperandVector"
2533 << " &Operands,\n StringRef Mnemonic) {\n";
2535 // Emit code to get the available features.
2536 OS << " // Get the current feature set.\n";
2537 OS << " uint64_t AvailableFeatures = getAvailableFeatures();\n\n";
2539 OS << " // Get the next operand index.\n";
2540 OS << " unsigned NextOpNum = Operands.size()-1;\n";
2542 // Emit code to search the table.
2543 OS << " // Search the table.\n";
2544 OS << " std::pair<const OperandMatchEntry*, const OperandMatchEntry*>";
2545 OS << " MnemonicRange =\n";
2546 OS << " std::equal_range(OperandMatchTable, OperandMatchTable+"
2547 << Info.OperandMatchInfo.size() << ", Mnemonic,\n"
2548 << " LessOpcodeOperand());\n\n";
2550 OS << " if (MnemonicRange.first == MnemonicRange.second)\n";
2551 OS << " return MatchOperand_NoMatch;\n\n";
2553 OS << " for (const OperandMatchEntry *it = MnemonicRange.first,\n"
2554 << " *ie = MnemonicRange.second; it != ie; ++it) {\n";
2556 OS << " // equal_range guarantees that instruction mnemonic matches.\n";
2557 OS << " assert(Mnemonic == it->getMnemonic());\n\n";
2559 // Emit check that the required features are available.
2560 OS << " // check if the available features match\n";
2561 OS << " if ((AvailableFeatures & it->RequiredFeatures) "
2562 << "!= it->RequiredFeatures) {\n";
2563 OS << " continue;\n";
2566 // Emit check to ensure the operand number matches.
2567 OS << " // check if the operand in question has a custom parser.\n";
2568 OS << " if (!(it->OperandMask & (1 << NextOpNum)))\n";
2569 OS << " continue;\n\n";
2571 // Emit call to the custom parser method
2572 OS << " // call custom parse method to handle the operand\n";
2573 OS << " OperandMatchResultTy Result = ";
2574 OS << "tryCustomParseOperand(Operands, it->Class);\n";
2575 OS << " if (Result != MatchOperand_NoMatch)\n";
2576 OS << " return Result;\n";
2579 OS << " // Okay, we had no match.\n";
2580 OS << " return MatchOperand_NoMatch;\n";
2584 void AsmMatcherEmitter::run(raw_ostream &OS) {
2585 CodeGenTarget Target(Records);
2586 Record *AsmParser = Target.getAsmParser();
2587 std::string ClassName = AsmParser->getValueAsString("AsmParserClassName");
2589 // Compute the information on the instructions to match.
2590 AsmMatcherInfo Info(AsmParser, Target, Records);
2593 // Sort the instruction table using the partial order on classes. We use
2594 // stable_sort to ensure that ambiguous instructions are still
2595 // deterministically ordered.
2596 std::stable_sort(Info.Matchables.begin(), Info.Matchables.end(),
2597 less_ptr<MatchableInfo>());
2599 DEBUG_WITH_TYPE("instruction_info", {
2600 for (const MatchableInfo *MI : Info.Matchables)
2604 // Check for ambiguous matchables.
2605 DEBUG_WITH_TYPE("ambiguous_instrs", {
2606 unsigned NumAmbiguous = 0;
2607 for (unsigned i = 0, e = Info.Matchables.size(); i != e; ++i) {
2608 for (unsigned j = i + 1; j != e; ++j) {
2609 const MatchableInfo &A = *Info.Matchables[i];
2610 const MatchableInfo &B = *Info.Matchables[j];
2612 if (A.couldMatchAmbiguouslyWith(B)) {
2613 errs() << "warning: ambiguous matchables:\n";
2615 errs() << "\nis incomparable with:\n";
2623 errs() << "warning: " << NumAmbiguous
2624 << " ambiguous matchables!\n";
2627 // Compute the information on the custom operand parsing.
2628 Info.buildOperandMatchInfo();
2630 // Write the output.
2632 // Information for the class declaration.
2633 OS << "\n#ifdef GET_ASSEMBLER_HEADER\n";
2634 OS << "#undef GET_ASSEMBLER_HEADER\n";
2635 OS << " // This should be included into the middle of the declaration of\n";
2636 OS << " // your subclasses implementation of MCTargetAsmParser.\n";
2637 OS << " uint64_t ComputeAvailableFeatures(uint64_t FeatureBits) const;\n";
2638 OS << " void convertToMCInst(unsigned Kind, MCInst &Inst, "
2639 << "unsigned Opcode,\n"
2640 << " const OperandVector "
2642 OS << " void convertToMapAndConstraints(unsigned Kind,\n ";
2643 OS << " const OperandVector &Operands) override;\n";
2644 OS << " bool mnemonicIsValid(StringRef Mnemonic, unsigned VariantID) override;\n";
2645 OS << " unsigned MatchInstructionImpl(\n";
2647 OS << "const OperandVector &Operands,\n"
2648 << " MCInst &Inst,\n"
2649 << " uint64_t &ErrorInfo,"
2650 << " bool matchingInlineAsm,\n"
2651 << " unsigned VariantID = 0);\n";
2653 if (Info.OperandMatchInfo.size()) {
2654 OS << "\n enum OperandMatchResultTy {\n";
2655 OS << " MatchOperand_Success, // operand matched successfully\n";
2656 OS << " MatchOperand_NoMatch, // operand did not match\n";
2657 OS << " MatchOperand_ParseFail // operand matched but had errors\n";
2659 OS << " OperandMatchResultTy MatchOperandParserImpl(\n";
2660 OS << " OperandVector &Operands,\n";
2661 OS << " StringRef Mnemonic);\n";
2663 OS << " OperandMatchResultTy tryCustomParseOperand(\n";
2664 OS << " OperandVector &Operands,\n";
2665 OS << " unsigned MCK);\n\n";
2668 OS << "#endif // GET_ASSEMBLER_HEADER_INFO\n\n";
2670 // Emit the operand match diagnostic enum names.
2671 OS << "\n#ifdef GET_OPERAND_DIAGNOSTIC_TYPES\n";
2672 OS << "#undef GET_OPERAND_DIAGNOSTIC_TYPES\n\n";
2673 emitOperandDiagnosticTypes(Info, OS);
2674 OS << "#endif // GET_OPERAND_DIAGNOSTIC_TYPES\n\n";
2677 OS << "\n#ifdef GET_REGISTER_MATCHER\n";
2678 OS << "#undef GET_REGISTER_MATCHER\n\n";
2680 // Emit the subtarget feature enumeration.
2681 emitSubtargetFeatureFlagEnumeration(Info, OS);
2683 // Emit the function to match a register name to number.
2684 // This should be omitted for Mips target
2685 if (AsmParser->getValueAsBit("ShouldEmitMatchRegisterName"))
2686 emitMatchRegisterName(Target, AsmParser, OS);
2688 OS << "#endif // GET_REGISTER_MATCHER\n\n";
2690 OS << "\n#ifdef GET_SUBTARGET_FEATURE_NAME\n";
2691 OS << "#undef GET_SUBTARGET_FEATURE_NAME\n\n";
2693 // Generate the helper function to get the names for subtarget features.
2694 emitGetSubtargetFeatureName(Info, OS);
2696 OS << "#endif // GET_SUBTARGET_FEATURE_NAME\n\n";
2698 OS << "\n#ifdef GET_MATCHER_IMPLEMENTATION\n";
2699 OS << "#undef GET_MATCHER_IMPLEMENTATION\n\n";
2701 // Generate the function that remaps for mnemonic aliases.
2702 bool HasMnemonicAliases = emitMnemonicAliases(OS, Info, Target);
2704 // Generate the convertToMCInst function to convert operands into an MCInst.
2705 // Also, generate the convertToMapAndConstraints function for MS-style inline
2706 // assembly. The latter doesn't actually generate a MCInst.
2707 emitConvertFuncs(Target, ClassName, Info.Matchables, OS);
2709 // Emit the enumeration for classes which participate in matching.
2710 emitMatchClassEnumeration(Target, Info.Classes, OS);
2712 // Emit the routine to match token strings to their match class.
2713 emitMatchTokenString(Target, Info.Classes, OS);
2715 // Emit the subclass predicate routine.
2716 emitIsSubclass(Target, Info.Classes, OS);
2718 // Emit the routine to validate an operand against a match class.
2719 emitValidateOperandClass(Info, OS);
2721 // Emit the available features compute function.
2722 emitComputeAvailableFeatures(Info, OS);
2725 StringToOffsetTable StringTable;
2727 size_t MaxNumOperands = 0;
2728 unsigned MaxMnemonicIndex = 0;
2729 bool HasDeprecation = false;
2730 for (const MatchableInfo *MI : Info.Matchables) {
2731 MaxNumOperands = std::max(MaxNumOperands, MI->AsmOperands.size());
2732 HasDeprecation |= MI->HasDeprecation;
2734 // Store a pascal-style length byte in the mnemonic.
2735 std::string LenMnemonic = char(MI->Mnemonic.size()) + MI->Mnemonic.str();
2736 MaxMnemonicIndex = std::max(MaxMnemonicIndex,
2737 StringTable.GetOrAddStringOffset(LenMnemonic, false));
2740 OS << "static const char *const MnemonicTable =\n";
2741 StringTable.EmitString(OS);
2744 // Emit the static match table; unused classes get initalized to 0 which is
2745 // guaranteed to be InvalidMatchClass.
2747 // FIXME: We can reduce the size of this table very easily. First, we change
2748 // it so that store the kinds in separate bit-fields for each index, which
2749 // only needs to be the max width used for classes at that index (we also need
2750 // to reject based on this during classification). If we then make sure to
2751 // order the match kinds appropriately (putting mnemonics last), then we
2752 // should only end up using a few bits for each class, especially the ones
2753 // following the mnemonic.
2754 OS << "namespace {\n";
2755 OS << " struct MatchEntry {\n";
2756 OS << " " << getMinimalTypeForRange(MaxMnemonicIndex)
2758 OS << " uint16_t Opcode;\n";
2759 OS << " " << getMinimalTypeForRange(Info.Matchables.size())
2761 OS << " " << getMinimalRequiredFeaturesType(Info)
2762 << " RequiredFeatures;\n";
2763 OS << " " << getMinimalTypeForRange(Info.Classes.size())
2764 << " Classes[" << MaxNumOperands << "];\n";
2765 OS << " StringRef getMnemonic() const {\n";
2766 OS << " return StringRef(MnemonicTable + Mnemonic + 1,\n";
2767 OS << " MnemonicTable[Mnemonic]);\n";
2771 OS << " // Predicate for searching for an opcode.\n";
2772 OS << " struct LessOpcode {\n";
2773 OS << " bool operator()(const MatchEntry &LHS, StringRef RHS) {\n";
2774 OS << " return LHS.getMnemonic() < RHS;\n";
2776 OS << " bool operator()(StringRef LHS, const MatchEntry &RHS) {\n";
2777 OS << " return LHS < RHS.getMnemonic();\n";
2779 OS << " bool operator()(const MatchEntry &LHS, const MatchEntry &RHS) {\n";
2780 OS << " return LHS.getMnemonic() < RHS.getMnemonic();\n";
2784 OS << "} // end anonymous namespace.\n\n";
2786 unsigned VariantCount = Target.getAsmParserVariantCount();
2787 for (unsigned VC = 0; VC != VariantCount; ++VC) {
2788 Record *AsmVariant = Target.getAsmParserVariant(VC);
2789 int AsmVariantNo = AsmVariant->getValueAsInt("Variant");
2791 OS << "static const MatchEntry MatchTable" << VC << "[] = {\n";
2793 for (const MatchableInfo *MI : Info.Matchables) {
2794 if (MI->AsmVariantID != AsmVariantNo)
2797 // Store a pascal-style length byte in the mnemonic.
2798 std::string LenMnemonic = char(MI->Mnemonic.size()) + MI->Mnemonic.str();
2799 OS << " { " << StringTable.GetOrAddStringOffset(LenMnemonic, false)
2800 << " /* " << MI->Mnemonic << " */, "
2801 << Target.getName() << "::"
2802 << MI->getResultInst()->TheDef->getName() << ", "
2803 << MI->ConversionFnKind << ", ";
2805 // Write the required features mask.
2806 if (!MI->RequiredFeatures.empty()) {
2807 for (unsigned i = 0, e = MI->RequiredFeatures.size(); i != e; ++i) {
2809 OS << MI->RequiredFeatures[i]->getEnumName();
2815 for (unsigned i = 0, e = MI->AsmOperands.size(); i != e; ++i) {
2816 const MatchableInfo::AsmOperand &Op = MI->AsmOperands[i];
2819 OS << Op.Class->Name;
2827 // A method to determine if a mnemonic is in the list.
2828 OS << "bool " << Target.getName() << ClassName << "::\n"
2829 << "mnemonicIsValid(StringRef Mnemonic, unsigned VariantID) {\n";
2830 OS << " // Find the appropriate table for this asm variant.\n";
2831 OS << " const MatchEntry *Start, *End;\n";
2832 OS << " switch (VariantID) {\n";
2833 OS << " default: // unreachable\n";
2834 for (unsigned VC = 0; VC != VariantCount; ++VC) {
2835 Record *AsmVariant = Target.getAsmParserVariant(VC);
2836 int AsmVariantNo = AsmVariant->getValueAsInt("Variant");
2837 OS << " case " << AsmVariantNo << ": Start = std::begin(MatchTable" << VC
2838 << "); End = std::end(MatchTable" << VC << "); break;\n";
2841 OS << " // Search the table.\n";
2842 OS << " std::pair<const MatchEntry*, const MatchEntry*> MnemonicRange =\n";
2843 OS << " std::equal_range(Start, End, Mnemonic, LessOpcode());\n";
2844 OS << " return MnemonicRange.first != MnemonicRange.second;\n";
2847 // Finally, build the match function.
2848 OS << "unsigned " << Target.getName() << ClassName << "::\n"
2849 << "MatchInstructionImpl(const OperandVector"
2851 OS << " MCInst &Inst,\n"
2852 << "uint64_t &ErrorInfo, bool matchingInlineAsm, unsigned VariantID) {\n";
2854 OS << " // Eliminate obvious mismatches.\n";
2855 OS << " if (Operands.size() > " << (MaxNumOperands+1) << ") {\n";
2856 OS << " ErrorInfo = " << (MaxNumOperands+1) << ";\n";
2857 OS << " return Match_InvalidOperand;\n";
2860 // Emit code to get the available features.
2861 OS << " // Get the current feature set.\n";
2862 OS << " uint64_t AvailableFeatures = getAvailableFeatures();\n\n";
2864 OS << " // Get the instruction mnemonic, which is the first token.\n";
2865 OS << " StringRef Mnemonic = ((" << Target.getName()
2866 << "Operand&)*Operands[0]).getToken();\n\n";
2868 if (HasMnemonicAliases) {
2869 OS << " // Process all MnemonicAliases to remap the mnemonic.\n";
2870 OS << " applyMnemonicAliases(Mnemonic, AvailableFeatures, VariantID);\n\n";
2873 // Emit code to compute the class list for this operand vector.
2874 OS << " // Some state to try to produce better error messages.\n";
2875 OS << " bool HadMatchOtherThanFeatures = false;\n";
2876 OS << " bool HadMatchOtherThanPredicate = false;\n";
2877 OS << " unsigned RetCode = Match_InvalidOperand;\n";
2878 OS << " uint64_t MissingFeatures = ~0ULL;\n";
2879 OS << " // Set ErrorInfo to the operand that mismatches if it is\n";
2880 OS << " // wrong for all instances of the instruction.\n";
2881 OS << " ErrorInfo = ~0U;\n";
2883 // Emit code to search the table.
2884 OS << " // Find the appropriate table for this asm variant.\n";
2885 OS << " const MatchEntry *Start, *End;\n";
2886 OS << " switch (VariantID) {\n";
2887 OS << " default: // unreachable\n";
2888 for (unsigned VC = 0; VC != VariantCount; ++VC) {
2889 Record *AsmVariant = Target.getAsmParserVariant(VC);
2890 int AsmVariantNo = AsmVariant->getValueAsInt("Variant");
2891 OS << " case " << AsmVariantNo << ": Start = std::begin(MatchTable" << VC
2892 << "); End = std::end(MatchTable" << VC << "); break;\n";
2895 OS << " // Search the table.\n";
2896 OS << " std::pair<const MatchEntry*, const MatchEntry*> MnemonicRange =\n";
2897 OS << " std::equal_range(Start, End, Mnemonic, LessOpcode());\n\n";
2899 OS << " // Return a more specific error code if no mnemonics match.\n";
2900 OS << " if (MnemonicRange.first == MnemonicRange.second)\n";
2901 OS << " return Match_MnemonicFail;\n\n";
2903 OS << " for (const MatchEntry *it = MnemonicRange.first, "
2904 << "*ie = MnemonicRange.second;\n";
2905 OS << " it != ie; ++it) {\n";
2907 OS << " // equal_range guarantees that instruction mnemonic matches.\n";
2908 OS << " assert(Mnemonic == it->getMnemonic());\n";
2910 // Emit check that the subclasses match.
2911 OS << " bool OperandsValid = true;\n";
2912 OS << " for (unsigned i = 0; i != " << MaxNumOperands << "; ++i) {\n";
2913 OS << " if (i + 1 >= Operands.size()) {\n";
2914 OS << " OperandsValid = (it->Classes[i] == " <<"InvalidMatchClass);\n";
2915 OS << " if (!OperandsValid) ErrorInfo = i + 1;\n";
2918 OS << " unsigned Diag = validateOperandClass(*Operands[i+1],\n";
2920 OS << "(MatchClassKind)it->Classes[i]);\n";
2921 OS << " if (Diag == Match_Success)\n";
2922 OS << " continue;\n";
2923 OS << " // If the generic handler indicates an invalid operand\n";
2924 OS << " // failure, check for a special case.\n";
2925 OS << " if (Diag == Match_InvalidOperand) {\n";
2926 OS << " Diag = validateTargetOperandClass(*Operands[i+1],\n";
2928 OS << "(MatchClassKind)it->Classes[i]);\n";
2929 OS << " if (Diag == Match_Success)\n";
2930 OS << " continue;\n";
2932 OS << " // If this operand is broken for all of the instances of this\n";
2933 OS << " // mnemonic, keep track of it so we can report loc info.\n";
2934 OS << " // If we already had a match that only failed due to a\n";
2935 OS << " // target predicate, that diagnostic is preferred.\n";
2936 OS << " if (!HadMatchOtherThanPredicate &&\n";
2937 OS << " (it == MnemonicRange.first || ErrorInfo <= i+1)) {\n";
2938 OS << " ErrorInfo = i+1;\n";
2939 OS << " // InvalidOperand is the default. Prefer specificity.\n";
2940 OS << " if (Diag != Match_InvalidOperand)\n";
2941 OS << " RetCode = Diag;\n";
2943 OS << " // Otherwise, just reject this instance of the mnemonic.\n";
2944 OS << " OperandsValid = false;\n";
2948 OS << " if (!OperandsValid) continue;\n";
2950 // Emit check that the required features are available.
2951 OS << " if ((AvailableFeatures & it->RequiredFeatures) "
2952 << "!= it->RequiredFeatures) {\n";
2953 OS << " HadMatchOtherThanFeatures = true;\n";
2954 OS << " uint64_t NewMissingFeatures = it->RequiredFeatures & "
2955 "~AvailableFeatures;\n";
2956 OS << " if (CountPopulation_64(NewMissingFeatures) <=\n"
2957 " CountPopulation_64(MissingFeatures))\n";
2958 OS << " MissingFeatures = NewMissingFeatures;\n";
2959 OS << " continue;\n";
2962 OS << " if (matchingInlineAsm) {\n";
2963 OS << " Inst.setOpcode(it->Opcode);\n";
2964 OS << " convertToMapAndConstraints(it->ConvertFn, Operands);\n";
2965 OS << " return Match_Success;\n";
2967 OS << " // We have selected a definite instruction, convert the parsed\n"
2968 << " // operands into the appropriate MCInst.\n";
2969 OS << " convertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands);\n";
2972 // Verify the instruction with the target-specific match predicate function.
2973 OS << " // We have a potential match. Check the target predicate to\n"
2974 << " // handle any context sensitive constraints.\n"
2975 << " unsigned MatchResult;\n"
2976 << " if ((MatchResult = checkTargetMatchPredicate(Inst)) !="
2977 << " Match_Success) {\n"
2978 << " Inst.clear();\n"
2979 << " RetCode = MatchResult;\n"
2980 << " HadMatchOtherThanPredicate = true;\n"
2984 // Call the post-processing function, if used.
2985 std::string InsnCleanupFn =
2986 AsmParser->getValueAsString("AsmParserInstCleanup");
2987 if (!InsnCleanupFn.empty())
2988 OS << " " << InsnCleanupFn << "(Inst);\n";
2990 if (HasDeprecation) {
2991 OS << " std::string Info;\n";
2992 OS << " if (MII.get(Inst.getOpcode()).getDeprecatedInfo(Inst, STI, Info)) {\n";
2993 OS << " SMLoc Loc = ((" << Target.getName()
2994 << "Operand&)*Operands[0]).getStartLoc();\n";
2995 OS << " getParser().Warning(Loc, Info, None);\n";
2999 OS << " return Match_Success;\n";
3002 OS << " // Okay, we had no match. Try to return a useful error code.\n";
3003 OS << " if (HadMatchOtherThanPredicate || !HadMatchOtherThanFeatures)\n";
3004 OS << " return RetCode;\n\n";
3005 OS << " // Missing feature matches return which features were missing\n";
3006 OS << " ErrorInfo = MissingFeatures;\n";
3007 OS << " return Match_MissingFeature;\n";
3010 if (Info.OperandMatchInfo.size())
3011 emitCustomOperandParsing(OS, Target, Info, ClassName, StringTable,
3014 OS << "#endif // GET_MATCHER_IMPLEMENTATION\n\n";
3019 void EmitAsmMatcher(RecordKeeper &RK, raw_ostream &OS) {
3020 emitSourceFileHeader("Assembly Matcher Source Fragment", OS);
3021 AsmMatcherEmitter(RK).run(OS);
3024 } // End llvm namespace