1 //===- AsmMatcherEmitter.cpp - Generate an assembly matcher ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend emits a target specifier matcher for converting parsed
11 // assembly operands in the MCInst structures.
13 // The input to the target specific matcher is a list of literal tokens and
14 // operands. The target specific parser should generally eliminate any syntax
15 // which is not relevant for matching; for example, comma tokens should have
16 // already been consumed and eliminated by the parser. Most instructions will
17 // end up with a single literal token (the instruction name) and some number of
20 // Some example inputs, for X86:
21 // 'addl' (immediate ...) (register ...)
22 // 'add' (immediate ...) (memory ...)
25 // The assembly matcher is responsible for converting this input into a precise
26 // machine instruction (i.e., an instruction with a well defined encoding). This
27 // mapping has several properties which complicate matching:
29 // - It may be ambiguous; many architectures can legally encode particular
30 // variants of an instruction in different ways (for example, using a smaller
31 // encoding for small immediates). Such ambiguities should never be
32 // arbitrarily resolved by the assembler, the assembler is always responsible
33 // for choosing the "best" available instruction.
35 // - It may depend on the subtarget or the assembler context. Instructions
36 // which are invalid for the current mode, but otherwise unambiguous (e.g.,
37 // an SSE instruction in a file being assembled for i486) should be accepted
38 // and rejected by the assembler front end. However, if the proper encoding
39 // for an instruction is dependent on the assembler context then the matcher
40 // is responsible for selecting the correct machine instruction for the
43 // The core matching algorithm attempts to exploit the regularity in most
44 // instruction sets to quickly determine the set of possibly matching
45 // instructions, and the simplify the generated code. Additionally, this helps
46 // to ensure that the ambiguities are intentionally resolved by the user.
48 // The matching is divided into two distinct phases:
50 // 1. Classification: Each operand is mapped to the unique set which (a)
51 // contains it, and (b) is the largest such subset for which a single
52 // instruction could match all members.
54 // For register classes, we can generate these subgroups automatically. For
55 // arbitrary operands, we expect the user to define the classes and their
56 // relations to one another (for example, 8-bit signed immediates as a
57 // subset of 32-bit immediates).
59 // By partitioning the operands in this way, we guarantee that for any
60 // tuple of classes, any single instruction must match either all or none
61 // of the sets of operands which could classify to that tuple.
63 // In addition, the subset relation amongst classes induces a partial order
64 // on such tuples, which we use to resolve ambiguities.
66 // FIXME: What do we do if a crazy case shows up where this is the wrong
69 // 2. The input can now be treated as a tuple of classes (static tokens are
70 // simple singleton sets). Each such tuple should generally map to a single
71 // instruction (we currently ignore cases where this isn't true, whee!!!),
72 // which we can emit a simple matcher for.
74 //===----------------------------------------------------------------------===//
76 #include "AsmMatcherEmitter.h"
77 #include "CodeGenTarget.h"
79 #include "StringMatcher.h"
80 #include "llvm/ADT/OwningPtr.h"
81 #include "llvm/ADT/SmallVector.h"
82 #include "llvm/ADT/STLExtras.h"
83 #include "llvm/ADT/StringExtras.h"
84 #include "llvm/Support/CommandLine.h"
85 #include "llvm/Support/Debug.h"
91 static cl::opt<std::string>
92 MatchPrefix("match-prefix", cl::init(""),
93 cl::desc("Only match instructions with the given prefix"));
95 /// FlattenVariants - Flatten an .td file assembly string by selecting the
96 /// variant at index \arg N.
97 static std::string FlattenVariants(const std::string &AsmString,
99 StringRef Cur = AsmString;
100 std::string Res = "";
103 // Find the start of the next variant string.
104 size_t VariantsStart = 0;
105 for (size_t e = Cur.size(); VariantsStart != e; ++VariantsStart)
106 if (Cur[VariantsStart] == '{' &&
107 (VariantsStart == 0 || (Cur[VariantsStart-1] != '$' &&
108 Cur[VariantsStart-1] != '\\')))
111 // Add the prefix to the result.
112 Res += Cur.slice(0, VariantsStart);
113 if (VariantsStart == Cur.size())
116 ++VariantsStart; // Skip the '{'.
118 // Scan to the end of the variants string.
119 size_t VariantsEnd = VariantsStart;
120 unsigned NestedBraces = 1;
121 for (size_t e = Cur.size(); VariantsEnd != e; ++VariantsEnd) {
122 if (Cur[VariantsEnd] == '}' && Cur[VariantsEnd-1] != '\\') {
123 if (--NestedBraces == 0)
125 } else if (Cur[VariantsEnd] == '{')
129 // Select the Nth variant (or empty).
130 StringRef Selection = Cur.slice(VariantsStart, VariantsEnd);
131 for (unsigned i = 0; i != N; ++i)
132 Selection = Selection.split('|').second;
133 Res += Selection.split('|').first;
135 assert(VariantsEnd != Cur.size() &&
136 "Unterminated variants in assembly string!");
137 Cur = Cur.substr(VariantsEnd + 1);
143 /// TokenizeAsmString - Tokenize a simplified assembly string.
144 static void TokenizeAsmString(StringRef AsmString,
145 SmallVectorImpl<StringRef> &Tokens) {
148 for (unsigned i = 0, e = AsmString.size(); i != e; ++i) {
149 switch (AsmString[i]) {
158 Tokens.push_back(AsmString.slice(Prev, i));
161 if (!isspace(AsmString[i]) && AsmString[i] != ',')
162 Tokens.push_back(AsmString.substr(i, 1));
168 Tokens.push_back(AsmString.slice(Prev, i));
172 assert(i != AsmString.size() && "Invalid quoted character");
173 Tokens.push_back(AsmString.substr(i, 1));
178 // If this isn't "${", treat like a normal token.
179 if (i + 1 == AsmString.size() || AsmString[i + 1] != '{') {
181 Tokens.push_back(AsmString.slice(Prev, i));
189 Tokens.push_back(AsmString.slice(Prev, i));
193 StringRef::iterator End =
194 std::find(AsmString.begin() + i, AsmString.end(), '}');
195 assert(End != AsmString.end() && "Missing brace in operand reference!");
196 size_t EndPos = End - AsmString.begin();
197 Tokens.push_back(AsmString.slice(i, EndPos+1));
205 Tokens.push_back(AsmString.slice(Prev, i));
215 if (InTok && Prev != AsmString.size())
216 Tokens.push_back(AsmString.substr(Prev));
219 static bool IsAssemblerInstruction(StringRef Name,
220 const CodeGenInstruction &CGI,
221 const SmallVectorImpl<StringRef> &Tokens) {
222 // Ignore "codegen only" instructions.
223 if (CGI.TheDef->getValueAsBit("isCodeGenOnly"))
226 // Ignore pseudo ops.
228 // FIXME: This is a hack; can we convert these instructions to set the
229 // "codegen only" bit instead?
230 if (const RecordVal *Form = CGI.TheDef->getValue("Form"))
231 if (Form->getValue()->getAsString() == "Pseudo")
234 // Ignore "Int_*" and "*_Int" instructions, which are internal aliases.
236 // FIXME: This is a total hack.
237 if (StringRef(Name).startswith("Int_") || StringRef(Name).endswith("_Int"))
240 // Ignore instructions with no .s string.
242 // FIXME: What are these?
243 if (CGI.AsmString.empty())
246 // FIXME: Hack; ignore any instructions with a newline in them.
247 if (std::find(CGI.AsmString.begin(),
248 CGI.AsmString.end(), '\n') != CGI.AsmString.end())
251 // Ignore instructions with attributes, these are always fake instructions for
252 // simplifying codegen.
254 // FIXME: Is this true?
256 // Also, check for instructions which reference the operand multiple times;
257 // this implies a constraint we would not honor.
258 std::set<std::string> OperandNames;
259 for (unsigned i = 1, e = Tokens.size(); i < e; ++i) {
260 if (Tokens[i][0] == '$' &&
261 std::find(Tokens[i].begin(),
262 Tokens[i].end(), ':') != Tokens[i].end()) {
264 errs() << "warning: '" << Name << "': "
265 << "ignoring instruction; operand with attribute '"
266 << Tokens[i] << "'\n";
271 if (Tokens[i][0] == '$' && !OperandNames.insert(Tokens[i]).second) {
273 errs() << "warning: '" << Name << "': "
274 << "ignoring instruction with tied operand '"
275 << Tokens[i].str() << "'\n";
286 struct SubtargetFeatureInfo;
288 /// ClassInfo - Helper class for storing the information about a particular
289 /// class of operands which can be matched.
292 /// Invalid kind, for use as a sentinel value.
295 /// The class for a particular token.
298 /// The (first) register class, subsequent register classes are
299 /// RegisterClass0+1, and so on.
302 /// The (first) user defined class, subsequent user defined classes are
303 /// UserClass0+1, and so on.
307 /// Kind - The class kind, which is either a predefined kind, or (UserClass0 +
308 /// N) for the Nth user defined class.
311 /// SuperClasses - The super classes of this class. Note that for simplicities
312 /// sake user operands only record their immediate super class, while register
313 /// operands include all superclasses.
314 std::vector<ClassInfo*> SuperClasses;
316 /// Name - The full class name, suitable for use in an enum.
319 /// ClassName - The unadorned generic name for this class (e.g., Token).
320 std::string ClassName;
322 /// ValueName - The name of the value this class represents; for a token this
323 /// is the literal token string, for an operand it is the TableGen class (or
324 /// empty if this is a derived class).
325 std::string ValueName;
327 /// PredicateMethod - The name of the operand method to test whether the
328 /// operand matches this class; this is not valid for Token or register kinds.
329 std::string PredicateMethod;
331 /// RenderMethod - The name of the operand method to add this operand to an
332 /// MCInst; this is not valid for Token or register kinds.
333 std::string RenderMethod;
335 /// For register classes, the records for all the registers in this class.
336 std::set<Record*> Registers;
339 /// isRegisterClass() - Check if this is a register class.
340 bool isRegisterClass() const {
341 return Kind >= RegisterClass0 && Kind < UserClass0;
344 /// isUserClass() - Check if this is a user defined class.
345 bool isUserClass() const {
346 return Kind >= UserClass0;
349 /// isRelatedTo - Check whether this class is "related" to \arg RHS. Classes
350 /// are related if they are in the same class hierarchy.
351 bool isRelatedTo(const ClassInfo &RHS) const {
352 // Tokens are only related to tokens.
353 if (Kind == Token || RHS.Kind == Token)
354 return Kind == Token && RHS.Kind == Token;
356 // Registers classes are only related to registers classes, and only if
357 // their intersection is non-empty.
358 if (isRegisterClass() || RHS.isRegisterClass()) {
359 if (!isRegisterClass() || !RHS.isRegisterClass())
362 std::set<Record*> Tmp;
363 std::insert_iterator< std::set<Record*> > II(Tmp, Tmp.begin());
364 std::set_intersection(Registers.begin(), Registers.end(),
365 RHS.Registers.begin(), RHS.Registers.end(),
371 // Otherwise we have two users operands; they are related if they are in the
372 // same class hierarchy.
374 // FIXME: This is an oversimplification, they should only be related if they
375 // intersect, however we don't have that information.
376 assert(isUserClass() && RHS.isUserClass() && "Unexpected class!");
377 const ClassInfo *Root = this;
378 while (!Root->SuperClasses.empty())
379 Root = Root->SuperClasses.front();
381 const ClassInfo *RHSRoot = &RHS;
382 while (!RHSRoot->SuperClasses.empty())
383 RHSRoot = RHSRoot->SuperClasses.front();
385 return Root == RHSRoot;
388 /// isSubsetOf - Test whether this class is a subset of \arg RHS;
389 bool isSubsetOf(const ClassInfo &RHS) const {
390 // This is a subset of RHS if it is the same class...
394 // ... or if any of its super classes are a subset of RHS.
395 for (std::vector<ClassInfo*>::const_iterator it = SuperClasses.begin(),
396 ie = SuperClasses.end(); it != ie; ++it)
397 if ((*it)->isSubsetOf(RHS))
403 /// operator< - Compare two classes.
404 bool operator<(const ClassInfo &RHS) const {
408 // Unrelated classes can be ordered by kind.
409 if (!isRelatedTo(RHS))
410 return Kind < RHS.Kind;
414 assert(0 && "Invalid kind!");
416 // Tokens are comparable by value.
418 // FIXME: Compare by enum value.
419 return ValueName < RHS.ValueName;
422 // This class preceeds the RHS if it is a proper subset of the RHS.
425 if (RHS.isSubsetOf(*this))
428 // Otherwise, order by name to ensure we have a total ordering.
429 return ValueName < RHS.ValueName;
434 /// InstructionInfo - Helper class for storing the necessary information for an
435 /// instruction which is capable of being matched.
436 struct InstructionInfo {
438 /// The unique class instance this operand should match.
441 /// The original operand this corresponds to, if any.
442 const CodeGenInstruction::OperandInfo *OperandInfo;
445 /// InstrName - The target name for this instruction.
446 std::string InstrName;
448 /// Instr - The instruction this matches.
449 const CodeGenInstruction *Instr;
451 /// AsmString - The assembly string for this instruction (with variants
453 std::string AsmString;
455 /// Tokens - The tokenized assembly pattern that this instruction matches.
456 SmallVector<StringRef, 4> Tokens;
458 /// Operands - The operands that this instruction matches.
459 SmallVector<Operand, 4> Operands;
461 /// Predicates - The required subtarget features to match this instruction.
462 SmallVector<SubtargetFeatureInfo*, 4> RequiredFeatures;
464 /// ConversionFnKind - The enum value which is passed to the generated
465 /// ConvertToMCInst to convert parsed operands into an MCInst for this
467 std::string ConversionFnKind;
469 /// operator< - Compare two instructions.
470 bool operator<(const InstructionInfo &RHS) const {
471 if (Operands.size() != RHS.Operands.size())
472 return Operands.size() < RHS.Operands.size();
474 // Compare lexicographically by operand. The matcher validates that other
475 // orderings wouldn't be ambiguous using \see CouldMatchAmiguouslyWith().
476 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
477 if (*Operands[i].Class < *RHS.Operands[i].Class)
479 if (*RHS.Operands[i].Class < *Operands[i].Class)
486 /// CouldMatchAmiguouslyWith - Check whether this instruction could
487 /// ambiguously match the same set of operands as \arg RHS (without being a
488 /// strictly superior match).
489 bool CouldMatchAmiguouslyWith(const InstructionInfo &RHS) {
490 // The number of operands is unambiguous.
491 if (Operands.size() != RHS.Operands.size())
494 // Otherwise, make sure the ordering of the two instructions is unambiguous
495 // by checking that either (a) a token or operand kind discriminates them,
496 // or (b) the ordering among equivalent kinds is consistent.
498 // Tokens and operand kinds are unambiguous (assuming a correct target
500 for (unsigned i = 0, e = Operands.size(); i != e; ++i)
501 if (Operands[i].Class->Kind != RHS.Operands[i].Class->Kind ||
502 Operands[i].Class->Kind == ClassInfo::Token)
503 if (*Operands[i].Class < *RHS.Operands[i].Class ||
504 *RHS.Operands[i].Class < *Operands[i].Class)
507 // Otherwise, this operand could commute if all operands are equivalent, or
508 // there is a pair of operands that compare less than and a pair that
509 // compare greater than.
510 bool HasLT = false, HasGT = false;
511 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
512 if (*Operands[i].Class < *RHS.Operands[i].Class)
514 if (*RHS.Operands[i].Class < *Operands[i].Class)
518 return !(HasLT ^ HasGT);
525 /// SubtargetFeatureInfo - Helper class for storing information on a subtarget
526 /// feature which participates in instruction matching.
527 struct SubtargetFeatureInfo {
528 /// \brief The predicate record for this feature.
531 /// \brief An unique index assigned to represent this feature.
534 /// \brief The name of the enumerated constant identifying this feature.
535 std::string EnumName;
538 class AsmMatcherInfo {
540 /// The tablegen AsmParser record.
543 /// The AsmParser "CommentDelimiter" value.
544 std::string CommentDelimiter;
546 /// The AsmParser "RegisterPrefix" value.
547 std::string RegisterPrefix;
549 /// The classes which are needed for matching.
550 std::vector<ClassInfo*> Classes;
552 /// The information on the instruction to match.
553 std::vector<InstructionInfo*> Instructions;
555 /// Map of Register records to their class information.
556 std::map<Record*, ClassInfo*> RegisterClasses;
558 /// Map of Predicate records to their subtarget information.
559 std::map<Record*, SubtargetFeatureInfo*> SubtargetFeatures;
562 /// Map of token to class information which has already been constructed.
563 std::map<std::string, ClassInfo*> TokenClasses;
565 /// Map of RegisterClass records to their class information.
566 std::map<Record*, ClassInfo*> RegisterClassClasses;
568 /// Map of AsmOperandClass records to their class information.
569 std::map<Record*, ClassInfo*> AsmOperandClasses;
572 /// getTokenClass - Lookup or create the class for the given token.
573 ClassInfo *getTokenClass(StringRef Token);
575 /// getOperandClass - Lookup or create the class for the given operand.
576 ClassInfo *getOperandClass(StringRef Token,
577 const CodeGenInstruction::OperandInfo &OI);
579 /// getSubtargetFeature - Lookup or create the subtarget feature info for the
581 SubtargetFeatureInfo *getSubtargetFeature(Record *Def) {
582 assert(Def->isSubClassOf("Predicate") && "Invalid predicate type!");
584 SubtargetFeatureInfo *&Entry = SubtargetFeatures[Def];
586 Entry = new SubtargetFeatureInfo;
588 Entry->Index = SubtargetFeatures.size() - 1;
589 Entry->EnumName = "Feature_" + Def->getName();
590 assert(Entry->Index < 32 && "Too many subtarget features!");
596 /// BuildRegisterClasses - Build the ClassInfo* instances for register
598 void BuildRegisterClasses(CodeGenTarget &Target,
599 std::set<std::string> &SingletonRegisterNames);
601 /// BuildOperandClasses - Build the ClassInfo* instances for user defined
603 void BuildOperandClasses(CodeGenTarget &Target);
606 AsmMatcherInfo(Record *_AsmParser);
608 /// BuildInfo - Construct the various tables used during matching.
609 void BuildInfo(CodeGenTarget &Target);
614 void InstructionInfo::dump() {
615 errs() << InstrName << " -- " << "flattened:\"" << AsmString << '\"'
617 for (unsigned i = 0, e = Tokens.size(); i != e; ++i) {
624 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
625 Operand &Op = Operands[i];
626 errs() << " op[" << i << "] = " << Op.Class->ClassName << " - ";
627 if (Op.Class->Kind == ClassInfo::Token) {
628 errs() << '\"' << Tokens[i] << "\"\n";
632 if (!Op.OperandInfo) {
633 errs() << "(singleton register)\n";
637 const CodeGenInstruction::OperandInfo &OI = *Op.OperandInfo;
638 errs() << OI.Name << " " << OI.Rec->getName()
639 << " (" << OI.MIOperandNo << ", " << OI.MINumOperands << ")\n";
643 static std::string getEnumNameForToken(StringRef Str) {
646 for (StringRef::iterator it = Str.begin(), ie = Str.end(); it != ie; ++it) {
648 case '*': Res += "_STAR_"; break;
649 case '%': Res += "_PCT_"; break;
650 case ':': Res += "_COLON_"; break;
656 Res += "_" + utostr((unsigned) *it) + "_";
664 /// getRegisterRecord - Get the register record for \arg name, or 0.
665 static Record *getRegisterRecord(CodeGenTarget &Target, StringRef Name) {
666 for (unsigned i = 0, e = Target.getRegisters().size(); i != e; ++i) {
667 const CodeGenRegister &Reg = Target.getRegisters()[i];
668 if (Name == Reg.TheDef->getValueAsString("AsmName"))
675 ClassInfo *AsmMatcherInfo::getTokenClass(StringRef Token) {
676 ClassInfo *&Entry = TokenClasses[Token];
679 Entry = new ClassInfo();
680 Entry->Kind = ClassInfo::Token;
681 Entry->ClassName = "Token";
682 Entry->Name = "MCK_" + getEnumNameForToken(Token);
683 Entry->ValueName = Token;
684 Entry->PredicateMethod = "<invalid>";
685 Entry->RenderMethod = "<invalid>";
686 Classes.push_back(Entry);
693 AsmMatcherInfo::getOperandClass(StringRef Token,
694 const CodeGenInstruction::OperandInfo &OI) {
695 if (OI.Rec->isSubClassOf("RegisterClass")) {
696 ClassInfo *CI = RegisterClassClasses[OI.Rec];
699 PrintError(OI.Rec->getLoc(), "register class has no class info!");
700 throw std::string("ERROR: Missing register class!");
706 assert(OI.Rec->isSubClassOf("Operand") && "Unexpected operand!");
707 Record *MatchClass = OI.Rec->getValueAsDef("ParserMatchClass");
708 ClassInfo *CI = AsmOperandClasses[MatchClass];
711 PrintError(OI.Rec->getLoc(), "operand has no match class!");
712 throw std::string("ERROR: Missing match class!");
718 void AsmMatcherInfo::BuildRegisterClasses(CodeGenTarget &Target,
719 std::set<std::string>
720 &SingletonRegisterNames) {
721 std::vector<CodeGenRegisterClass> RegisterClasses;
722 std::vector<CodeGenRegister> Registers;
724 RegisterClasses = Target.getRegisterClasses();
725 Registers = Target.getRegisters();
727 // The register sets used for matching.
728 std::set< std::set<Record*> > RegisterSets;
730 // Gather the defined sets.
731 for (std::vector<CodeGenRegisterClass>::iterator it = RegisterClasses.begin(),
732 ie = RegisterClasses.end(); it != ie; ++it)
733 RegisterSets.insert(std::set<Record*>(it->Elements.begin(),
734 it->Elements.end()));
736 // Add any required singleton sets.
737 for (std::set<std::string>::iterator it = SingletonRegisterNames.begin(),
738 ie = SingletonRegisterNames.end(); it != ie; ++it)
739 if (Record *Rec = getRegisterRecord(Target, *it))
740 RegisterSets.insert(std::set<Record*>(&Rec, &Rec + 1));
742 // Introduce derived sets where necessary (when a register does not determine
743 // a unique register set class), and build the mapping of registers to the set
744 // they should classify to.
745 std::map<Record*, std::set<Record*> > RegisterMap;
746 for (std::vector<CodeGenRegister>::iterator it = Registers.begin(),
747 ie = Registers.end(); it != ie; ++it) {
748 CodeGenRegister &CGR = *it;
749 // Compute the intersection of all sets containing this register.
750 std::set<Record*> ContainingSet;
752 for (std::set< std::set<Record*> >::iterator it = RegisterSets.begin(),
753 ie = RegisterSets.end(); it != ie; ++it) {
754 if (!it->count(CGR.TheDef))
757 if (ContainingSet.empty()) {
760 std::set<Record*> Tmp;
761 std::swap(Tmp, ContainingSet);
762 std::insert_iterator< std::set<Record*> > II(ContainingSet,
763 ContainingSet.begin());
764 std::set_intersection(Tmp.begin(), Tmp.end(), it->begin(), it->end(),
769 if (!ContainingSet.empty()) {
770 RegisterSets.insert(ContainingSet);
771 RegisterMap.insert(std::make_pair(CGR.TheDef, ContainingSet));
775 // Construct the register classes.
776 std::map<std::set<Record*>, ClassInfo*> RegisterSetClasses;
778 for (std::set< std::set<Record*> >::iterator it = RegisterSets.begin(),
779 ie = RegisterSets.end(); it != ie; ++it, ++Index) {
780 ClassInfo *CI = new ClassInfo();
781 CI->Kind = ClassInfo::RegisterClass0 + Index;
782 CI->ClassName = "Reg" + utostr(Index);
783 CI->Name = "MCK_Reg" + utostr(Index);
785 CI->PredicateMethod = ""; // unused
786 CI->RenderMethod = "addRegOperands";
788 Classes.push_back(CI);
789 RegisterSetClasses.insert(std::make_pair(*it, CI));
792 // Find the superclasses; we could compute only the subgroup lattice edges,
793 // but there isn't really a point.
794 for (std::set< std::set<Record*> >::iterator it = RegisterSets.begin(),
795 ie = RegisterSets.end(); it != ie; ++it) {
796 ClassInfo *CI = RegisterSetClasses[*it];
797 for (std::set< std::set<Record*> >::iterator it2 = RegisterSets.begin(),
798 ie2 = RegisterSets.end(); it2 != ie2; ++it2)
800 std::includes(it2->begin(), it2->end(), it->begin(), it->end()))
801 CI->SuperClasses.push_back(RegisterSetClasses[*it2]);
804 // Name the register classes which correspond to a user defined RegisterClass.
805 for (std::vector<CodeGenRegisterClass>::iterator it = RegisterClasses.begin(),
806 ie = RegisterClasses.end(); it != ie; ++it) {
807 ClassInfo *CI = RegisterSetClasses[std::set<Record*>(it->Elements.begin(),
808 it->Elements.end())];
809 if (CI->ValueName.empty()) {
810 CI->ClassName = it->getName();
811 CI->Name = "MCK_" + it->getName();
812 CI->ValueName = it->getName();
814 CI->ValueName = CI->ValueName + "," + it->getName();
816 RegisterClassClasses.insert(std::make_pair(it->TheDef, CI));
819 // Populate the map for individual registers.
820 for (std::map<Record*, std::set<Record*> >::iterator it = RegisterMap.begin(),
821 ie = RegisterMap.end(); it != ie; ++it)
822 this->RegisterClasses[it->first] = RegisterSetClasses[it->second];
824 // Name the register classes which correspond to singleton registers.
825 for (std::set<std::string>::iterator it = SingletonRegisterNames.begin(),
826 ie = SingletonRegisterNames.end(); it != ie; ++it) {
827 if (Record *Rec = getRegisterRecord(Target, *it)) {
828 ClassInfo *CI = this->RegisterClasses[Rec];
829 assert(CI && "Missing singleton register class info!");
831 if (CI->ValueName.empty()) {
832 CI->ClassName = Rec->getName();
833 CI->Name = "MCK_" + Rec->getName();
834 CI->ValueName = Rec->getName();
836 CI->ValueName = CI->ValueName + "," + Rec->getName();
841 void AsmMatcherInfo::BuildOperandClasses(CodeGenTarget &Target) {
842 std::vector<Record*> AsmOperands;
843 AsmOperands = Records.getAllDerivedDefinitions("AsmOperandClass");
845 // Pre-populate AsmOperandClasses map.
846 for (std::vector<Record*>::iterator it = AsmOperands.begin(),
847 ie = AsmOperands.end(); it != ie; ++it)
848 AsmOperandClasses[*it] = new ClassInfo();
851 for (std::vector<Record*>::iterator it = AsmOperands.begin(),
852 ie = AsmOperands.end(); it != ie; ++it, ++Index) {
853 ClassInfo *CI = AsmOperandClasses[*it];
854 CI->Kind = ClassInfo::UserClass0 + Index;
856 ListInit *Supers = (*it)->getValueAsListInit("SuperClasses");
857 for (unsigned i = 0, e = Supers->getSize(); i != e; ++i) {
858 DefInit *DI = dynamic_cast<DefInit*>(Supers->getElement(i));
860 PrintError((*it)->getLoc(), "Invalid super class reference!");
864 ClassInfo *SC = AsmOperandClasses[DI->getDef()];
866 PrintError((*it)->getLoc(), "Invalid super class reference!");
868 CI->SuperClasses.push_back(SC);
870 CI->ClassName = (*it)->getValueAsString("Name");
871 CI->Name = "MCK_" + CI->ClassName;
872 CI->ValueName = (*it)->getName();
874 // Get or construct the predicate method name.
875 Init *PMName = (*it)->getValueInit("PredicateMethod");
876 if (StringInit *SI = dynamic_cast<StringInit*>(PMName)) {
877 CI->PredicateMethod = SI->getValue();
879 assert(dynamic_cast<UnsetInit*>(PMName) &&
880 "Unexpected PredicateMethod field!");
881 CI->PredicateMethod = "is" + CI->ClassName;
884 // Get or construct the render method name.
885 Init *RMName = (*it)->getValueInit("RenderMethod");
886 if (StringInit *SI = dynamic_cast<StringInit*>(RMName)) {
887 CI->RenderMethod = SI->getValue();
889 assert(dynamic_cast<UnsetInit*>(RMName) &&
890 "Unexpected RenderMethod field!");
891 CI->RenderMethod = "add" + CI->ClassName + "Operands";
894 AsmOperandClasses[*it] = CI;
895 Classes.push_back(CI);
899 AsmMatcherInfo::AsmMatcherInfo(Record *_AsmParser)
900 : AsmParser(_AsmParser),
901 CommentDelimiter(AsmParser->getValueAsString("CommentDelimiter")),
902 RegisterPrefix(AsmParser->getValueAsString("RegisterPrefix"))
906 void AsmMatcherInfo::BuildInfo(CodeGenTarget &Target) {
907 // Parse the instructions; we need to do this first so that we can gather the
908 // singleton register classes.
909 std::set<std::string> SingletonRegisterNames;
911 const std::vector<const CodeGenInstruction*> &InstrList =
912 Target.getInstructionsByEnumValue();
914 for (unsigned i = 0, e = InstrList.size(); i != e; ++i) {
915 const CodeGenInstruction &CGI = *InstrList[i];
917 if (!StringRef(CGI.TheDef->getName()).startswith(MatchPrefix))
920 OwningPtr<InstructionInfo> II(new InstructionInfo());
922 II->InstrName = CGI.TheDef->getName();
924 II->AsmString = FlattenVariants(CGI.AsmString, 0);
926 // Remove comments from the asm string.
927 if (!CommentDelimiter.empty()) {
928 size_t Idx = StringRef(II->AsmString).find(CommentDelimiter);
929 if (Idx != StringRef::npos)
930 II->AsmString = II->AsmString.substr(0, Idx);
933 TokenizeAsmString(II->AsmString, II->Tokens);
935 // Ignore instructions which shouldn't be matched.
936 if (!IsAssemblerInstruction(CGI.TheDef->getName(), CGI, II->Tokens))
939 // Collect singleton registers, if used.
940 if (!RegisterPrefix.empty()) {
941 for (unsigned i = 0, e = II->Tokens.size(); i != e; ++i) {
942 if (II->Tokens[i].startswith(RegisterPrefix)) {
943 StringRef RegName = II->Tokens[i].substr(RegisterPrefix.size());
944 Record *Rec = getRegisterRecord(Target, RegName);
947 std::string Err = "unable to find register for '" + RegName.str() +
948 "' (which matches register prefix)";
949 throw TGError(CGI.TheDef->getLoc(), Err);
952 SingletonRegisterNames.insert(RegName);
957 // Compute the require features.
958 ListInit *Predicates = CGI.TheDef->getValueAsListInit("Predicates");
959 for (unsigned i = 0, e = Predicates->getSize(); i != e; ++i) {
960 if (DefInit *Pred = dynamic_cast<DefInit*>(Predicates->getElement(i))) {
961 // Ignore OptForSize and OptForSpeed, they aren't really requirements,
962 // rather they are hints to isel.
964 // FIXME: Find better way to model this.
965 if (Pred->getDef()->getName() == "OptForSize" ||
966 Pred->getDef()->getName() == "OptForSpeed")
969 // FIXME: Total hack; for now, we just limit ourselves to In32BitMode
970 // and In64BitMode, because we aren't going to have the right feature
971 // masks for SSE and friends. We need to decide what we are going to do
972 // about CPU subtypes to implement this the right way.
973 if (Pred->getDef()->getName() != "In32BitMode" &&
974 Pred->getDef()->getName() != "In64BitMode")
977 II->RequiredFeatures.push_back(getSubtargetFeature(Pred->getDef()));
981 Instructions.push_back(II.take());
984 // Build info for the register classes.
985 BuildRegisterClasses(Target, SingletonRegisterNames);
987 // Build info for the user defined assembly operand classes.
988 BuildOperandClasses(Target);
990 // Build the instruction information.
991 for (std::vector<InstructionInfo*>::iterator it = Instructions.begin(),
992 ie = Instructions.end(); it != ie; ++it) {
993 InstructionInfo *II = *it;
995 for (unsigned i = 0, e = II->Tokens.size(); i != e; ++i) {
996 StringRef Token = II->Tokens[i];
998 // Check for singleton registers.
999 if (!RegisterPrefix.empty() && Token.startswith(RegisterPrefix)) {
1000 StringRef RegName = II->Tokens[i].substr(RegisterPrefix.size());
1001 InstructionInfo::Operand Op;
1002 Op.Class = RegisterClasses[getRegisterRecord(Target, RegName)];
1004 assert(Op.Class && Op.Class->Registers.size() == 1 &&
1005 "Unexpected class for singleton register");
1006 II->Operands.push_back(Op);
1010 // Check for simple tokens.
1011 if (Token[0] != '$') {
1012 InstructionInfo::Operand Op;
1013 Op.Class = getTokenClass(Token);
1015 II->Operands.push_back(Op);
1019 // Otherwise this is an operand reference.
1020 StringRef OperandName;
1021 if (Token[1] == '{')
1022 OperandName = Token.substr(2, Token.size() - 3);
1024 OperandName = Token.substr(1);
1026 // Map this token to an operand. FIXME: Move elsewhere.
1029 Idx = II->Instr->getOperandNamed(OperandName);
1031 throw std::string("error: unable to find operand: '" +
1032 OperandName.str() + "'");
1035 // FIXME: This is annoying, the named operand may be tied (e.g.,
1036 // XCHG8rm). What we want is the untied operand, which we now have to
1037 // grovel for. Only worry about this for single entry operands, we have to
1038 // clean this up anyway.
1039 const CodeGenInstruction::OperandInfo *OI = &II->Instr->OperandList[Idx];
1040 if (OI->Constraints[0].isTied()) {
1041 unsigned TiedOp = OI->Constraints[0].getTiedOperand();
1043 // The tied operand index is an MIOperand index, find the operand that
1045 for (unsigned i = 0, e = II->Instr->OperandList.size(); i != e; ++i) {
1046 if (II->Instr->OperandList[i].MIOperandNo == TiedOp) {
1047 OI = &II->Instr->OperandList[i];
1052 assert(OI && "Unable to find tied operand target!");
1055 InstructionInfo::Operand Op;
1056 Op.Class = getOperandClass(Token, *OI);
1057 Op.OperandInfo = OI;
1058 II->Operands.push_back(Op);
1062 // Reorder classes so that classes preceed super classes.
1063 std::sort(Classes.begin(), Classes.end(), less_ptr<ClassInfo>());
1066 static std::pair<unsigned, unsigned> *
1067 GetTiedOperandAtIndex(SmallVectorImpl<std::pair<unsigned, unsigned> > &List,
1069 for (unsigned i = 0, e = List.size(); i != e; ++i)
1070 if (Index == List[i].first)
1076 static void EmitConvertToMCInst(CodeGenTarget &Target,
1077 std::vector<InstructionInfo*> &Infos,
1079 // Write the convert function to a separate stream, so we can drop it after
1081 std::string ConvertFnBody;
1082 raw_string_ostream CvtOS(ConvertFnBody);
1084 // Function we have already generated.
1085 std::set<std::string> GeneratedFns;
1087 // Start the unified conversion function.
1089 CvtOS << "static void ConvertToMCInst(ConversionKind Kind, MCInst &Inst, "
1090 << "unsigned Opcode,\n"
1091 << " const SmallVectorImpl<MCParsedAsmOperand*"
1092 << "> &Operands) {\n";
1093 CvtOS << " Inst.setOpcode(Opcode);\n";
1094 CvtOS << " switch (Kind) {\n";
1095 CvtOS << " default:\n";
1097 // Start the enum, which we will generate inline.
1099 OS << "// Unified function for converting operants to MCInst instances.\n\n";
1100 OS << "enum ConversionKind {\n";
1102 // TargetOperandClass - This is the target's operand class, like X86Operand.
1103 std::string TargetOperandClass = Target.getName() + "Operand";
1105 for (std::vector<InstructionInfo*>::const_iterator it = Infos.begin(),
1106 ie = Infos.end(); it != ie; ++it) {
1107 InstructionInfo &II = **it;
1109 // Order the (class) operands by the order to convert them into an MCInst.
1110 SmallVector<std::pair<unsigned, unsigned>, 4> MIOperandList;
1111 for (unsigned i = 0, e = II.Operands.size(); i != e; ++i) {
1112 InstructionInfo::Operand &Op = II.Operands[i];
1114 MIOperandList.push_back(std::make_pair(Op.OperandInfo->MIOperandNo, i));
1117 // Find any tied operands.
1118 SmallVector<std::pair<unsigned, unsigned>, 4> TiedOperands;
1119 for (unsigned i = 0, e = II.Instr->OperandList.size(); i != e; ++i) {
1120 const CodeGenInstruction::OperandInfo &OpInfo = II.Instr->OperandList[i];
1121 for (unsigned j = 0, e = OpInfo.Constraints.size(); j != e; ++j) {
1122 const CodeGenInstruction::ConstraintInfo &CI = OpInfo.Constraints[j];
1124 TiedOperands.push_back(std::make_pair(OpInfo.MIOperandNo + j,
1125 CI.getTiedOperand()));
1129 std::sort(MIOperandList.begin(), MIOperandList.end());
1131 // Compute the total number of operands.
1132 unsigned NumMIOperands = 0;
1133 for (unsigned i = 0, e = II.Instr->OperandList.size(); i != e; ++i) {
1134 const CodeGenInstruction::OperandInfo &OI = II.Instr->OperandList[i];
1135 NumMIOperands = std::max(NumMIOperands,
1136 OI.MIOperandNo + OI.MINumOperands);
1139 // Build the conversion function signature.
1140 std::string Signature = "Convert";
1141 unsigned CurIndex = 0;
1142 for (unsigned i = 0, e = MIOperandList.size(); i != e; ++i) {
1143 InstructionInfo::Operand &Op = II.Operands[MIOperandList[i].second];
1144 assert(CurIndex <= Op.OperandInfo->MIOperandNo &&
1145 "Duplicate match for instruction operand!");
1147 // Skip operands which weren't matched by anything, this occurs when the
1148 // .td file encodes "implicit" operands as explicit ones.
1150 // FIXME: This should be removed from the MCInst structure.
1151 for (; CurIndex != Op.OperandInfo->MIOperandNo; ++CurIndex) {
1152 std::pair<unsigned, unsigned> *Tie = GetTiedOperandAtIndex(TiedOperands,
1155 Signature += "__Imp";
1157 Signature += "__Tie" + utostr(Tie->second);
1162 // Registers are always converted the same, don't duplicate the conversion
1163 // function based on them.
1165 // FIXME: We could generalize this based on the render method, if it
1167 if (Op.Class->isRegisterClass())
1170 Signature += Op.Class->ClassName;
1171 Signature += utostr(Op.OperandInfo->MINumOperands);
1172 Signature += "_" + utostr(MIOperandList[i].second);
1174 CurIndex += Op.OperandInfo->MINumOperands;
1177 // Add any trailing implicit operands.
1178 for (; CurIndex != NumMIOperands; ++CurIndex) {
1179 std::pair<unsigned, unsigned> *Tie = GetTiedOperandAtIndex(TiedOperands,
1182 Signature += "__Imp";
1184 Signature += "__Tie" + utostr(Tie->second);
1187 II.ConversionFnKind = Signature;
1189 // Check if we have already generated this signature.
1190 if (!GeneratedFns.insert(Signature).second)
1193 // If not, emit it now.
1195 // Add to the enum list.
1196 OS << " " << Signature << ",\n";
1198 // And to the convert function.
1199 CvtOS << " case " << Signature << ":\n";
1201 for (unsigned i = 0, e = MIOperandList.size(); i != e; ++i) {
1202 InstructionInfo::Operand &Op = II.Operands[MIOperandList[i].second];
1204 // Add the implicit operands.
1205 for (; CurIndex != Op.OperandInfo->MIOperandNo; ++CurIndex) {
1206 // See if this is a tied operand.
1207 std::pair<unsigned, unsigned> *Tie = GetTiedOperandAtIndex(TiedOperands,
1211 // If not, this is some implicit operand. Just assume it is a register
1213 CvtOS << " Inst.addOperand(MCOperand::CreateReg(0));\n";
1215 // Copy the tied operand.
1216 assert(Tie->first>Tie->second && "Tied operand preceeds its target!");
1217 CvtOS << " Inst.addOperand(Inst.getOperand("
1218 << Tie->second << "));\n";
1222 CvtOS << " ((" << TargetOperandClass << "*)Operands["
1223 << MIOperandList[i].second
1224 << "])->" << Op.Class->RenderMethod
1225 << "(Inst, " << Op.OperandInfo->MINumOperands << ");\n";
1226 CurIndex += Op.OperandInfo->MINumOperands;
1229 // And add trailing implicit operands.
1230 for (; CurIndex != NumMIOperands; ++CurIndex) {
1231 std::pair<unsigned, unsigned> *Tie = GetTiedOperandAtIndex(TiedOperands,
1235 // If not, this is some implicit operand. Just assume it is a register
1237 CvtOS << " Inst.addOperand(MCOperand::CreateReg(0));\n";
1239 // Copy the tied operand.
1240 assert(Tie->first>Tie->second && "Tied operand preceeds its target!");
1241 CvtOS << " Inst.addOperand(Inst.getOperand("
1242 << Tie->second << "));\n";
1246 CvtOS << " return;\n";
1249 // Finish the convert function.
1254 // Finish the enum, and drop the convert function after it.
1256 OS << " NumConversionVariants\n";
1262 /// EmitMatchClassEnumeration - Emit the enumeration for match class kinds.
1263 static void EmitMatchClassEnumeration(CodeGenTarget &Target,
1264 std::vector<ClassInfo*> &Infos,
1266 OS << "namespace {\n\n";
1268 OS << "/// MatchClassKind - The kinds of classes which participate in\n"
1269 << "/// instruction matching.\n";
1270 OS << "enum MatchClassKind {\n";
1271 OS << " InvalidMatchClass = 0,\n";
1272 for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
1273 ie = Infos.end(); it != ie; ++it) {
1274 ClassInfo &CI = **it;
1275 OS << " " << CI.Name << ", // ";
1276 if (CI.Kind == ClassInfo::Token) {
1277 OS << "'" << CI.ValueName << "'\n";
1278 } else if (CI.isRegisterClass()) {
1279 if (!CI.ValueName.empty())
1280 OS << "register class '" << CI.ValueName << "'\n";
1282 OS << "derived register class\n";
1284 OS << "user defined class '" << CI.ValueName << "'\n";
1287 OS << " NumMatchClassKinds\n";
1293 /// EmitClassifyOperand - Emit the function to classify an operand.
1294 static void EmitClassifyOperand(CodeGenTarget &Target,
1295 AsmMatcherInfo &Info,
1297 OS << "static MatchClassKind ClassifyOperand(MCParsedAsmOperand *GOp) {\n"
1298 << " " << Target.getName() << "Operand &Operand = *("
1299 << Target.getName() << "Operand*)GOp;\n";
1302 OS << " if (Operand.isToken())\n";
1303 OS << " return MatchTokenString(Operand.getToken());\n\n";
1305 // Classify registers.
1307 // FIXME: Don't hardcode isReg, getReg.
1308 OS << " if (Operand.isReg()) {\n";
1309 OS << " switch (Operand.getReg()) {\n";
1310 OS << " default: return InvalidMatchClass;\n";
1311 for (std::map<Record*, ClassInfo*>::iterator
1312 it = Info.RegisterClasses.begin(), ie = Info.RegisterClasses.end();
1314 OS << " case " << Target.getName() << "::"
1315 << it->first->getName() << ": return " << it->second->Name << ";\n";
1319 // Classify user defined operands.
1320 for (std::vector<ClassInfo*>::iterator it = Info.Classes.begin(),
1321 ie = Info.Classes.end(); it != ie; ++it) {
1322 ClassInfo &CI = **it;
1324 if (!CI.isUserClass())
1327 OS << " // '" << CI.ClassName << "' class";
1328 if (!CI.SuperClasses.empty()) {
1329 OS << ", subclass of ";
1330 for (unsigned i = 0, e = CI.SuperClasses.size(); i != e; ++i) {
1332 OS << "'" << CI.SuperClasses[i]->ClassName << "'";
1333 assert(CI < *CI.SuperClasses[i] && "Invalid class relation!");
1338 OS << " if (Operand." << CI.PredicateMethod << "()) {\n";
1340 // Validate subclass relationships.
1341 if (!CI.SuperClasses.empty()) {
1342 for (unsigned i = 0, e = CI.SuperClasses.size(); i != e; ++i)
1343 OS << " assert(Operand." << CI.SuperClasses[i]->PredicateMethod
1344 << "() && \"Invalid class relationship!\");\n";
1347 OS << " return " << CI.Name << ";\n";
1350 OS << " return InvalidMatchClass;\n";
1354 /// EmitIsSubclass - Emit the subclass predicate function.
1355 static void EmitIsSubclass(CodeGenTarget &Target,
1356 std::vector<ClassInfo*> &Infos,
1358 OS << "/// IsSubclass - Compute whether \\arg A is a subclass of \\arg B.\n";
1359 OS << "static bool IsSubclass(MatchClassKind A, MatchClassKind B) {\n";
1360 OS << " if (A == B)\n";
1361 OS << " return true;\n\n";
1363 OS << " switch (A) {\n";
1364 OS << " default:\n";
1365 OS << " return false;\n";
1366 for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
1367 ie = Infos.end(); it != ie; ++it) {
1368 ClassInfo &A = **it;
1370 if (A.Kind != ClassInfo::Token) {
1371 std::vector<StringRef> SuperClasses;
1372 for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
1373 ie = Infos.end(); it != ie; ++it) {
1374 ClassInfo &B = **it;
1376 if (&A != &B && A.isSubsetOf(B))
1377 SuperClasses.push_back(B.Name);
1380 if (SuperClasses.empty())
1383 OS << "\n case " << A.Name << ":\n";
1385 if (SuperClasses.size() == 1) {
1386 OS << " return B == " << SuperClasses.back() << ";\n";
1390 OS << " switch (B) {\n";
1391 OS << " default: return false;\n";
1392 for (unsigned i = 0, e = SuperClasses.size(); i != e; ++i)
1393 OS << " case " << SuperClasses[i] << ": return true;\n";
1403 /// EmitMatchTokenString - Emit the function to match a token string to the
1404 /// appropriate match class value.
1405 static void EmitMatchTokenString(CodeGenTarget &Target,
1406 std::vector<ClassInfo*> &Infos,
1408 // Construct the match list.
1409 std::vector<StringMatcher::StringPair> Matches;
1410 for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
1411 ie = Infos.end(); it != ie; ++it) {
1412 ClassInfo &CI = **it;
1414 if (CI.Kind == ClassInfo::Token)
1415 Matches.push_back(StringMatcher::StringPair(CI.ValueName,
1416 "return " + CI.Name + ";"));
1419 OS << "static MatchClassKind MatchTokenString(StringRef Name) {\n";
1421 StringMatcher("Name", Matches, OS).Emit();
1423 OS << " return InvalidMatchClass;\n";
1427 /// EmitMatchRegisterName - Emit the function to match a string to the target
1428 /// specific register enum.
1429 static void EmitMatchRegisterName(CodeGenTarget &Target, Record *AsmParser,
1431 // Construct the match list.
1432 std::vector<StringMatcher::StringPair> Matches;
1433 for (unsigned i = 0, e = Target.getRegisters().size(); i != e; ++i) {
1434 const CodeGenRegister &Reg = Target.getRegisters()[i];
1435 if (Reg.TheDef->getValueAsString("AsmName").empty())
1438 Matches.push_back(StringMatcher::StringPair(
1439 Reg.TheDef->getValueAsString("AsmName"),
1440 "return " + utostr(i + 1) + ";"));
1443 OS << "static unsigned MatchRegisterName(StringRef Name) {\n";
1445 StringMatcher("Name", Matches, OS).Emit();
1447 OS << " return 0;\n";
1451 /// EmitSubtargetFeatureFlagEnumeration - Emit the subtarget feature flag
1453 static void EmitSubtargetFeatureFlagEnumeration(CodeGenTarget &Target,
1454 AsmMatcherInfo &Info,
1456 OS << "// Flags for subtarget features that participate in "
1457 << "instruction matching.\n";
1458 OS << "enum SubtargetFeatureFlag {\n";
1459 for (std::map<Record*, SubtargetFeatureInfo*>::const_iterator
1460 it = Info.SubtargetFeatures.begin(),
1461 ie = Info.SubtargetFeatures.end(); it != ie; ++it) {
1462 SubtargetFeatureInfo &SFI = *it->second;
1463 OS << " " << SFI.EnumName << " = (1 << " << SFI.Index << "),\n";
1465 OS << " Feature_None = 0\n";
1469 /// EmitComputeAvailableFeatures - Emit the function to compute the list of
1470 /// available features given a subtarget.
1471 static void EmitComputeAvailableFeatures(CodeGenTarget &Target,
1472 AsmMatcherInfo &Info,
1474 std::string ClassName =
1475 Info.AsmParser->getValueAsString("AsmParserClassName");
1477 OS << "unsigned " << Target.getName() << ClassName << "::\n"
1478 << "ComputeAvailableFeatures(const " << Target.getName()
1479 << "Subtarget *Subtarget) const {\n";
1480 OS << " unsigned Features = 0;\n";
1481 for (std::map<Record*, SubtargetFeatureInfo*>::const_iterator
1482 it = Info.SubtargetFeatures.begin(),
1483 ie = Info.SubtargetFeatures.end(); it != ie; ++it) {
1484 SubtargetFeatureInfo &SFI = *it->second;
1485 OS << " if (" << SFI.TheDef->getValueAsString("CondString")
1487 OS << " Features |= " << SFI.EnumName << ";\n";
1489 OS << " return Features;\n";
1493 void AsmMatcherEmitter::run(raw_ostream &OS) {
1494 CodeGenTarget Target;
1495 Record *AsmParser = Target.getAsmParser();
1496 std::string ClassName = AsmParser->getValueAsString("AsmParserClassName");
1498 // Compute the information on the instructions to match.
1499 AsmMatcherInfo Info(AsmParser);
1500 Info.BuildInfo(Target);
1502 // Sort the instruction table using the partial order on classes. We use
1503 // stable_sort to ensure that ambiguous instructions are still
1504 // deterministically ordered.
1505 std::stable_sort(Info.Instructions.begin(), Info.Instructions.end(),
1506 less_ptr<InstructionInfo>());
1508 DEBUG_WITH_TYPE("instruction_info", {
1509 for (std::vector<InstructionInfo*>::iterator
1510 it = Info.Instructions.begin(), ie = Info.Instructions.end();
1515 // Check for ambiguous instructions.
1516 unsigned NumAmbiguous = 0;
1517 for (unsigned i = 0, e = Info.Instructions.size(); i != e; ++i) {
1518 for (unsigned j = i + 1; j != e; ++j) {
1519 InstructionInfo &A = *Info.Instructions[i];
1520 InstructionInfo &B = *Info.Instructions[j];
1522 if (A.CouldMatchAmiguouslyWith(B)) {
1523 DEBUG_WITH_TYPE("ambiguous_instrs", {
1524 errs() << "warning: ambiguous instruction match:\n";
1526 errs() << "\nis incomparable with:\n";
1535 DEBUG_WITH_TYPE("ambiguous_instrs", {
1536 errs() << "warning: " << NumAmbiguous
1537 << " ambiguous instructions!\n";
1540 // Write the output.
1542 EmitSourceFileHeader("Assembly Matcher Source Fragment", OS);
1544 // Information for the class declaration.
1545 OS << "\n#ifdef GET_ASSEMBLER_HEADER\n";
1546 OS << "#undef GET_ASSEMBLER_HEADER\n";
1547 OS << " unsigned ComputeAvailableFeatures(const " <<
1548 Target.getName() << "Subtarget *Subtarget) const;\n";
1549 OS << "bool MatchInstructionImpl(const SmallVectorImpl<MCParsedAsmOperand*>"
1550 << " &Operands, MCInst &Inst);\n\n";
1551 OS << "#endif // GET_ASSEMBLER_HEADER_INFO\n\n";
1556 OS << "\n#ifdef GET_REGISTER_MATCHER\n";
1557 OS << "#undef GET_REGISTER_MATCHER\n\n";
1559 // Emit the subtarget feature enumeration.
1560 EmitSubtargetFeatureFlagEnumeration(Target, Info, OS);
1562 // Emit the function to match a register name to number.
1563 EmitMatchRegisterName(Target, AsmParser, OS);
1565 OS << "#endif // GET_REGISTER_MATCHER\n\n";
1568 OS << "\n#ifdef GET_MATCHER_IMPLEMENTATION\n";
1569 OS << "#undef GET_MATCHER_IMPLEMENTATION\n\n";
1571 // Generate the unified function to convert operands into an MCInst.
1572 EmitConvertToMCInst(Target, Info.Instructions, OS);
1574 // Emit the enumeration for classes which participate in matching.
1575 EmitMatchClassEnumeration(Target, Info.Classes, OS);
1577 // Emit the routine to match token strings to their match class.
1578 EmitMatchTokenString(Target, Info.Classes, OS);
1580 // Emit the routine to classify an operand.
1581 EmitClassifyOperand(Target, Info, OS);
1583 // Emit the subclass predicate routine.
1584 EmitIsSubclass(Target, Info.Classes, OS);
1586 // Emit the available features compute function.
1587 EmitComputeAvailableFeatures(Target, Info, OS);
1589 // Finally, build the match function.
1591 size_t MaxNumOperands = 0;
1592 for (std::vector<InstructionInfo*>::const_iterator it =
1593 Info.Instructions.begin(), ie = Info.Instructions.end();
1595 MaxNumOperands = std::max(MaxNumOperands, (*it)->Operands.size());
1597 OS << "bool " << Target.getName() << ClassName << "::\n"
1598 << "MatchInstructionImpl(const SmallVectorImpl<MCParsedAsmOperand*>"
1600 OS << " MCInst &Inst) {\n";
1602 // Emit the static match table; unused classes get initalized to 0 which is
1603 // guaranteed to be InvalidMatchClass.
1605 // FIXME: We can reduce the size of this table very easily. First, we change
1606 // it so that store the kinds in separate bit-fields for each index, which
1607 // only needs to be the max width used for classes at that index (we also need
1608 // to reject based on this during classification). If we then make sure to
1609 // order the match kinds appropriately (putting mnemonics last), then we
1610 // should only end up using a few bits for each class, especially the ones
1611 // following the mnemonic.
1612 OS << " static const struct MatchEntry {\n";
1613 OS << " unsigned Opcode;\n";
1614 OS << " ConversionKind ConvertFn;\n";
1615 OS << " MatchClassKind Classes[" << MaxNumOperands << "];\n";
1616 OS << " unsigned RequiredFeatures;\n";
1617 OS << " } MatchTable[" << Info.Instructions.size() << "] = {\n";
1619 for (std::vector<InstructionInfo*>::const_iterator it =
1620 Info.Instructions.begin(), ie = Info.Instructions.end();
1622 InstructionInfo &II = **it;
1624 OS << " { " << Target.getName() << "::" << II.InstrName
1625 << ", " << II.ConversionFnKind << ", { ";
1626 for (unsigned i = 0, e = II.Operands.size(); i != e; ++i) {
1627 InstructionInfo::Operand &Op = II.Operands[i];
1630 OS << Op.Class->Name;
1634 // Write the required features mask.
1635 if (!II.RequiredFeatures.empty()) {
1636 for (unsigned i = 0, e = II.RequiredFeatures.size(); i != e; ++i) {
1638 OS << II.RequiredFeatures[i]->EnumName;
1649 // Emit code to get the available features.
1650 OS << " // Get the current feature set.\n";
1651 OS << " unsigned AvailableFeatures = getAvailableFeatures();\n\n";
1653 // Emit code to compute the class list for this operand vector.
1654 OS << " // Eliminate obvious mismatches.\n";
1655 OS << " if (Operands.size() > " << MaxNumOperands << ")\n";
1656 OS << " return true;\n\n";
1658 OS << " // Compute the class list for this operand vector.\n";
1659 OS << " MatchClassKind Classes[" << MaxNumOperands << "];\n";
1660 OS << " for (unsigned i = 0, e = Operands.size(); i != e; ++i) {\n";
1661 OS << " Classes[i] = ClassifyOperand(Operands[i]);\n\n";
1663 OS << " // Check for invalid operands before matching.\n";
1664 OS << " if (Classes[i] == InvalidMatchClass)\n";
1665 OS << " return true;\n";
1668 OS << " // Mark unused classes.\n";
1669 OS << " for (unsigned i = Operands.size(), e = " << MaxNumOperands << "; "
1670 << "i != e; ++i)\n";
1671 OS << " Classes[i] = InvalidMatchClass;\n\n";
1673 // Emit code to search the table.
1674 OS << " // Search the table.\n";
1675 OS << " for (const MatchEntry *it = MatchTable, "
1676 << "*ie = MatchTable + " << Info.Instructions.size()
1677 << "; it != ie; ++it) {\n";
1679 // Emit check that the required features are available.
1680 OS << " if ((AvailableFeatures & it->RequiredFeatures) "
1681 << "!= it->RequiredFeatures)\n";
1682 OS << " continue;\n";
1684 // Emit check that the subclasses match.
1685 for (unsigned i = 0; i != MaxNumOperands; ++i) {
1686 OS << " if (!IsSubclass(Classes["
1687 << i << "], it->Classes[" << i << "]))\n";
1688 OS << " continue;\n";
1692 OS << " ConvertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands);\n";
1694 // Call the post-processing function, if used.
1695 std::string InsnCleanupFn =
1696 AsmParser->getValueAsString("AsmParserInstCleanup");
1697 if (!InsnCleanupFn.empty())
1698 OS << " " << InsnCleanupFn << "(Inst);\n";
1700 OS << " return false;\n";
1703 OS << " return true;\n";
1706 OS << "#endif // GET_MATCHER_IMPLEMENTATION\n\n";