1 //===- AsmMatcherEmitter.cpp - Generate an assembly matcher ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend emits a target specifier matcher for converting parsed
11 // assembly operands in the MCInst structures. It also emits a matcher for
12 // custom operand parsing.
14 // Converting assembly operands into MCInst structures
15 // ---------------------------------------------------
17 // The input to the target specific matcher is a list of literal tokens and
18 // operands. The target specific parser should generally eliminate any syntax
19 // which is not relevant for matching; for example, comma tokens should have
20 // already been consumed and eliminated by the parser. Most instructions will
21 // end up with a single literal token (the instruction name) and some number of
24 // Some example inputs, for X86:
25 // 'addl' (immediate ...) (register ...)
26 // 'add' (immediate ...) (memory ...)
29 // The assembly matcher is responsible for converting this input into a precise
30 // machine instruction (i.e., an instruction with a well defined encoding). This
31 // mapping has several properties which complicate matching:
33 // - It may be ambiguous; many architectures can legally encode particular
34 // variants of an instruction in different ways (for example, using a smaller
35 // encoding for small immediates). Such ambiguities should never be
36 // arbitrarily resolved by the assembler, the assembler is always responsible
37 // for choosing the "best" available instruction.
39 // - It may depend on the subtarget or the assembler context. Instructions
40 // which are invalid for the current mode, but otherwise unambiguous (e.g.,
41 // an SSE instruction in a file being assembled for i486) should be accepted
42 // and rejected by the assembler front end. However, if the proper encoding
43 // for an instruction is dependent on the assembler context then the matcher
44 // is responsible for selecting the correct machine instruction for the
47 // The core matching algorithm attempts to exploit the regularity in most
48 // instruction sets to quickly determine the set of possibly matching
49 // instructions, and the simplify the generated code. Additionally, this helps
50 // to ensure that the ambiguities are intentionally resolved by the user.
52 // The matching is divided into two distinct phases:
54 // 1. Classification: Each operand is mapped to the unique set which (a)
55 // contains it, and (b) is the largest such subset for which a single
56 // instruction could match all members.
58 // For register classes, we can generate these subgroups automatically. For
59 // arbitrary operands, we expect the user to define the classes and their
60 // relations to one another (for example, 8-bit signed immediates as a
61 // subset of 32-bit immediates).
63 // By partitioning the operands in this way, we guarantee that for any
64 // tuple of classes, any single instruction must match either all or none
65 // of the sets of operands which could classify to that tuple.
67 // In addition, the subset relation amongst classes induces a partial order
68 // on such tuples, which we use to resolve ambiguities.
70 // 2. The input can now be treated as a tuple of classes (static tokens are
71 // simple singleton sets). Each such tuple should generally map to a single
72 // instruction (we currently ignore cases where this isn't true, whee!!!),
73 // which we can emit a simple matcher for.
75 // Custom Operand Parsing
76 // ----------------------
78 // Some targets need a custom way to parse operands, some specific instructions
79 // can contain arguments that can represent processor flags and other kinds of
80 // identifiers that need to be mapped to specific values in the final encoded
81 // instructions. The target specific custom operand parsing works in the
84 // 1. A operand match table is built, each entry contains a mnemonic, an
85 // operand class, a mask for all operand positions for that same
86 // class/mnemonic and target features to be checked while trying to match.
88 // 2. The operand matcher will try every possible entry with the same
89 // mnemonic and will check if the target feature for this mnemonic also
90 // matches. After that, if the operand to be matched has its index
91 // present in the mask, a successful match occurs. Otherwise, fallback
92 // to the regular operand parsing.
94 // 3. For a match success, each operand class that has a 'ParserMethod'
95 // becomes part of a switch from where the custom method is called.
97 //===----------------------------------------------------------------------===//
99 #include "CodeGenTarget.h"
100 #include "llvm/ADT/PointerUnion.h"
101 #include "llvm/ADT/STLExtras.h"
102 #include "llvm/ADT/SmallPtrSet.h"
103 #include "llvm/ADT/SmallVector.h"
104 #include "llvm/ADT/StringExtras.h"
105 #include "llvm/Support/CommandLine.h"
106 #include "llvm/Support/Debug.h"
107 #include "llvm/Support/ErrorHandling.h"
108 #include "llvm/TableGen/Error.h"
109 #include "llvm/TableGen/Record.h"
110 #include "llvm/TableGen/StringMatcher.h"
111 #include "llvm/TableGen/StringToOffsetTable.h"
112 #include "llvm/TableGen/TableGenBackend.h"
118 #include <forward_list>
119 using namespace llvm;
121 #define DEBUG_TYPE "asm-matcher-emitter"
123 static cl::opt<std::string>
124 MatchPrefix("match-prefix", cl::init(""),
125 cl::desc("Only match instructions with the given prefix"));
128 class AsmMatcherInfo;
129 struct SubtargetFeatureInfo;
131 // Register sets are used as keys in some second-order sets TableGen creates
132 // when generating its data structures. This means that the order of two
133 // RegisterSets can be seen in the outputted AsmMatcher tables occasionally, and
134 // can even affect compiler output (at least seen in diagnostics produced when
135 // all matches fail). So we use a type that sorts them consistently.
136 typedef std::set<Record*, LessRecordByID> RegisterSet;
138 class AsmMatcherEmitter {
139 RecordKeeper &Records;
141 AsmMatcherEmitter(RecordKeeper &R) : Records(R) {}
143 void run(raw_ostream &o);
146 /// ClassInfo - Helper class for storing the information about a particular
147 /// class of operands which can be matched.
150 /// Invalid kind, for use as a sentinel value.
153 /// The class for a particular token.
156 /// The (first) register class, subsequent register classes are
157 /// RegisterClass0+1, and so on.
160 /// The (first) user defined class, subsequent user defined classes are
161 /// UserClass0+1, and so on.
165 /// Kind - The class kind, which is either a predefined kind, or (UserClass0 +
166 /// N) for the Nth user defined class.
169 /// SuperClasses - The super classes of this class. Note that for simplicities
170 /// sake user operands only record their immediate super class, while register
171 /// operands include all superclasses.
172 std::vector<ClassInfo*> SuperClasses;
174 /// Name - The full class name, suitable for use in an enum.
177 /// ClassName - The unadorned generic name for this class (e.g., Token).
178 std::string ClassName;
180 /// ValueName - The name of the value this class represents; for a token this
181 /// is the literal token string, for an operand it is the TableGen class (or
182 /// empty if this is a derived class).
183 std::string ValueName;
185 /// PredicateMethod - The name of the operand method to test whether the
186 /// operand matches this class; this is not valid for Token or register kinds.
187 std::string PredicateMethod;
189 /// RenderMethod - The name of the operand method to add this operand to an
190 /// MCInst; this is not valid for Token or register kinds.
191 std::string RenderMethod;
193 /// ParserMethod - The name of the operand method to do a target specific
194 /// parsing on the operand.
195 std::string ParserMethod;
197 /// For register classes: the records for all the registers in this class.
198 RegisterSet Registers;
200 /// For custom match classes: the diagnostic kind for when the predicate fails.
201 std::string DiagnosticType;
203 /// isRegisterClass() - Check if this is a register class.
204 bool isRegisterClass() const {
205 return Kind >= RegisterClass0 && Kind < UserClass0;
208 /// isUserClass() - Check if this is a user defined class.
209 bool isUserClass() const {
210 return Kind >= UserClass0;
213 /// isRelatedTo - Check whether this class is "related" to \p RHS. Classes
214 /// are related if they are in the same class hierarchy.
215 bool isRelatedTo(const ClassInfo &RHS) const {
216 // Tokens are only related to tokens.
217 if (Kind == Token || RHS.Kind == Token)
218 return Kind == Token && RHS.Kind == Token;
220 // Registers classes are only related to registers classes, and only if
221 // their intersection is non-empty.
222 if (isRegisterClass() || RHS.isRegisterClass()) {
223 if (!isRegisterClass() || !RHS.isRegisterClass())
227 std::insert_iterator<RegisterSet> II(Tmp, Tmp.begin());
228 std::set_intersection(Registers.begin(), Registers.end(),
229 RHS.Registers.begin(), RHS.Registers.end(),
230 II, LessRecordByID());
235 // Otherwise we have two users operands; they are related if they are in the
236 // same class hierarchy.
238 // FIXME: This is an oversimplification, they should only be related if they
239 // intersect, however we don't have that information.
240 assert(isUserClass() && RHS.isUserClass() && "Unexpected class!");
241 const ClassInfo *Root = this;
242 while (!Root->SuperClasses.empty())
243 Root = Root->SuperClasses.front();
245 const ClassInfo *RHSRoot = &RHS;
246 while (!RHSRoot->SuperClasses.empty())
247 RHSRoot = RHSRoot->SuperClasses.front();
249 return Root == RHSRoot;
252 /// isSubsetOf - Test whether this class is a subset of \p RHS.
253 bool isSubsetOf(const ClassInfo &RHS) const {
254 // This is a subset of RHS if it is the same class...
258 // ... or if any of its super classes are a subset of RHS.
259 for (const ClassInfo *CI : SuperClasses)
260 if (CI->isSubsetOf(RHS))
266 /// operator< - Compare two classes.
267 bool operator<(const ClassInfo &RHS) const {
271 // Unrelated classes can be ordered by kind.
272 if (!isRelatedTo(RHS))
273 return Kind < RHS.Kind;
277 llvm_unreachable("Invalid kind!");
280 // This class precedes the RHS if it is a proper subset of the RHS.
283 if (RHS.isSubsetOf(*this))
286 // Otherwise, order by name to ensure we have a total ordering.
287 return ValueName < RHS.ValueName;
292 /// MatchableInfo - Helper class for storing the necessary information for an
293 /// instruction or alias which is capable of being matched.
294 struct MatchableInfo {
296 /// Token - This is the token that the operand came from.
299 /// The unique class instance this operand should match.
302 /// The operand name this is, if anything.
305 /// The suboperand index within SrcOpName, or -1 for the entire operand.
308 /// Register record if this token is singleton register.
309 Record *SingletonReg;
311 explicit AsmOperand(StringRef T) : Token(T), Class(nullptr), SubOpIdx(-1),
312 SingletonReg(nullptr) {}
315 /// ResOperand - This represents a single operand in the result instruction
316 /// generated by the match. In cases (like addressing modes) where a single
317 /// assembler operand expands to multiple MCOperands, this represents the
318 /// single assembler operand, not the MCOperand.
321 /// RenderAsmOperand - This represents an operand result that is
322 /// generated by calling the render method on the assembly operand. The
323 /// corresponding AsmOperand is specified by AsmOperandNum.
326 /// TiedOperand - This represents a result operand that is a duplicate of
327 /// a previous result operand.
330 /// ImmOperand - This represents an immediate value that is dumped into
334 /// RegOperand - This represents a fixed register that is dumped in.
339 /// This is the operand # in the AsmOperands list that this should be
341 unsigned AsmOperandNum;
343 /// TiedOperandNum - This is the (earlier) result operand that should be
345 unsigned TiedOperandNum;
347 /// ImmVal - This is the immediate value added to the instruction.
350 /// Register - This is the register record.
354 /// MINumOperands - The number of MCInst operands populated by this
356 unsigned MINumOperands;
358 static ResOperand getRenderedOp(unsigned AsmOpNum, unsigned NumOperands) {
360 X.Kind = RenderAsmOperand;
361 X.AsmOperandNum = AsmOpNum;
362 X.MINumOperands = NumOperands;
366 static ResOperand getTiedOp(unsigned TiedOperandNum) {
368 X.Kind = TiedOperand;
369 X.TiedOperandNum = TiedOperandNum;
374 static ResOperand getImmOp(int64_t Val) {
382 static ResOperand getRegOp(Record *Reg) {
391 /// AsmVariantID - Target's assembly syntax variant no.
394 /// TheDef - This is the definition of the instruction or InstAlias that this
395 /// matchable came from.
396 Record *const TheDef;
398 /// DefRec - This is the definition that it came from.
399 PointerUnion<const CodeGenInstruction*, const CodeGenInstAlias*> DefRec;
401 const CodeGenInstruction *getResultInst() const {
402 if (DefRec.is<const CodeGenInstruction*>())
403 return DefRec.get<const CodeGenInstruction*>();
404 return DefRec.get<const CodeGenInstAlias*>()->ResultInst;
407 /// ResOperands - This is the operand list that should be built for the result
409 SmallVector<ResOperand, 8> ResOperands;
411 /// AsmString - The assembly string for this instruction (with variants
412 /// removed), e.g. "movsx $src, $dst".
413 std::string AsmString;
415 /// Mnemonic - This is the first token of the matched instruction, its
419 /// AsmOperands - The textual operands that this instruction matches,
420 /// annotated with a class and where in the OperandList they were defined.
421 /// This directly corresponds to the tokenized AsmString after the mnemonic is
423 SmallVector<AsmOperand, 8> AsmOperands;
425 /// Predicates - The required subtarget features to match this instruction.
426 SmallVector<SubtargetFeatureInfo*, 4> RequiredFeatures;
428 /// ConversionFnKind - The enum value which is passed to the generated
429 /// convertToMCInst to convert parsed operands into an MCInst for this
431 std::string ConversionFnKind;
433 /// If this instruction is deprecated in some form.
436 MatchableInfo(const CodeGenInstruction &CGI)
437 : AsmVariantID(0), TheDef(CGI.TheDef), DefRec(&CGI),
438 AsmString(CGI.AsmString) {
441 MatchableInfo(const CodeGenInstAlias *Alias)
442 : AsmVariantID(0), TheDef(Alias->TheDef), DefRec(Alias),
443 AsmString(Alias->AsmString) {
447 if (DefRec.is<const CodeGenInstAlias*>())
448 delete DefRec.get<const CodeGenInstAlias*>();
451 // Two-operand aliases clone from the main matchable, but mark the second
452 // operand as a tied operand of the first for purposes of the assembler.
453 void formTwoOperandAlias(StringRef Constraint);
455 void initialize(const AsmMatcherInfo &Info,
456 SmallPtrSetImpl<Record*> &SingletonRegisters,
457 int AsmVariantNo, std::string &RegisterPrefix);
459 /// validate - Return true if this matchable is a valid thing to match against
460 /// and perform a bunch of validity checking.
461 bool validate(StringRef CommentDelimiter, bool Hack) const;
463 /// extractSingletonRegisterForAsmOperand - Extract singleton register,
464 /// if present, from specified token.
466 extractSingletonRegisterForAsmOperand(unsigned i, const AsmMatcherInfo &Info,
467 std::string &RegisterPrefix);
469 /// findAsmOperand - Find the AsmOperand with the specified name and
470 /// suboperand index.
471 int findAsmOperand(StringRef N, int SubOpIdx) const {
472 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i)
473 if (N == AsmOperands[i].SrcOpName &&
474 SubOpIdx == AsmOperands[i].SubOpIdx)
479 /// findAsmOperandNamed - Find the first AsmOperand with the specified name.
480 /// This does not check the suboperand index.
481 int findAsmOperandNamed(StringRef N) const {
482 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i)
483 if (N == AsmOperands[i].SrcOpName)
488 void buildInstructionResultOperands();
489 void buildAliasResultOperands();
491 /// operator< - Compare two matchables.
492 bool operator<(const MatchableInfo &RHS) const {
493 // The primary comparator is the instruction mnemonic.
494 if (Mnemonic != RHS.Mnemonic)
495 return Mnemonic < RHS.Mnemonic;
497 if (AsmOperands.size() != RHS.AsmOperands.size())
498 return AsmOperands.size() < RHS.AsmOperands.size();
500 // Compare lexicographically by operand. The matcher validates that other
501 // orderings wouldn't be ambiguous using \see couldMatchAmbiguouslyWith().
502 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
503 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class)
505 if (*RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
509 // Give matches that require more features higher precedence. This is useful
510 // because we cannot define AssemblerPredicates with the negation of
511 // processor features. For example, ARM v6 "nop" may be either a HINT or
512 // MOV. With v6, we want to match HINT. The assembler has no way to
513 // predicate MOV under "NoV6", but HINT will always match first because it
514 // requires V6 while MOV does not.
515 if (RequiredFeatures.size() != RHS.RequiredFeatures.size())
516 return RequiredFeatures.size() > RHS.RequiredFeatures.size();
521 /// couldMatchAmbiguouslyWith - Check whether this matchable could
522 /// ambiguously match the same set of operands as \p RHS (without being a
523 /// strictly superior match).
524 bool couldMatchAmbiguouslyWith(const MatchableInfo &RHS) const {
525 // The primary comparator is the instruction mnemonic.
526 if (Mnemonic != RHS.Mnemonic)
529 // The number of operands is unambiguous.
530 if (AsmOperands.size() != RHS.AsmOperands.size())
533 // Otherwise, make sure the ordering of the two instructions is unambiguous
534 // by checking that either (a) a token or operand kind discriminates them,
535 // or (b) the ordering among equivalent kinds is consistent.
537 // Tokens and operand kinds are unambiguous (assuming a correct target
539 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i)
540 if (AsmOperands[i].Class->Kind != RHS.AsmOperands[i].Class->Kind ||
541 AsmOperands[i].Class->Kind == ClassInfo::Token)
542 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class ||
543 *RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
546 // Otherwise, this operand could commute if all operands are equivalent, or
547 // there is a pair of operands that compare less than and a pair that
548 // compare greater than.
549 bool HasLT = false, HasGT = false;
550 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
551 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class)
553 if (*RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
557 return !(HasLT ^ HasGT);
563 void tokenizeAsmString(const AsmMatcherInfo &Info);
566 /// SubtargetFeatureInfo - Helper class for storing information on a subtarget
567 /// feature which participates in instruction matching.
568 struct SubtargetFeatureInfo {
569 /// \brief The predicate record for this feature.
572 /// \brief An unique index assigned to represent this feature.
575 SubtargetFeatureInfo(Record *D, uint64_t Idx) : TheDef(D), Index(Idx) {}
577 /// \brief The name of the enumerated constant identifying this feature.
578 std::string getEnumName() const {
579 return "Feature_" + TheDef->getName();
583 errs() << getEnumName() << " " << Index << "\n";
588 struct OperandMatchEntry {
589 unsigned OperandMask;
590 const MatchableInfo* MI;
593 static OperandMatchEntry create(const MatchableInfo *mi, ClassInfo *ci,
596 X.OperandMask = opMask;
604 class AsmMatcherInfo {
607 RecordKeeper &Records;
609 /// The tablegen AsmParser record.
612 /// Target - The target information.
613 CodeGenTarget &Target;
615 /// The classes which are needed for matching.
616 std::forward_list<ClassInfo> Classes;
618 /// The information on the matchables to match.
619 std::vector<std::unique_ptr<MatchableInfo>> Matchables;
621 /// Info for custom matching operands by user defined methods.
622 std::vector<OperandMatchEntry> OperandMatchInfo;
624 /// Map of Register records to their class information.
625 typedef std::map<Record*, ClassInfo*, LessRecordByID> RegisterClassesTy;
626 RegisterClassesTy RegisterClasses;
628 /// Map of Predicate records to their subtarget information.
629 std::map<Record*, std::unique_ptr<SubtargetFeatureInfo>,
630 LessRecordByID> SubtargetFeatures;
632 /// Map of AsmOperandClass records to their class information.
633 std::map<Record*, ClassInfo*> AsmOperandClasses;
636 /// Map of token to class information which has already been constructed.
637 std::map<std::string, ClassInfo*> TokenClasses;
639 /// Map of RegisterClass records to their class information.
640 std::map<Record*, ClassInfo*> RegisterClassClasses;
643 /// getTokenClass - Lookup or create the class for the given token.
644 ClassInfo *getTokenClass(StringRef Token);
646 /// getOperandClass - Lookup or create the class for the given operand.
647 ClassInfo *getOperandClass(const CGIOperandList::OperandInfo &OI,
649 ClassInfo *getOperandClass(Record *Rec, int SubOpIdx);
651 /// buildRegisterClasses - Build the ClassInfo* instances for register
653 void buildRegisterClasses(SmallPtrSetImpl<Record*> &SingletonRegisters);
655 /// buildOperandClasses - Build the ClassInfo* instances for user defined
657 void buildOperandClasses();
659 void buildInstructionOperandReference(MatchableInfo *II, StringRef OpName,
661 void buildAliasOperandReference(MatchableInfo *II, StringRef OpName,
662 MatchableInfo::AsmOperand &Op);
665 AsmMatcherInfo(Record *AsmParser,
666 CodeGenTarget &Target,
667 RecordKeeper &Records);
669 /// buildInfo - Construct the various tables used during matching.
672 /// buildOperandMatchInfo - Build the necessary information to handle user
673 /// defined operand parsing methods.
674 void buildOperandMatchInfo();
676 /// getSubtargetFeature - Lookup or create the subtarget feature info for the
678 SubtargetFeatureInfo *getSubtargetFeature(Record *Def) const {
679 assert(Def->isSubClassOf("Predicate") && "Invalid predicate type!");
680 const auto &I = SubtargetFeatures.find(Def);
681 return I == SubtargetFeatures.end() ? nullptr : I->second.get();
684 RecordKeeper &getRecords() const {
689 } // End anonymous namespace
691 void MatchableInfo::dump() const {
692 errs() << TheDef->getName() << " -- " << "flattened:\"" << AsmString <<"\"\n";
694 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
695 const AsmOperand &Op = AsmOperands[i];
696 errs() << " op[" << i << "] = " << Op.Class->ClassName << " - ";
697 errs() << '\"' << Op.Token << "\"\n";
701 static std::pair<StringRef, StringRef>
702 parseTwoOperandConstraint(StringRef S, ArrayRef<SMLoc> Loc) {
703 // Split via the '='.
704 std::pair<StringRef, StringRef> Ops = S.split('=');
705 if (Ops.second == "")
706 PrintFatalError(Loc, "missing '=' in two-operand alias constraint");
707 // Trim whitespace and the leading '$' on the operand names.
708 size_t start = Ops.first.find_first_of('$');
709 if (start == std::string::npos)
710 PrintFatalError(Loc, "expected '$' prefix on asm operand name");
711 Ops.first = Ops.first.slice(start + 1, std::string::npos);
712 size_t end = Ops.first.find_last_of(" \t");
713 Ops.first = Ops.first.slice(0, end);
714 // Now the second operand.
715 start = Ops.second.find_first_of('$');
716 if (start == std::string::npos)
717 PrintFatalError(Loc, "expected '$' prefix on asm operand name");
718 Ops.second = Ops.second.slice(start + 1, std::string::npos);
719 end = Ops.second.find_last_of(" \t");
720 Ops.first = Ops.first.slice(0, end);
724 void MatchableInfo::formTwoOperandAlias(StringRef Constraint) {
725 // Figure out which operands are aliased and mark them as tied.
726 std::pair<StringRef, StringRef> Ops =
727 parseTwoOperandConstraint(Constraint, TheDef->getLoc());
729 // Find the AsmOperands that refer to the operands we're aliasing.
730 int SrcAsmOperand = findAsmOperandNamed(Ops.first);
731 int DstAsmOperand = findAsmOperandNamed(Ops.second);
732 if (SrcAsmOperand == -1)
733 PrintFatalError(TheDef->getLoc(),
734 "unknown source two-operand alias operand '" + Ops.first +
736 if (DstAsmOperand == -1)
737 PrintFatalError(TheDef->getLoc(),
738 "unknown destination two-operand alias operand '" +
741 // Find the ResOperand that refers to the operand we're aliasing away
742 // and update it to refer to the combined operand instead.
743 for (unsigned i = 0, e = ResOperands.size(); i != e; ++i) {
744 ResOperand &Op = ResOperands[i];
745 if (Op.Kind == ResOperand::RenderAsmOperand &&
746 Op.AsmOperandNum == (unsigned)SrcAsmOperand) {
747 Op.AsmOperandNum = DstAsmOperand;
751 // Remove the AsmOperand for the alias operand.
752 AsmOperands.erase(AsmOperands.begin() + SrcAsmOperand);
753 // Adjust the ResOperand references to any AsmOperands that followed
754 // the one we just deleted.
755 for (unsigned i = 0, e = ResOperands.size(); i != e; ++i) {
756 ResOperand &Op = ResOperands[i];
759 // Nothing to do for operands that don't reference AsmOperands.
761 case ResOperand::RenderAsmOperand:
762 if (Op.AsmOperandNum > (unsigned)SrcAsmOperand)
765 case ResOperand::TiedOperand:
766 if (Op.TiedOperandNum > (unsigned)SrcAsmOperand)
773 void MatchableInfo::initialize(const AsmMatcherInfo &Info,
774 SmallPtrSetImpl<Record*> &SingletonRegisters,
775 int AsmVariantNo, std::string &RegisterPrefix) {
776 AsmVariantID = AsmVariantNo;
778 CodeGenInstruction::FlattenAsmStringVariants(AsmString, AsmVariantNo);
780 tokenizeAsmString(Info);
782 // Compute the require features.
783 std::vector<Record*> Predicates =TheDef->getValueAsListOfDefs("Predicates");
784 for (unsigned i = 0, e = Predicates.size(); i != e; ++i)
785 if (SubtargetFeatureInfo *Feature =
786 Info.getSubtargetFeature(Predicates[i]))
787 RequiredFeatures.push_back(Feature);
789 // Collect singleton registers, if used.
790 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
791 extractSingletonRegisterForAsmOperand(i, Info, RegisterPrefix);
792 if (Record *Reg = AsmOperands[i].SingletonReg)
793 SingletonRegisters.insert(Reg);
796 const RecordVal *DepMask = TheDef->getValue("DeprecatedFeatureMask");
798 DepMask = TheDef->getValue("ComplexDeprecationPredicate");
801 DepMask ? !DepMask->getValue()->getAsUnquotedString().empty() : false;
804 /// tokenizeAsmString - Tokenize a simplified assembly string.
805 void MatchableInfo::tokenizeAsmString(const AsmMatcherInfo &Info) {
806 StringRef String = AsmString;
809 for (unsigned i = 0, e = String.size(); i != e; ++i) {
819 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
822 if (!isspace(String[i]) && String[i] != ',')
823 AsmOperands.push_back(AsmOperand(String.substr(i, 1)));
829 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
833 assert(i != String.size() && "Invalid quoted character");
834 AsmOperands.push_back(AsmOperand(String.substr(i, 1)));
840 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
844 // If this isn't "${", treat like a normal token.
845 if (i + 1 == String.size() || String[i + 1] != '{') {
850 StringRef::iterator End = std::find(String.begin() + i, String.end(),'}');
851 assert(End != String.end() && "Missing brace in operand reference!");
852 size_t EndPos = End - String.begin();
853 AsmOperands.push_back(AsmOperand(String.slice(i, EndPos+1)));
860 if (!Info.AsmParser->getValueAsBit("MnemonicContainsDot")) {
862 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
872 if (InTok && Prev != String.size())
873 AsmOperands.push_back(AsmOperand(String.substr(Prev)));
875 // The first token of the instruction is the mnemonic, which must be a
876 // simple string, not a $foo variable or a singleton register.
877 if (AsmOperands.empty())
878 PrintFatalError(TheDef->getLoc(),
879 "Instruction '" + TheDef->getName() + "' has no tokens");
880 Mnemonic = AsmOperands[0].Token;
881 if (Mnemonic.empty())
882 PrintFatalError(TheDef->getLoc(),
883 "Missing instruction mnemonic");
884 // FIXME : Check and raise an error if it is a register.
885 if (Mnemonic[0] == '$')
886 PrintFatalError(TheDef->getLoc(),
887 "Invalid instruction mnemonic '" + Mnemonic + "'!");
889 // Remove the first operand, it is tracked in the mnemonic field.
890 AsmOperands.erase(AsmOperands.begin());
893 bool MatchableInfo::validate(StringRef CommentDelimiter, bool Hack) const {
894 // Reject matchables with no .s string.
895 if (AsmString.empty())
896 PrintFatalError(TheDef->getLoc(), "instruction with empty asm string");
898 // Reject any matchables with a newline in them, they should be marked
899 // isCodeGenOnly if they are pseudo instructions.
900 if (AsmString.find('\n') != std::string::npos)
901 PrintFatalError(TheDef->getLoc(),
902 "multiline instruction is not valid for the asmparser, "
903 "mark it isCodeGenOnly");
905 // Remove comments from the asm string. We know that the asmstring only
907 if (!CommentDelimiter.empty() &&
908 StringRef(AsmString).find(CommentDelimiter) != StringRef::npos)
909 PrintFatalError(TheDef->getLoc(),
910 "asmstring for instruction has comment character in it, "
911 "mark it isCodeGenOnly");
913 // Reject matchables with operand modifiers, these aren't something we can
914 // handle, the target should be refactored to use operands instead of
917 // Also, check for instructions which reference the operand multiple times;
918 // this implies a constraint we would not honor.
919 std::set<std::string> OperandNames;
920 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
921 StringRef Tok = AsmOperands[i].Token;
922 if (Tok[0] == '$' && Tok.find(':') != StringRef::npos)
923 PrintFatalError(TheDef->getLoc(),
924 "matchable with operand modifier '" + Tok +
925 "' not supported by asm matcher. Mark isCodeGenOnly!");
927 // Verify that any operand is only mentioned once.
928 // We reject aliases and ignore instructions for now.
929 if (Tok[0] == '$' && !OperandNames.insert(Tok).second) {
931 PrintFatalError(TheDef->getLoc(),
932 "ERROR: matchable with tied operand '" + Tok +
933 "' can never be matched!");
934 // FIXME: Should reject these. The ARM backend hits this with $lane in a
935 // bunch of instructions. It is unclear what the right answer is.
937 errs() << "warning: '" << TheDef->getName() << "': "
938 << "ignoring instruction with tied operand '"
948 /// extractSingletonRegisterForAsmOperand - Extract singleton register,
949 /// if present, from specified token.
951 extractSingletonRegisterForAsmOperand(unsigned OperandNo,
952 const AsmMatcherInfo &Info,
953 std::string &RegisterPrefix) {
954 StringRef Tok = AsmOperands[OperandNo].Token;
955 if (RegisterPrefix.empty()) {
956 std::string LoweredTok = Tok.lower();
957 if (const CodeGenRegister *Reg = Info.Target.getRegisterByName(LoweredTok))
958 AsmOperands[OperandNo].SingletonReg = Reg->TheDef;
962 if (!Tok.startswith(RegisterPrefix))
965 StringRef RegName = Tok.substr(RegisterPrefix.size());
966 if (const CodeGenRegister *Reg = Info.Target.getRegisterByName(RegName))
967 AsmOperands[OperandNo].SingletonReg = Reg->TheDef;
969 // If there is no register prefix (i.e. "%" in "%eax"), then this may
970 // be some random non-register token, just ignore it.
974 static std::string getEnumNameForToken(StringRef Str) {
977 for (StringRef::iterator it = Str.begin(), ie = Str.end(); it != ie; ++it) {
979 case '*': Res += "_STAR_"; break;
980 case '%': Res += "_PCT_"; break;
981 case ':': Res += "_COLON_"; break;
982 case '!': Res += "_EXCLAIM_"; break;
983 case '.': Res += "_DOT_"; break;
984 case '<': Res += "_LT_"; break;
985 case '>': Res += "_GT_"; break;
987 if ((*it >= 'A' && *it <= 'Z') ||
988 (*it >= 'a' && *it <= 'z') ||
989 (*it >= '0' && *it <= '9'))
992 Res += "_" + utostr((unsigned) *it) + "_";
999 ClassInfo *AsmMatcherInfo::getTokenClass(StringRef Token) {
1000 ClassInfo *&Entry = TokenClasses[Token];
1003 Classes.emplace_front();
1004 Entry = &Classes.front();
1005 Entry->Kind = ClassInfo::Token;
1006 Entry->ClassName = "Token";
1007 Entry->Name = "MCK_" + getEnumNameForToken(Token);
1008 Entry->ValueName = Token;
1009 Entry->PredicateMethod = "<invalid>";
1010 Entry->RenderMethod = "<invalid>";
1011 Entry->ParserMethod = "";
1012 Entry->DiagnosticType = "";
1019 AsmMatcherInfo::getOperandClass(const CGIOperandList::OperandInfo &OI,
1021 Record *Rec = OI.Rec;
1023 Rec = cast<DefInit>(OI.MIOperandInfo->getArg(SubOpIdx))->getDef();
1024 return getOperandClass(Rec, SubOpIdx);
1028 AsmMatcherInfo::getOperandClass(Record *Rec, int SubOpIdx) {
1029 if (Rec->isSubClassOf("RegisterOperand")) {
1030 // RegisterOperand may have an associated ParserMatchClass. If it does,
1031 // use it, else just fall back to the underlying register class.
1032 const RecordVal *R = Rec->getValue("ParserMatchClass");
1033 if (!R || !R->getValue())
1034 PrintFatalError("Record `" + Rec->getName() +
1035 "' does not have a ParserMatchClass!\n");
1037 if (DefInit *DI= dyn_cast<DefInit>(R->getValue())) {
1038 Record *MatchClass = DI->getDef();
1039 if (ClassInfo *CI = AsmOperandClasses[MatchClass])
1043 // No custom match class. Just use the register class.
1044 Record *ClassRec = Rec->getValueAsDef("RegClass");
1046 PrintFatalError(Rec->getLoc(), "RegisterOperand `" + Rec->getName() +
1047 "' has no associated register class!\n");
1048 if (ClassInfo *CI = RegisterClassClasses[ClassRec])
1050 PrintFatalError(Rec->getLoc(), "register class has no class info!");
1054 if (Rec->isSubClassOf("RegisterClass")) {
1055 if (ClassInfo *CI = RegisterClassClasses[Rec])
1057 PrintFatalError(Rec->getLoc(), "register class has no class info!");
1060 if (!Rec->isSubClassOf("Operand"))
1061 PrintFatalError(Rec->getLoc(), "Operand `" + Rec->getName() +
1062 "' does not derive from class Operand!\n");
1063 Record *MatchClass = Rec->getValueAsDef("ParserMatchClass");
1064 if (ClassInfo *CI = AsmOperandClasses[MatchClass])
1067 PrintFatalError(Rec->getLoc(), "operand has no match class!");
1070 struct LessRegisterSet {
1071 bool operator() (const RegisterSet &LHS, const RegisterSet & RHS) const {
1072 // std::set<T> defines its own compariso "operator<", but it
1073 // performs a lexicographical comparison by T's innate comparison
1074 // for some reason. We don't want non-deterministic pointer
1075 // comparisons so use this instead.
1076 return std::lexicographical_compare(LHS.begin(), LHS.end(),
1077 RHS.begin(), RHS.end(),
1082 void AsmMatcherInfo::
1083 buildRegisterClasses(SmallPtrSetImpl<Record*> &SingletonRegisters) {
1084 const std::vector<CodeGenRegister*> &Registers =
1085 Target.getRegBank().getRegisters();
1086 ArrayRef<CodeGenRegisterClass*> RegClassList =
1087 Target.getRegBank().getRegClasses();
1089 typedef std::set<RegisterSet, LessRegisterSet> RegisterSetSet;
1091 // The register sets used for matching.
1092 RegisterSetSet RegisterSets;
1094 // Gather the defined sets.
1095 for (const CodeGenRegisterClass *RC : RegClassList)
1096 RegisterSets.insert(RegisterSet(RC->getOrder().begin(),
1097 RC->getOrder().end()));
1099 // Add any required singleton sets.
1100 for (Record *Rec : SingletonRegisters) {
1101 RegisterSets.insert(RegisterSet(&Rec, &Rec + 1));
1104 // Introduce derived sets where necessary (when a register does not determine
1105 // a unique register set class), and build the mapping of registers to the set
1106 // they should classify to.
1107 std::map<Record*, RegisterSet> RegisterMap;
1108 for (const CodeGenRegister *CGR : Registers) {
1109 // Compute the intersection of all sets containing this register.
1110 RegisterSet ContainingSet;
1112 for (const RegisterSet &RS : RegisterSets) {
1113 if (!RS.count(CGR->TheDef))
1116 if (ContainingSet.empty()) {
1122 std::swap(Tmp, ContainingSet);
1123 std::insert_iterator<RegisterSet> II(ContainingSet,
1124 ContainingSet.begin());
1125 std::set_intersection(Tmp.begin(), Tmp.end(), RS.begin(), RS.end(), II,
1129 if (!ContainingSet.empty()) {
1130 RegisterSets.insert(ContainingSet);
1131 RegisterMap.insert(std::make_pair(CGR->TheDef, ContainingSet));
1135 // Construct the register classes.
1136 std::map<RegisterSet, ClassInfo*, LessRegisterSet> RegisterSetClasses;
1138 for (const RegisterSet &RS : RegisterSets) {
1139 Classes.emplace_front();
1140 ClassInfo *CI = &Classes.front();
1141 CI->Kind = ClassInfo::RegisterClass0 + Index;
1142 CI->ClassName = "Reg" + utostr(Index);
1143 CI->Name = "MCK_Reg" + utostr(Index);
1145 CI->PredicateMethod = ""; // unused
1146 CI->RenderMethod = "addRegOperands";
1148 // FIXME: diagnostic type.
1149 CI->DiagnosticType = "";
1150 RegisterSetClasses.insert(std::make_pair(RS, CI));
1154 // Find the superclasses; we could compute only the subgroup lattice edges,
1155 // but there isn't really a point.
1156 for (const RegisterSet &RS : RegisterSets) {
1157 ClassInfo *CI = RegisterSetClasses[RS];
1158 for (const RegisterSet &RS2 : RegisterSets)
1160 std::includes(RS2.begin(), RS2.end(), RS.begin(), RS.end(),
1162 CI->SuperClasses.push_back(RegisterSetClasses[RS2]);
1165 // Name the register classes which correspond to a user defined RegisterClass.
1166 for (const CodeGenRegisterClass *RC : RegClassList) {
1167 // Def will be NULL for non-user defined register classes.
1168 Record *Def = RC->getDef();
1171 ClassInfo *CI = RegisterSetClasses[RegisterSet(RC->getOrder().begin(),
1172 RC->getOrder().end())];
1173 if (CI->ValueName.empty()) {
1174 CI->ClassName = RC->getName();
1175 CI->Name = "MCK_" + RC->getName();
1176 CI->ValueName = RC->getName();
1178 CI->ValueName = CI->ValueName + "," + RC->getName();
1180 RegisterClassClasses.insert(std::make_pair(Def, CI));
1183 // Populate the map for individual registers.
1184 for (std::map<Record*, RegisterSet>::iterator it = RegisterMap.begin(),
1185 ie = RegisterMap.end(); it != ie; ++it)
1186 RegisterClasses[it->first] = RegisterSetClasses[it->second];
1188 // Name the register classes which correspond to singleton registers.
1189 for (Record *Rec : SingletonRegisters) {
1190 ClassInfo *CI = RegisterClasses[Rec];
1191 assert(CI && "Missing singleton register class info!");
1193 if (CI->ValueName.empty()) {
1194 CI->ClassName = Rec->getName();
1195 CI->Name = "MCK_" + Rec->getName();
1196 CI->ValueName = Rec->getName();
1198 CI->ValueName = CI->ValueName + "," + Rec->getName();
1202 void AsmMatcherInfo::buildOperandClasses() {
1203 std::vector<Record*> AsmOperands =
1204 Records.getAllDerivedDefinitions("AsmOperandClass");
1206 // Pre-populate AsmOperandClasses map.
1207 for (Record *Rec : AsmOperands) {
1208 Classes.emplace_front();
1209 AsmOperandClasses[Rec] = &Classes.front();
1213 for (Record *Rec : AsmOperands) {
1214 ClassInfo *CI = AsmOperandClasses[Rec];
1215 CI->Kind = ClassInfo::UserClass0 + Index;
1217 ListInit *Supers = Rec->getValueAsListInit("SuperClasses");
1218 for (unsigned i = 0, e = Supers->getSize(); i != e; ++i) {
1219 DefInit *DI = dyn_cast<DefInit>(Supers->getElement(i));
1221 PrintError(Rec->getLoc(), "Invalid super class reference!");
1225 ClassInfo *SC = AsmOperandClasses[DI->getDef()];
1227 PrintError(Rec->getLoc(), "Invalid super class reference!");
1229 CI->SuperClasses.push_back(SC);
1231 CI->ClassName = Rec->getValueAsString("Name");
1232 CI->Name = "MCK_" + CI->ClassName;
1233 CI->ValueName = Rec->getName();
1235 // Get or construct the predicate method name.
1236 Init *PMName = Rec->getValueInit("PredicateMethod");
1237 if (StringInit *SI = dyn_cast<StringInit>(PMName)) {
1238 CI->PredicateMethod = SI->getValue();
1240 assert(isa<UnsetInit>(PMName) && "Unexpected PredicateMethod field!");
1241 CI->PredicateMethod = "is" + CI->ClassName;
1244 // Get or construct the render method name.
1245 Init *RMName = Rec->getValueInit("RenderMethod");
1246 if (StringInit *SI = dyn_cast<StringInit>(RMName)) {
1247 CI->RenderMethod = SI->getValue();
1249 assert(isa<UnsetInit>(RMName) && "Unexpected RenderMethod field!");
1250 CI->RenderMethod = "add" + CI->ClassName + "Operands";
1253 // Get the parse method name or leave it as empty.
1254 Init *PRMName = Rec->getValueInit("ParserMethod");
1255 if (StringInit *SI = dyn_cast<StringInit>(PRMName))
1256 CI->ParserMethod = SI->getValue();
1258 // Get the diagnostic type or leave it as empty.
1259 // Get the parse method name or leave it as empty.
1260 Init *DiagnosticType = Rec->getValueInit("DiagnosticType");
1261 if (StringInit *SI = dyn_cast<StringInit>(DiagnosticType))
1262 CI->DiagnosticType = SI->getValue();
1268 AsmMatcherInfo::AsmMatcherInfo(Record *asmParser,
1269 CodeGenTarget &target,
1270 RecordKeeper &records)
1271 : Records(records), AsmParser(asmParser), Target(target) {
1274 /// buildOperandMatchInfo - Build the necessary information to handle user
1275 /// defined operand parsing methods.
1276 void AsmMatcherInfo::buildOperandMatchInfo() {
1278 /// Map containing a mask with all operands indices that can be found for
1279 /// that class inside a instruction.
1280 typedef std::map<ClassInfo *, unsigned, less_ptr<ClassInfo>> OpClassMaskTy;
1281 OpClassMaskTy OpClassMask;
1283 for (const auto &MI : Matchables) {
1284 OpClassMask.clear();
1286 // Keep track of all operands of this instructions which belong to the
1288 for (unsigned i = 0, e = MI->AsmOperands.size(); i != e; ++i) {
1289 const MatchableInfo::AsmOperand &Op = MI->AsmOperands[i];
1290 if (Op.Class->ParserMethod.empty())
1292 unsigned &OperandMask = OpClassMask[Op.Class];
1293 OperandMask |= (1 << i);
1296 // Generate operand match info for each mnemonic/operand class pair.
1297 for (const auto &OCM : OpClassMask) {
1298 unsigned OpMask = OCM.second;
1299 ClassInfo *CI = OCM.first;
1300 OperandMatchInfo.push_back(OperandMatchEntry::create(MI.get(), CI,
1306 void AsmMatcherInfo::buildInfo() {
1307 // Build information about all of the AssemblerPredicates.
1308 std::vector<Record*> AllPredicates =
1309 Records.getAllDerivedDefinitions("Predicate");
1310 for (unsigned i = 0, e = AllPredicates.size(); i != e; ++i) {
1311 Record *Pred = AllPredicates[i];
1312 // Ignore predicates that are not intended for the assembler.
1313 if (!Pred->getValueAsBit("AssemblerMatcherPredicate"))
1316 if (Pred->getName().empty())
1317 PrintFatalError(Pred->getLoc(), "Predicate has no name!");
1319 uint64_t FeatureNo = SubtargetFeatures.size();
1320 SubtargetFeatures[Pred] =
1321 llvm::make_unique<SubtargetFeatureInfo>(Pred, FeatureNo);
1322 DEBUG(SubtargetFeatures[Pred]->dump());
1323 assert(FeatureNo < 64 && "Too many subtarget features!");
1326 // Parse the instructions; we need to do this first so that we can gather the
1327 // singleton register classes.
1328 SmallPtrSet<Record*, 16> SingletonRegisters;
1329 unsigned VariantCount = Target.getAsmParserVariantCount();
1330 for (unsigned VC = 0; VC != VariantCount; ++VC) {
1331 Record *AsmVariant = Target.getAsmParserVariant(VC);
1332 std::string CommentDelimiter =
1333 AsmVariant->getValueAsString("CommentDelimiter");
1334 std::string RegisterPrefix = AsmVariant->getValueAsString("RegisterPrefix");
1335 int AsmVariantNo = AsmVariant->getValueAsInt("Variant");
1337 for (const CodeGenInstruction *CGI : Target.instructions()) {
1339 // If the tblgen -match-prefix option is specified (for tblgen hackers),
1340 // filter the set of instructions we consider.
1341 if (!StringRef(CGI->TheDef->getName()).startswith(MatchPrefix))
1344 // Ignore "codegen only" instructions.
1345 if (CGI->TheDef->getValueAsBit("isCodeGenOnly"))
1348 std::unique_ptr<MatchableInfo> II(new MatchableInfo(*CGI));
1350 II->initialize(*this, SingletonRegisters, AsmVariantNo, RegisterPrefix);
1352 // Ignore instructions which shouldn't be matched and diagnose invalid
1353 // instruction definitions with an error.
1354 if (!II->validate(CommentDelimiter, true))
1357 Matchables.push_back(std::move(II));
1360 // Parse all of the InstAlias definitions and stick them in the list of
1362 std::vector<Record*> AllInstAliases =
1363 Records.getAllDerivedDefinitions("InstAlias");
1364 for (unsigned i = 0, e = AllInstAliases.size(); i != e; ++i) {
1365 CodeGenInstAlias *Alias =
1366 new CodeGenInstAlias(AllInstAliases[i], AsmVariantNo, Target);
1368 // If the tblgen -match-prefix option is specified (for tblgen hackers),
1369 // filter the set of instruction aliases we consider, based on the target
1371 if (!StringRef(Alias->ResultInst->TheDef->getName())
1372 .startswith( MatchPrefix))
1375 std::unique_ptr<MatchableInfo> II(new MatchableInfo(Alias));
1377 II->initialize(*this, SingletonRegisters, AsmVariantNo, RegisterPrefix);
1379 // Validate the alias definitions.
1380 II->validate(CommentDelimiter, false);
1382 Matchables.push_back(std::move(II));
1386 // Build info for the register classes.
1387 buildRegisterClasses(SingletonRegisters);
1389 // Build info for the user defined assembly operand classes.
1390 buildOperandClasses();
1392 // Build the information about matchables, now that we have fully formed
1394 std::vector<std::unique_ptr<MatchableInfo>> NewMatchables;
1395 for (auto &II : Matchables) {
1396 // Parse the tokens after the mnemonic.
1397 // Note: buildInstructionOperandReference may insert new AsmOperands, so
1398 // don't precompute the loop bound.
1399 for (unsigned i = 0; i != II->AsmOperands.size(); ++i) {
1400 MatchableInfo::AsmOperand &Op = II->AsmOperands[i];
1401 StringRef Token = Op.Token;
1403 // Check for singleton registers.
1404 if (Record *RegRecord = II->AsmOperands[i].SingletonReg) {
1405 Op.Class = RegisterClasses[RegRecord];
1406 assert(Op.Class && Op.Class->Registers.size() == 1 &&
1407 "Unexpected class for singleton register");
1411 // Check for simple tokens.
1412 if (Token[0] != '$') {
1413 Op.Class = getTokenClass(Token);
1417 if (Token.size() > 1 && isdigit(Token[1])) {
1418 Op.Class = getTokenClass(Token);
1422 // Otherwise this is an operand reference.
1423 StringRef OperandName;
1424 if (Token[1] == '{')
1425 OperandName = Token.substr(2, Token.size() - 3);
1427 OperandName = Token.substr(1);
1429 if (II->DefRec.is<const CodeGenInstruction*>())
1430 buildInstructionOperandReference(II.get(), OperandName, i);
1432 buildAliasOperandReference(II.get(), OperandName, Op);
1435 if (II->DefRec.is<const CodeGenInstruction*>()) {
1436 II->buildInstructionResultOperands();
1437 // If the instruction has a two-operand alias, build up the
1438 // matchable here. We'll add them in bulk at the end to avoid
1439 // confusing this loop.
1440 std::string Constraint =
1441 II->TheDef->getValueAsString("TwoOperandAliasConstraint");
1442 if (Constraint != "") {
1443 // Start by making a copy of the original matchable.
1444 std::unique_ptr<MatchableInfo> AliasII(new MatchableInfo(*II));
1446 // Adjust it to be a two-operand alias.
1447 AliasII->formTwoOperandAlias(Constraint);
1449 // Add the alias to the matchables list.
1450 NewMatchables.push_back(std::move(AliasII));
1453 II->buildAliasResultOperands();
1455 if (!NewMatchables.empty())
1456 std::move(NewMatchables.begin(), NewMatchables.end(),
1457 std::back_inserter(Matchables));
1459 // Process token alias definitions and set up the associated superclass
1461 std::vector<Record*> AllTokenAliases =
1462 Records.getAllDerivedDefinitions("TokenAlias");
1463 for (unsigned i = 0, e = AllTokenAliases.size(); i != e; ++i) {
1464 Record *Rec = AllTokenAliases[i];
1465 ClassInfo *FromClass = getTokenClass(Rec->getValueAsString("FromToken"));
1466 ClassInfo *ToClass = getTokenClass(Rec->getValueAsString("ToToken"));
1467 if (FromClass == ToClass)
1468 PrintFatalError(Rec->getLoc(),
1469 "error: Destination value identical to source value.");
1470 FromClass->SuperClasses.push_back(ToClass);
1473 // Reorder classes so that classes precede super classes.
1477 /// buildInstructionOperandReference - The specified operand is a reference to a
1478 /// named operand such as $src. Resolve the Class and OperandInfo pointers.
1479 void AsmMatcherInfo::
1480 buildInstructionOperandReference(MatchableInfo *II,
1481 StringRef OperandName,
1482 unsigned AsmOpIdx) {
1483 const CodeGenInstruction &CGI = *II->DefRec.get<const CodeGenInstruction*>();
1484 const CGIOperandList &Operands = CGI.Operands;
1485 MatchableInfo::AsmOperand *Op = &II->AsmOperands[AsmOpIdx];
1487 // Map this token to an operand.
1489 if (!Operands.hasOperandNamed(OperandName, Idx))
1490 PrintFatalError(II->TheDef->getLoc(),
1491 "error: unable to find operand: '" + OperandName + "'");
1493 // If the instruction operand has multiple suboperands, but the parser
1494 // match class for the asm operand is still the default "ImmAsmOperand",
1495 // then handle each suboperand separately.
1496 if (Op->SubOpIdx == -1 && Operands[Idx].MINumOperands > 1) {
1497 Record *Rec = Operands[Idx].Rec;
1498 assert(Rec->isSubClassOf("Operand") && "Unexpected operand!");
1499 Record *MatchClass = Rec->getValueAsDef("ParserMatchClass");
1500 if (MatchClass && MatchClass->getValueAsString("Name") == "Imm") {
1501 // Insert remaining suboperands after AsmOpIdx in II->AsmOperands.
1502 StringRef Token = Op->Token; // save this in case Op gets moved
1503 for (unsigned SI = 1, SE = Operands[Idx].MINumOperands; SI != SE; ++SI) {
1504 MatchableInfo::AsmOperand NewAsmOp(Token);
1505 NewAsmOp.SubOpIdx = SI;
1506 II->AsmOperands.insert(II->AsmOperands.begin()+AsmOpIdx+SI, NewAsmOp);
1508 // Replace Op with first suboperand.
1509 Op = &II->AsmOperands[AsmOpIdx]; // update the pointer in case it moved
1514 // Set up the operand class.
1515 Op->Class = getOperandClass(Operands[Idx], Op->SubOpIdx);
1517 // If the named operand is tied, canonicalize it to the untied operand.
1518 // For example, something like:
1519 // (outs GPR:$dst), (ins GPR:$src)
1520 // with an asmstring of
1522 // we want to canonicalize to:
1524 // so that we know how to provide the $dst operand when filling in the result.
1526 if (Operands[Idx].MINumOperands == 1)
1527 OITied = Operands[Idx].getTiedRegister();
1529 // The tied operand index is an MIOperand index, find the operand that
1531 std::pair<unsigned, unsigned> Idx = Operands.getSubOperandNumber(OITied);
1532 OperandName = Operands[Idx.first].Name;
1533 Op->SubOpIdx = Idx.second;
1536 Op->SrcOpName = OperandName;
1539 /// buildAliasOperandReference - When parsing an operand reference out of the
1540 /// matching string (e.g. "movsx $src, $dst"), determine what the class of the
1541 /// operand reference is by looking it up in the result pattern definition.
1542 void AsmMatcherInfo::buildAliasOperandReference(MatchableInfo *II,
1543 StringRef OperandName,
1544 MatchableInfo::AsmOperand &Op) {
1545 const CodeGenInstAlias &CGA = *II->DefRec.get<const CodeGenInstAlias*>();
1547 // Set up the operand class.
1548 for (unsigned i = 0, e = CGA.ResultOperands.size(); i != e; ++i)
1549 if (CGA.ResultOperands[i].isRecord() &&
1550 CGA.ResultOperands[i].getName() == OperandName) {
1551 // It's safe to go with the first one we find, because CodeGenInstAlias
1552 // validates that all operands with the same name have the same record.
1553 Op.SubOpIdx = CGA.ResultInstOperandIndex[i].second;
1554 // Use the match class from the Alias definition, not the
1555 // destination instruction, as we may have an immediate that's
1556 // being munged by the match class.
1557 Op.Class = getOperandClass(CGA.ResultOperands[i].getRecord(),
1559 Op.SrcOpName = OperandName;
1563 PrintFatalError(II->TheDef->getLoc(),
1564 "error: unable to find operand: '" + OperandName + "'");
1567 void MatchableInfo::buildInstructionResultOperands() {
1568 const CodeGenInstruction *ResultInst = getResultInst();
1570 // Loop over all operands of the result instruction, determining how to
1572 for (unsigned i = 0, e = ResultInst->Operands.size(); i != e; ++i) {
1573 const CGIOperandList::OperandInfo &OpInfo = ResultInst->Operands[i];
1575 // If this is a tied operand, just copy from the previously handled operand.
1577 if (OpInfo.MINumOperands == 1)
1578 TiedOp = OpInfo.getTiedRegister();
1580 ResOperands.push_back(ResOperand::getTiedOp(TiedOp));
1584 // Find out what operand from the asmparser this MCInst operand comes from.
1585 int SrcOperand = findAsmOperandNamed(OpInfo.Name);
1586 if (OpInfo.Name.empty() || SrcOperand == -1) {
1587 // This may happen for operands that are tied to a suboperand of a
1588 // complex operand. Simply use a dummy value here; nobody should
1589 // use this operand slot.
1590 // FIXME: The long term goal is for the MCOperand list to not contain
1591 // tied operands at all.
1592 ResOperands.push_back(ResOperand::getImmOp(0));
1596 // Check if the one AsmOperand populates the entire operand.
1597 unsigned NumOperands = OpInfo.MINumOperands;
1598 if (AsmOperands[SrcOperand].SubOpIdx == -1) {
1599 ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand, NumOperands));
1603 // Add a separate ResOperand for each suboperand.
1604 for (unsigned AI = 0; AI < NumOperands; ++AI) {
1605 assert(AsmOperands[SrcOperand+AI].SubOpIdx == (int)AI &&
1606 AsmOperands[SrcOperand+AI].SrcOpName == OpInfo.Name &&
1607 "unexpected AsmOperands for suboperands");
1608 ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand + AI, 1));
1613 void MatchableInfo::buildAliasResultOperands() {
1614 const CodeGenInstAlias &CGA = *DefRec.get<const CodeGenInstAlias*>();
1615 const CodeGenInstruction *ResultInst = getResultInst();
1617 // Loop over all operands of the result instruction, determining how to
1619 unsigned AliasOpNo = 0;
1620 unsigned LastOpNo = CGA.ResultInstOperandIndex.size();
1621 for (unsigned i = 0, e = ResultInst->Operands.size(); i != e; ++i) {
1622 const CGIOperandList::OperandInfo *OpInfo = &ResultInst->Operands[i];
1624 // If this is a tied operand, just copy from the previously handled operand.
1626 if (OpInfo->MINumOperands == 1)
1627 TiedOp = OpInfo->getTiedRegister();
1629 ResOperands.push_back(ResOperand::getTiedOp(TiedOp));
1633 // Handle all the suboperands for this operand.
1634 const std::string &OpName = OpInfo->Name;
1635 for ( ; AliasOpNo < LastOpNo &&
1636 CGA.ResultInstOperandIndex[AliasOpNo].first == i; ++AliasOpNo) {
1637 int SubIdx = CGA.ResultInstOperandIndex[AliasOpNo].second;
1639 // Find out what operand from the asmparser that this MCInst operand
1641 switch (CGA.ResultOperands[AliasOpNo].Kind) {
1642 case CodeGenInstAlias::ResultOperand::K_Record: {
1643 StringRef Name = CGA.ResultOperands[AliasOpNo].getName();
1644 int SrcOperand = findAsmOperand(Name, SubIdx);
1645 if (SrcOperand == -1)
1646 PrintFatalError(TheDef->getLoc(), "Instruction '" +
1647 TheDef->getName() + "' has operand '" + OpName +
1648 "' that doesn't appear in asm string!");
1649 unsigned NumOperands = (SubIdx == -1 ? OpInfo->MINumOperands : 1);
1650 ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand,
1654 case CodeGenInstAlias::ResultOperand::K_Imm: {
1655 int64_t ImmVal = CGA.ResultOperands[AliasOpNo].getImm();
1656 ResOperands.push_back(ResOperand::getImmOp(ImmVal));
1659 case CodeGenInstAlias::ResultOperand::K_Reg: {
1660 Record *Reg = CGA.ResultOperands[AliasOpNo].getRegister();
1661 ResOperands.push_back(ResOperand::getRegOp(Reg));
1669 static unsigned getConverterOperandID(const std::string &Name,
1670 SetVector<std::string> &Table,
1672 IsNew = Table.insert(Name);
1674 unsigned ID = IsNew ? Table.size() - 1 :
1675 std::find(Table.begin(), Table.end(), Name) - Table.begin();
1677 assert(ID < Table.size());
1683 static void emitConvertFuncs(CodeGenTarget &Target, StringRef ClassName,
1684 std::vector<std::unique_ptr<MatchableInfo>> &Infos,
1686 SetVector<std::string> OperandConversionKinds;
1687 SetVector<std::string> InstructionConversionKinds;
1688 std::vector<std::vector<uint8_t> > ConversionTable;
1689 size_t MaxRowLength = 2; // minimum is custom converter plus terminator.
1691 // TargetOperandClass - This is the target's operand class, like X86Operand.
1692 std::string TargetOperandClass = Target.getName() + "Operand";
1694 // Write the convert function to a separate stream, so we can drop it after
1695 // the enum. We'll build up the conversion handlers for the individual
1696 // operand types opportunistically as we encounter them.
1697 std::string ConvertFnBody;
1698 raw_string_ostream CvtOS(ConvertFnBody);
1699 // Start the unified conversion function.
1700 CvtOS << "void " << Target.getName() << ClassName << "::\n"
1701 << "convertToMCInst(unsigned Kind, MCInst &Inst, "
1702 << "unsigned Opcode,\n"
1703 << " const OperandVector"
1704 << " &Operands) {\n"
1705 << " assert(Kind < CVT_NUM_SIGNATURES && \"Invalid signature!\");\n"
1706 << " const uint8_t *Converter = ConversionTable[Kind];\n"
1707 << " Inst.setOpcode(Opcode);\n"
1708 << " for (const uint8_t *p = Converter; *p; p+= 2) {\n"
1709 << " switch (*p) {\n"
1710 << " default: llvm_unreachable(\"invalid conversion entry!\");\n"
1711 << " case CVT_Reg:\n"
1712 << " static_cast<" << TargetOperandClass
1713 << "&>(*Operands[*(p + 1)]).addRegOperands(Inst, 1);\n"
1715 << " case CVT_Tied:\n"
1716 << " Inst.addOperand(Inst.getOperand(*(p + 1)));\n"
1719 std::string OperandFnBody;
1720 raw_string_ostream OpOS(OperandFnBody);
1721 // Start the operand number lookup function.
1722 OpOS << "void " << Target.getName() << ClassName << "::\n"
1723 << "convertToMapAndConstraints(unsigned Kind,\n";
1725 OpOS << "const OperandVector &Operands) {\n"
1726 << " assert(Kind < CVT_NUM_SIGNATURES && \"Invalid signature!\");\n"
1727 << " unsigned NumMCOperands = 0;\n"
1728 << " const uint8_t *Converter = ConversionTable[Kind];\n"
1729 << " for (const uint8_t *p = Converter; *p; p+= 2) {\n"
1730 << " switch (*p) {\n"
1731 << " default: llvm_unreachable(\"invalid conversion entry!\");\n"
1732 << " case CVT_Reg:\n"
1733 << " Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n"
1734 << " Operands[*(p + 1)]->setConstraint(\"r\");\n"
1735 << " ++NumMCOperands;\n"
1737 << " case CVT_Tied:\n"
1738 << " ++NumMCOperands;\n"
1741 // Pre-populate the operand conversion kinds with the standard always
1742 // available entries.
1743 OperandConversionKinds.insert("CVT_Done");
1744 OperandConversionKinds.insert("CVT_Reg");
1745 OperandConversionKinds.insert("CVT_Tied");
1746 enum { CVT_Done, CVT_Reg, CVT_Tied };
1748 for (auto &II : Infos) {
1749 // Check if we have a custom match function.
1750 std::string AsmMatchConverter =
1751 II->getResultInst()->TheDef->getValueAsString("AsmMatchConverter");
1752 if (!AsmMatchConverter.empty()) {
1753 std::string Signature = "ConvertCustom_" + AsmMatchConverter;
1754 II->ConversionFnKind = Signature;
1756 // Check if we have already generated this signature.
1757 if (!InstructionConversionKinds.insert(Signature))
1760 // Remember this converter for the kind enum.
1761 unsigned KindID = OperandConversionKinds.size();
1762 OperandConversionKinds.insert("CVT_" +
1763 getEnumNameForToken(AsmMatchConverter));
1765 // Add the converter row for this instruction.
1766 ConversionTable.push_back(std::vector<uint8_t>());
1767 ConversionTable.back().push_back(KindID);
1768 ConversionTable.back().push_back(CVT_Done);
1770 // Add the handler to the conversion driver function.
1771 CvtOS << " case CVT_"
1772 << getEnumNameForToken(AsmMatchConverter) << ":\n"
1773 << " " << AsmMatchConverter << "(Inst, Operands);\n"
1776 // FIXME: Handle the operand number lookup for custom match functions.
1780 // Build the conversion function signature.
1781 std::string Signature = "Convert";
1783 std::vector<uint8_t> ConversionRow;
1785 // Compute the convert enum and the case body.
1786 MaxRowLength = std::max(MaxRowLength, II->ResOperands.size()*2 + 1 );
1788 for (unsigned i = 0, e = II->ResOperands.size(); i != e; ++i) {
1789 const MatchableInfo::ResOperand &OpInfo = II->ResOperands[i];
1791 // Generate code to populate each result operand.
1792 switch (OpInfo.Kind) {
1793 case MatchableInfo::ResOperand::RenderAsmOperand: {
1794 // This comes from something we parsed.
1795 const MatchableInfo::AsmOperand &Op =
1796 II->AsmOperands[OpInfo.AsmOperandNum];
1798 // Registers are always converted the same, don't duplicate the
1799 // conversion function based on them.
1802 Class = Op.Class->isRegisterClass() ? "Reg" : Op.Class->ClassName;
1804 Signature += utostr(OpInfo.MINumOperands);
1805 Signature += "_" + itostr(OpInfo.AsmOperandNum);
1807 // Add the conversion kind, if necessary, and get the associated ID
1808 // the index of its entry in the vector).
1809 std::string Name = "CVT_" + (Op.Class->isRegisterClass() ? "Reg" :
1810 Op.Class->RenderMethod);
1811 Name = getEnumNameForToken(Name);
1813 bool IsNewConverter = false;
1814 unsigned ID = getConverterOperandID(Name, OperandConversionKinds,
1817 // Add the operand entry to the instruction kind conversion row.
1818 ConversionRow.push_back(ID);
1819 ConversionRow.push_back(OpInfo.AsmOperandNum + 1);
1821 if (!IsNewConverter)
1824 // This is a new operand kind. Add a handler for it to the
1825 // converter driver.
1826 CvtOS << " case " << Name << ":\n"
1827 << " static_cast<" << TargetOperandClass
1828 << "&>(*Operands[*(p + 1)])." << Op.Class->RenderMethod
1829 << "(Inst, " << OpInfo.MINumOperands << ");\n"
1832 // Add a handler for the operand number lookup.
1833 OpOS << " case " << Name << ":\n"
1834 << " Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n";
1836 if (Op.Class->isRegisterClass())
1837 OpOS << " Operands[*(p + 1)]->setConstraint(\"r\");\n";
1839 OpOS << " Operands[*(p + 1)]->setConstraint(\"m\");\n";
1840 OpOS << " NumMCOperands += " << OpInfo.MINumOperands << ";\n"
1844 case MatchableInfo::ResOperand::TiedOperand: {
1845 // If this operand is tied to a previous one, just copy the MCInst
1846 // operand from the earlier one.We can only tie single MCOperand values.
1847 assert(OpInfo.MINumOperands == 1 && "Not a singular MCOperand");
1848 unsigned TiedOp = OpInfo.TiedOperandNum;
1849 assert(i > TiedOp && "Tied operand precedes its target!");
1850 Signature += "__Tie" + utostr(TiedOp);
1851 ConversionRow.push_back(CVT_Tied);
1852 ConversionRow.push_back(TiedOp);
1855 case MatchableInfo::ResOperand::ImmOperand: {
1856 int64_t Val = OpInfo.ImmVal;
1857 std::string Ty = "imm_" + itostr(Val);
1858 Signature += "__" + Ty;
1860 std::string Name = "CVT_" + Ty;
1861 bool IsNewConverter = false;
1862 unsigned ID = getConverterOperandID(Name, OperandConversionKinds,
1864 // Add the operand entry to the instruction kind conversion row.
1865 ConversionRow.push_back(ID);
1866 ConversionRow.push_back(0);
1868 if (!IsNewConverter)
1871 CvtOS << " case " << Name << ":\n"
1872 << " Inst.addOperand(MCOperand::CreateImm(" << Val << "));\n"
1875 OpOS << " case " << Name << ":\n"
1876 << " Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n"
1877 << " Operands[*(p + 1)]->setConstraint(\"\");\n"
1878 << " ++NumMCOperands;\n"
1882 case MatchableInfo::ResOperand::RegOperand: {
1883 std::string Reg, Name;
1884 if (!OpInfo.Register) {
1888 Reg = getQualifiedName(OpInfo.Register);
1889 Name = "reg" + OpInfo.Register->getName();
1891 Signature += "__" + Name;
1892 Name = "CVT_" + Name;
1893 bool IsNewConverter = false;
1894 unsigned ID = getConverterOperandID(Name, OperandConversionKinds,
1896 // Add the operand entry to the instruction kind conversion row.
1897 ConversionRow.push_back(ID);
1898 ConversionRow.push_back(0);
1900 if (!IsNewConverter)
1902 CvtOS << " case " << Name << ":\n"
1903 << " Inst.addOperand(MCOperand::CreateReg(" << Reg << "));\n"
1906 OpOS << " case " << Name << ":\n"
1907 << " Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n"
1908 << " Operands[*(p + 1)]->setConstraint(\"m\");\n"
1909 << " ++NumMCOperands;\n"
1915 // If there were no operands, add to the signature to that effect
1916 if (Signature == "Convert")
1917 Signature += "_NoOperands";
1919 II->ConversionFnKind = Signature;
1921 // Save the signature. If we already have it, don't add a new row
1923 if (!InstructionConversionKinds.insert(Signature))
1926 // Add the row to the table.
1927 ConversionTable.push_back(ConversionRow);
1930 // Finish up the converter driver function.
1931 CvtOS << " }\n }\n}\n\n";
1933 // Finish up the operand number lookup function.
1934 OpOS << " }\n }\n}\n\n";
1936 OS << "namespace {\n";
1938 // Output the operand conversion kind enum.
1939 OS << "enum OperatorConversionKind {\n";
1940 for (unsigned i = 0, e = OperandConversionKinds.size(); i != e; ++i)
1941 OS << " " << OperandConversionKinds[i] << ",\n";
1942 OS << " CVT_NUM_CONVERTERS\n";
1945 // Output the instruction conversion kind enum.
1946 OS << "enum InstructionConversionKind {\n";
1947 for (SetVector<std::string>::const_iterator
1948 i = InstructionConversionKinds.begin(),
1949 e = InstructionConversionKinds.end(); i != e; ++i)
1950 OS << " " << *i << ",\n";
1951 OS << " CVT_NUM_SIGNATURES\n";
1955 OS << "} // end anonymous namespace\n\n";
1957 // Output the conversion table.
1958 OS << "static const uint8_t ConversionTable[CVT_NUM_SIGNATURES]["
1959 << MaxRowLength << "] = {\n";
1961 for (unsigned Row = 0, ERow = ConversionTable.size(); Row != ERow; ++Row) {
1962 assert(ConversionTable[Row].size() % 2 == 0 && "bad conversion row!");
1963 OS << " // " << InstructionConversionKinds[Row] << "\n";
1965 for (unsigned i = 0, e = ConversionTable[Row].size(); i != e; i += 2)
1966 OS << OperandConversionKinds[ConversionTable[Row][i]] << ", "
1967 << (unsigned)(ConversionTable[Row][i + 1]) << ", ";
1968 OS << "CVT_Done },\n";
1973 // Spit out the conversion driver function.
1976 // Spit out the operand number lookup function.
1980 /// emitMatchClassEnumeration - Emit the enumeration for match class kinds.
1981 static void emitMatchClassEnumeration(CodeGenTarget &Target,
1982 std::forward_list<ClassInfo> &Infos,
1984 OS << "namespace {\n\n";
1986 OS << "/// MatchClassKind - The kinds of classes which participate in\n"
1987 << "/// instruction matching.\n";
1988 OS << "enum MatchClassKind {\n";
1989 OS << " InvalidMatchClass = 0,\n";
1990 for (const auto &CI : Infos) {
1991 OS << " " << CI.Name << ", // ";
1992 if (CI.Kind == ClassInfo::Token) {
1993 OS << "'" << CI.ValueName << "'\n";
1994 } else if (CI.isRegisterClass()) {
1995 if (!CI.ValueName.empty())
1996 OS << "register class '" << CI.ValueName << "'\n";
1998 OS << "derived register class\n";
2000 OS << "user defined class '" << CI.ValueName << "'\n";
2003 OS << " NumMatchClassKinds\n";
2009 /// emitValidateOperandClass - Emit the function to validate an operand class.
2010 static void emitValidateOperandClass(AsmMatcherInfo &Info,
2012 OS << "static unsigned validateOperandClass(MCParsedAsmOperand &GOp, "
2013 << "MatchClassKind Kind) {\n";
2014 OS << " " << Info.Target.getName() << "Operand &Operand = ("
2015 << Info.Target.getName() << "Operand&)GOp;\n";
2017 // The InvalidMatchClass is not to match any operand.
2018 OS << " if (Kind == InvalidMatchClass)\n";
2019 OS << " return MCTargetAsmParser::Match_InvalidOperand;\n\n";
2021 // Check for Token operands first.
2022 // FIXME: Use a more specific diagnostic type.
2023 OS << " if (Operand.isToken())\n";
2024 OS << " return isSubclass(matchTokenString(Operand.getToken()), Kind) ?\n"
2025 << " MCTargetAsmParser::Match_Success :\n"
2026 << " MCTargetAsmParser::Match_InvalidOperand;\n\n";
2028 // Check the user classes. We don't care what order since we're only
2029 // actually matching against one of them.
2030 for (const auto &CI : Info.Classes) {
2031 if (!CI.isUserClass())
2034 OS << " // '" << CI.ClassName << "' class\n";
2035 OS << " if (Kind == " << CI.Name << ") {\n";
2036 OS << " if (Operand." << CI.PredicateMethod << "())\n";
2037 OS << " return MCTargetAsmParser::Match_Success;\n";
2038 if (!CI.DiagnosticType.empty())
2039 OS << " return " << Info.Target.getName() << "AsmParser::Match_"
2040 << CI.DiagnosticType << ";\n";
2044 // Check for register operands, including sub-classes.
2045 OS << " if (Operand.isReg()) {\n";
2046 OS << " MatchClassKind OpKind;\n";
2047 OS << " switch (Operand.getReg()) {\n";
2048 OS << " default: OpKind = InvalidMatchClass; break;\n";
2049 for (const auto &RC : Info.RegisterClasses)
2050 OS << " case " << Info.Target.getName() << "::"
2051 << RC.first->getName() << ": OpKind = " << RC.second->Name
2054 OS << " return isSubclass(OpKind, Kind) ? "
2055 << "MCTargetAsmParser::Match_Success :\n "
2056 << " MCTargetAsmParser::Match_InvalidOperand;\n }\n\n";
2058 // Generic fallthrough match failure case for operands that don't have
2059 // specialized diagnostic types.
2060 OS << " return MCTargetAsmParser::Match_InvalidOperand;\n";
2064 /// emitIsSubclass - Emit the subclass predicate function.
2065 static void emitIsSubclass(CodeGenTarget &Target,
2066 std::forward_list<ClassInfo> &Infos,
2068 OS << "/// isSubclass - Compute whether \\p A is a subclass of \\p B.\n";
2069 OS << "static bool isSubclass(MatchClassKind A, MatchClassKind B) {\n";
2070 OS << " if (A == B)\n";
2071 OS << " return true;\n\n";
2074 raw_string_ostream SS(OStr);
2076 SS << " switch (A) {\n";
2077 SS << " default:\n";
2078 SS << " return false;\n";
2079 for (const auto &A : Infos) {
2080 std::vector<StringRef> SuperClasses;
2081 for (const auto &B : Infos) {
2082 if (&A != &B && A.isSubsetOf(B))
2083 SuperClasses.push_back(B.Name);
2086 if (SuperClasses.empty())
2090 SS << "\n case " << A.Name << ":\n";
2092 if (SuperClasses.size() == 1) {
2093 SS << " return B == " << SuperClasses.back().str() << ";\n";
2097 if (!SuperClasses.empty()) {
2098 SS << " switch (B) {\n";
2099 SS << " default: return false;\n";
2100 for (unsigned i = 0, e = SuperClasses.size(); i != e; ++i)
2101 SS << " case " << SuperClasses[i].str() << ": return true;\n";
2104 // No case statement to emit
2105 SS << " return false;\n";
2110 // If there were case statements emitted into the string stream, write them
2111 // to the output stream, otherwise write the default.
2115 OS << " return false;\n";
2120 /// emitMatchTokenString - Emit the function to match a token string to the
2121 /// appropriate match class value.
2122 static void emitMatchTokenString(CodeGenTarget &Target,
2123 std::forward_list<ClassInfo> &Infos,
2125 // Construct the match list.
2126 std::vector<StringMatcher::StringPair> Matches;
2127 for (const auto &CI : Infos) {
2128 if (CI.Kind == ClassInfo::Token)
2129 Matches.push_back(StringMatcher::StringPair(CI.ValueName,
2130 "return " + CI.Name + ";"));
2133 OS << "static MatchClassKind matchTokenString(StringRef Name) {\n";
2135 StringMatcher("Name", Matches, OS).Emit();
2137 OS << " return InvalidMatchClass;\n";
2141 /// emitMatchRegisterName - Emit the function to match a string to the target
2142 /// specific register enum.
2143 static void emitMatchRegisterName(CodeGenTarget &Target, Record *AsmParser,
2145 // Construct the match list.
2146 std::vector<StringMatcher::StringPair> Matches;
2147 const std::vector<CodeGenRegister*> &Regs =
2148 Target.getRegBank().getRegisters();
2149 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
2150 const CodeGenRegister *Reg = Regs[i];
2151 if (Reg->TheDef->getValueAsString("AsmName").empty())
2154 Matches.push_back(StringMatcher::StringPair(
2155 Reg->TheDef->getValueAsString("AsmName"),
2156 "return " + utostr(Reg->EnumValue) + ";"));
2159 OS << "static unsigned MatchRegisterName(StringRef Name) {\n";
2161 StringMatcher("Name", Matches, OS).Emit();
2163 OS << " return 0;\n";
2167 static const char *getMinimalTypeForRange(uint64_t Range) {
2168 assert(Range <= 0xFFFFFFFFFFFFFFFFULL && "Enum too large");
2169 if (Range > 0xFFFFFFFFULL)
2178 static const char *getMinimalRequiredFeaturesType(const AsmMatcherInfo &Info) {
2179 uint64_t MaxIndex = Info.SubtargetFeatures.size();
2182 return getMinimalTypeForRange(1ULL << MaxIndex);
2185 /// emitSubtargetFeatureFlagEnumeration - Emit the subtarget feature flag
2187 static void emitSubtargetFeatureFlagEnumeration(AsmMatcherInfo &Info,
2189 OS << "// Flags for subtarget features that participate in "
2190 << "instruction matching.\n";
2191 OS << "enum SubtargetFeatureFlag : " << getMinimalRequiredFeaturesType(Info)
2193 for (const auto &SF : Info.SubtargetFeatures) {
2194 SubtargetFeatureInfo &SFI = *SF.second;
2195 OS << " " << SFI.getEnumName() << " = (1ULL << " << SFI.Index << "),\n";
2197 OS << " Feature_None = 0\n";
2201 /// emitOperandDiagnosticTypes - Emit the operand matching diagnostic types.
2202 static void emitOperandDiagnosticTypes(AsmMatcherInfo &Info, raw_ostream &OS) {
2203 // Get the set of diagnostic types from all of the operand classes.
2204 std::set<StringRef> Types;
2205 for (std::map<Record*, ClassInfo*>::const_iterator
2206 I = Info.AsmOperandClasses.begin(),
2207 E = Info.AsmOperandClasses.end(); I != E; ++I) {
2208 if (!I->second->DiagnosticType.empty())
2209 Types.insert(I->second->DiagnosticType);
2212 if (Types.empty()) return;
2214 // Now emit the enum entries.
2215 for (std::set<StringRef>::const_iterator I = Types.begin(), E = Types.end();
2217 OS << " Match_" << *I << ",\n";
2218 OS << " END_OPERAND_DIAGNOSTIC_TYPES\n";
2221 /// emitGetSubtargetFeatureName - Emit the helper function to get the
2222 /// user-level name for a subtarget feature.
2223 static void emitGetSubtargetFeatureName(AsmMatcherInfo &Info, raw_ostream &OS) {
2224 OS << "// User-level names for subtarget features that participate in\n"
2225 << "// instruction matching.\n"
2226 << "static const char *getSubtargetFeatureName(uint64_t Val) {\n";
2227 if (!Info.SubtargetFeatures.empty()) {
2228 OS << " switch(Val) {\n";
2229 for (const auto &SF : Info.SubtargetFeatures) {
2230 SubtargetFeatureInfo &SFI = *SF.second;
2231 // FIXME: Totally just a placeholder name to get the algorithm working.
2232 OS << " case " << SFI.getEnumName() << ": return \""
2233 << SFI.TheDef->getValueAsString("PredicateName") << "\";\n";
2235 OS << " default: return \"(unknown)\";\n";
2238 // Nothing to emit, so skip the switch
2239 OS << " return \"(unknown)\";\n";
2244 /// emitComputeAvailableFeatures - Emit the function to compute the list of
2245 /// available features given a subtarget.
2246 static void emitComputeAvailableFeatures(AsmMatcherInfo &Info,
2248 std::string ClassName =
2249 Info.AsmParser->getValueAsString("AsmParserClassName");
2251 OS << "uint64_t " << Info.Target.getName() << ClassName << "::\n"
2252 << "ComputeAvailableFeatures(uint64_t FB) const {\n";
2253 OS << " uint64_t Features = 0;\n";
2254 for (const auto &SF : Info.SubtargetFeatures) {
2255 SubtargetFeatureInfo &SFI = *SF.second;
2258 std::string CondStorage =
2259 SFI.TheDef->getValueAsString("AssemblerCondString");
2260 StringRef Conds = CondStorage;
2261 std::pair<StringRef,StringRef> Comma = Conds.split(',');
2268 StringRef Cond = Comma.first;
2269 if (Cond[0] == '!') {
2271 Cond = Cond.substr(1);
2274 OS << "((FB & " << Info.Target.getName() << "::" << Cond << ")";
2281 if (Comma.second.empty())
2285 Comma = Comma.second.split(',');
2289 OS << " Features |= " << SFI.getEnumName() << ";\n";
2291 OS << " return Features;\n";
2295 static std::string GetAliasRequiredFeatures(Record *R,
2296 const AsmMatcherInfo &Info) {
2297 std::vector<Record*> ReqFeatures = R->getValueAsListOfDefs("Predicates");
2299 unsigned NumFeatures = 0;
2300 for (unsigned i = 0, e = ReqFeatures.size(); i != e; ++i) {
2301 SubtargetFeatureInfo *F = Info.getSubtargetFeature(ReqFeatures[i]);
2304 PrintFatalError(R->getLoc(), "Predicate '" + ReqFeatures[i]->getName() +
2305 "' is not marked as an AssemblerPredicate!");
2310 Result += F->getEnumName();
2314 if (NumFeatures > 1)
2315 Result = '(' + Result + ')';
2319 static void emitMnemonicAliasVariant(raw_ostream &OS,const AsmMatcherInfo &Info,
2320 std::vector<Record*> &Aliases,
2321 unsigned Indent = 0,
2322 StringRef AsmParserVariantName = StringRef()){
2323 // Keep track of all the aliases from a mnemonic. Use an std::map so that the
2324 // iteration order of the map is stable.
2325 std::map<std::string, std::vector<Record*> > AliasesFromMnemonic;
2327 for (unsigned i = 0, e = Aliases.size(); i != e; ++i) {
2328 Record *R = Aliases[i];
2329 // FIXME: Allow AssemblerVariantName to be a comma separated list.
2330 std::string AsmVariantName = R->getValueAsString("AsmVariantName");
2331 if (AsmVariantName != AsmParserVariantName)
2333 AliasesFromMnemonic[R->getValueAsString("FromMnemonic")].push_back(R);
2335 if (AliasesFromMnemonic.empty())
2338 // Process each alias a "from" mnemonic at a time, building the code executed
2339 // by the string remapper.
2340 std::vector<StringMatcher::StringPair> Cases;
2341 for (std::map<std::string, std::vector<Record*> >::iterator
2342 I = AliasesFromMnemonic.begin(), E = AliasesFromMnemonic.end();
2344 const std::vector<Record*> &ToVec = I->second;
2346 // Loop through each alias and emit code that handles each case. If there
2347 // are two instructions without predicates, emit an error. If there is one,
2349 std::string MatchCode;
2350 int AliasWithNoPredicate = -1;
2352 for (unsigned i = 0, e = ToVec.size(); i != e; ++i) {
2353 Record *R = ToVec[i];
2354 std::string FeatureMask = GetAliasRequiredFeatures(R, Info);
2356 // If this unconditionally matches, remember it for later and diagnose
2358 if (FeatureMask.empty()) {
2359 if (AliasWithNoPredicate != -1) {
2360 // We can't have two aliases from the same mnemonic with no predicate.
2361 PrintError(ToVec[AliasWithNoPredicate]->getLoc(),
2362 "two MnemonicAliases with the same 'from' mnemonic!");
2363 PrintFatalError(R->getLoc(), "this is the other MnemonicAlias.");
2366 AliasWithNoPredicate = i;
2369 if (R->getValueAsString("ToMnemonic") == I->first)
2370 PrintFatalError(R->getLoc(), "MnemonicAlias to the same string");
2372 if (!MatchCode.empty())
2373 MatchCode += "else ";
2374 MatchCode += "if ((Features & " + FeatureMask + ") == "+FeatureMask+")\n";
2375 MatchCode += " Mnemonic = \"" +R->getValueAsString("ToMnemonic")+"\";\n";
2378 if (AliasWithNoPredicate != -1) {
2379 Record *R = ToVec[AliasWithNoPredicate];
2380 if (!MatchCode.empty())
2381 MatchCode += "else\n ";
2382 MatchCode += "Mnemonic = \"" + R->getValueAsString("ToMnemonic")+"\";\n";
2385 MatchCode += "return;";
2387 Cases.push_back(std::make_pair(I->first, MatchCode));
2389 StringMatcher("Mnemonic", Cases, OS).Emit(Indent);
2392 /// emitMnemonicAliases - If the target has any MnemonicAlias<> definitions,
2393 /// emit a function for them and return true, otherwise return false.
2394 static bool emitMnemonicAliases(raw_ostream &OS, const AsmMatcherInfo &Info,
2395 CodeGenTarget &Target) {
2396 // Ignore aliases when match-prefix is set.
2397 if (!MatchPrefix.empty())
2400 std::vector<Record*> Aliases =
2401 Info.getRecords().getAllDerivedDefinitions("MnemonicAlias");
2402 if (Aliases.empty()) return false;
2404 OS << "static void applyMnemonicAliases(StringRef &Mnemonic, "
2405 "uint64_t Features, unsigned VariantID) {\n";
2406 OS << " switch (VariantID) {\n";
2407 unsigned VariantCount = Target.getAsmParserVariantCount();
2408 for (unsigned VC = 0; VC != VariantCount; ++VC) {
2409 Record *AsmVariant = Target.getAsmParserVariant(VC);
2410 int AsmParserVariantNo = AsmVariant->getValueAsInt("Variant");
2411 std::string AsmParserVariantName = AsmVariant->getValueAsString("Name");
2412 OS << " case " << AsmParserVariantNo << ":\n";
2413 emitMnemonicAliasVariant(OS, Info, Aliases, /*Indent=*/2,
2414 AsmParserVariantName);
2419 // Emit aliases that apply to all variants.
2420 emitMnemonicAliasVariant(OS, Info, Aliases);
2427 static void emitCustomOperandParsing(raw_ostream &OS, CodeGenTarget &Target,
2428 const AsmMatcherInfo &Info, StringRef ClassName,
2429 StringToOffsetTable &StringTable,
2430 unsigned MaxMnemonicIndex) {
2431 unsigned MaxMask = 0;
2432 for (std::vector<OperandMatchEntry>::const_iterator it =
2433 Info.OperandMatchInfo.begin(), ie = Info.OperandMatchInfo.end();
2435 MaxMask |= it->OperandMask;
2438 // Emit the static custom operand parsing table;
2439 OS << "namespace {\n";
2440 OS << " struct OperandMatchEntry {\n";
2441 OS << " " << getMinimalRequiredFeaturesType(Info)
2442 << " RequiredFeatures;\n";
2443 OS << " " << getMinimalTypeForRange(MaxMnemonicIndex)
2445 OS << " " << getMinimalTypeForRange(std::distance(
2446 Info.Classes.begin(), Info.Classes.end())) << " Class;\n";
2447 OS << " " << getMinimalTypeForRange(MaxMask)
2448 << " OperandMask;\n\n";
2449 OS << " StringRef getMnemonic() const {\n";
2450 OS << " return StringRef(MnemonicTable + Mnemonic + 1,\n";
2451 OS << " MnemonicTable[Mnemonic]);\n";
2455 OS << " // Predicate for searching for an opcode.\n";
2456 OS << " struct LessOpcodeOperand {\n";
2457 OS << " bool operator()(const OperandMatchEntry &LHS, StringRef RHS) {\n";
2458 OS << " return LHS.getMnemonic() < RHS;\n";
2460 OS << " bool operator()(StringRef LHS, const OperandMatchEntry &RHS) {\n";
2461 OS << " return LHS < RHS.getMnemonic();\n";
2463 OS << " bool operator()(const OperandMatchEntry &LHS,";
2464 OS << " const OperandMatchEntry &RHS) {\n";
2465 OS << " return LHS.getMnemonic() < RHS.getMnemonic();\n";
2469 OS << "} // end anonymous namespace.\n\n";
2471 OS << "static const OperandMatchEntry OperandMatchTable["
2472 << Info.OperandMatchInfo.size() << "] = {\n";
2474 OS << " /* Operand List Mask, Mnemonic, Operand Class, Features */\n";
2475 for (std::vector<OperandMatchEntry>::const_iterator it =
2476 Info.OperandMatchInfo.begin(), ie = Info.OperandMatchInfo.end();
2478 const OperandMatchEntry &OMI = *it;
2479 const MatchableInfo &II = *OMI.MI;
2483 // Write the required features mask.
2484 if (!II.RequiredFeatures.empty()) {
2485 for (unsigned i = 0, e = II.RequiredFeatures.size(); i != e; ++i) {
2487 OS << II.RequiredFeatures[i]->getEnumName();
2492 // Store a pascal-style length byte in the mnemonic.
2493 std::string LenMnemonic = char(II.Mnemonic.size()) + II.Mnemonic.str();
2494 OS << ", " << StringTable.GetOrAddStringOffset(LenMnemonic, false)
2495 << " /* " << II.Mnemonic << " */, ";
2499 OS << ", " << OMI.OperandMask;
2501 bool printComma = false;
2502 for (int i = 0, e = 31; i !=e; ++i)
2503 if (OMI.OperandMask & (1 << i)) {
2515 // Emit the operand class switch to call the correct custom parser for
2516 // the found operand class.
2517 OS << Target.getName() << ClassName << "::OperandMatchResultTy "
2518 << Target.getName() << ClassName << "::\n"
2519 << "tryCustomParseOperand(OperandVector"
2520 << " &Operands,\n unsigned MCK) {\n\n"
2521 << " switch(MCK) {\n";
2523 for (const auto &CI : Info.Classes) {
2524 if (CI.ParserMethod.empty())
2526 OS << " case " << CI.Name << ":\n"
2527 << " return " << CI.ParserMethod << "(Operands);\n";
2530 OS << " default:\n";
2531 OS << " return MatchOperand_NoMatch;\n";
2533 OS << " return MatchOperand_NoMatch;\n";
2536 // Emit the static custom operand parser. This code is very similar with
2537 // the other matcher. Also use MatchResultTy here just in case we go for
2538 // a better error handling.
2539 OS << Target.getName() << ClassName << "::OperandMatchResultTy "
2540 << Target.getName() << ClassName << "::\n"
2541 << "MatchOperandParserImpl(OperandVector"
2542 << " &Operands,\n StringRef Mnemonic) {\n";
2544 // Emit code to get the available features.
2545 OS << " // Get the current feature set.\n";
2546 OS << " uint64_t AvailableFeatures = getAvailableFeatures();\n\n";
2548 OS << " // Get the next operand index.\n";
2549 OS << " unsigned NextOpNum = Operands.size()-1;\n";
2551 // Emit code to search the table.
2552 OS << " // Search the table.\n";
2553 OS << " std::pair<const OperandMatchEntry*, const OperandMatchEntry*>";
2554 OS << " MnemonicRange =\n";
2555 OS << " std::equal_range(OperandMatchTable, OperandMatchTable+"
2556 << Info.OperandMatchInfo.size() << ", Mnemonic,\n"
2557 << " LessOpcodeOperand());\n\n";
2559 OS << " if (MnemonicRange.first == MnemonicRange.second)\n";
2560 OS << " return MatchOperand_NoMatch;\n\n";
2562 OS << " for (const OperandMatchEntry *it = MnemonicRange.first,\n"
2563 << " *ie = MnemonicRange.second; it != ie; ++it) {\n";
2565 OS << " // equal_range guarantees that instruction mnemonic matches.\n";
2566 OS << " assert(Mnemonic == it->getMnemonic());\n\n";
2568 // Emit check that the required features are available.
2569 OS << " // check if the available features match\n";
2570 OS << " if ((AvailableFeatures & it->RequiredFeatures) "
2571 << "!= it->RequiredFeatures) {\n";
2572 OS << " continue;\n";
2575 // Emit check to ensure the operand number matches.
2576 OS << " // check if the operand in question has a custom parser.\n";
2577 OS << " if (!(it->OperandMask & (1 << NextOpNum)))\n";
2578 OS << " continue;\n\n";
2580 // Emit call to the custom parser method
2581 OS << " // call custom parse method to handle the operand\n";
2582 OS << " OperandMatchResultTy Result = ";
2583 OS << "tryCustomParseOperand(Operands, it->Class);\n";
2584 OS << " if (Result != MatchOperand_NoMatch)\n";
2585 OS << " return Result;\n";
2588 OS << " // Okay, we had no match.\n";
2589 OS << " return MatchOperand_NoMatch;\n";
2593 void AsmMatcherEmitter::run(raw_ostream &OS) {
2594 CodeGenTarget Target(Records);
2595 Record *AsmParser = Target.getAsmParser();
2596 std::string ClassName = AsmParser->getValueAsString("AsmParserClassName");
2598 // Compute the information on the instructions to match.
2599 AsmMatcherInfo Info(AsmParser, Target, Records);
2602 // Sort the instruction table using the partial order on classes. We use
2603 // stable_sort to ensure that ambiguous instructions are still
2604 // deterministically ordered.
2605 std::stable_sort(Info.Matchables.begin(), Info.Matchables.end(),
2606 [](const std::unique_ptr<MatchableInfo> &a,
2607 const std::unique_ptr<MatchableInfo> &b){
2610 DEBUG_WITH_TYPE("instruction_info", {
2611 for (const auto &MI : Info.Matchables)
2615 // Check for ambiguous matchables.
2616 DEBUG_WITH_TYPE("ambiguous_instrs", {
2617 unsigned NumAmbiguous = 0;
2618 for (unsigned i = 0, e = Info.Matchables.size(); i != e; ++i) {
2619 for (unsigned j = i + 1; j != e; ++j) {
2620 const MatchableInfo &A = *Info.Matchables[i];
2621 const MatchableInfo &B = *Info.Matchables[j];
2623 if (A.couldMatchAmbiguouslyWith(B)) {
2624 errs() << "warning: ambiguous matchables:\n";
2626 errs() << "\nis incomparable with:\n";
2634 errs() << "warning: " << NumAmbiguous
2635 << " ambiguous matchables!\n";
2638 // Compute the information on the custom operand parsing.
2639 Info.buildOperandMatchInfo();
2641 // Write the output.
2643 // Information for the class declaration.
2644 OS << "\n#ifdef GET_ASSEMBLER_HEADER\n";
2645 OS << "#undef GET_ASSEMBLER_HEADER\n";
2646 OS << " // This should be included into the middle of the declaration of\n";
2647 OS << " // your subclasses implementation of MCTargetAsmParser.\n";
2648 OS << " uint64_t ComputeAvailableFeatures(uint64_t FeatureBits) const;\n";
2649 OS << " void convertToMCInst(unsigned Kind, MCInst &Inst, "
2650 << "unsigned Opcode,\n"
2651 << " const OperandVector "
2653 OS << " void convertToMapAndConstraints(unsigned Kind,\n ";
2654 OS << " const OperandVector &Operands) override;\n";
2655 OS << " bool mnemonicIsValid(StringRef Mnemonic, unsigned VariantID) override;\n";
2656 OS << " unsigned MatchInstructionImpl(\n";
2658 OS << "const OperandVector &Operands,\n"
2659 << " MCInst &Inst,\n"
2660 << " uint64_t &ErrorInfo,"
2661 << " bool matchingInlineAsm,\n"
2662 << " unsigned VariantID = 0);\n";
2664 if (Info.OperandMatchInfo.size()) {
2665 OS << "\n enum OperandMatchResultTy {\n";
2666 OS << " MatchOperand_Success, // operand matched successfully\n";
2667 OS << " MatchOperand_NoMatch, // operand did not match\n";
2668 OS << " MatchOperand_ParseFail // operand matched but had errors\n";
2670 OS << " OperandMatchResultTy MatchOperandParserImpl(\n";
2671 OS << " OperandVector &Operands,\n";
2672 OS << " StringRef Mnemonic);\n";
2674 OS << " OperandMatchResultTy tryCustomParseOperand(\n";
2675 OS << " OperandVector &Operands,\n";
2676 OS << " unsigned MCK);\n\n";
2679 OS << "#endif // GET_ASSEMBLER_HEADER_INFO\n\n";
2681 // Emit the operand match diagnostic enum names.
2682 OS << "\n#ifdef GET_OPERAND_DIAGNOSTIC_TYPES\n";
2683 OS << "#undef GET_OPERAND_DIAGNOSTIC_TYPES\n\n";
2684 emitOperandDiagnosticTypes(Info, OS);
2685 OS << "#endif // GET_OPERAND_DIAGNOSTIC_TYPES\n\n";
2688 OS << "\n#ifdef GET_REGISTER_MATCHER\n";
2689 OS << "#undef GET_REGISTER_MATCHER\n\n";
2691 // Emit the subtarget feature enumeration.
2692 emitSubtargetFeatureFlagEnumeration(Info, OS);
2694 // Emit the function to match a register name to number.
2695 // This should be omitted for Mips target
2696 if (AsmParser->getValueAsBit("ShouldEmitMatchRegisterName"))
2697 emitMatchRegisterName(Target, AsmParser, OS);
2699 OS << "#endif // GET_REGISTER_MATCHER\n\n";
2701 OS << "\n#ifdef GET_SUBTARGET_FEATURE_NAME\n";
2702 OS << "#undef GET_SUBTARGET_FEATURE_NAME\n\n";
2704 // Generate the helper function to get the names for subtarget features.
2705 emitGetSubtargetFeatureName(Info, OS);
2707 OS << "#endif // GET_SUBTARGET_FEATURE_NAME\n\n";
2709 OS << "\n#ifdef GET_MATCHER_IMPLEMENTATION\n";
2710 OS << "#undef GET_MATCHER_IMPLEMENTATION\n\n";
2712 // Generate the function that remaps for mnemonic aliases.
2713 bool HasMnemonicAliases = emitMnemonicAliases(OS, Info, Target);
2715 // Generate the convertToMCInst function to convert operands into an MCInst.
2716 // Also, generate the convertToMapAndConstraints function for MS-style inline
2717 // assembly. The latter doesn't actually generate a MCInst.
2718 emitConvertFuncs(Target, ClassName, Info.Matchables, OS);
2720 // Emit the enumeration for classes which participate in matching.
2721 emitMatchClassEnumeration(Target, Info.Classes, OS);
2723 // Emit the routine to match token strings to their match class.
2724 emitMatchTokenString(Target, Info.Classes, OS);
2726 // Emit the subclass predicate routine.
2727 emitIsSubclass(Target, Info.Classes, OS);
2729 // Emit the routine to validate an operand against a match class.
2730 emitValidateOperandClass(Info, OS);
2732 // Emit the available features compute function.
2733 emitComputeAvailableFeatures(Info, OS);
2736 StringToOffsetTable StringTable;
2738 size_t MaxNumOperands = 0;
2739 unsigned MaxMnemonicIndex = 0;
2740 bool HasDeprecation = false;
2741 for (const auto &MI : Info.Matchables) {
2742 MaxNumOperands = std::max(MaxNumOperands, MI->AsmOperands.size());
2743 HasDeprecation |= MI->HasDeprecation;
2745 // Store a pascal-style length byte in the mnemonic.
2746 std::string LenMnemonic = char(MI->Mnemonic.size()) + MI->Mnemonic.str();
2747 MaxMnemonicIndex = std::max(MaxMnemonicIndex,
2748 StringTable.GetOrAddStringOffset(LenMnemonic, false));
2751 OS << "static const char *const MnemonicTable =\n";
2752 StringTable.EmitString(OS);
2755 // Emit the static match table; unused classes get initalized to 0 which is
2756 // guaranteed to be InvalidMatchClass.
2758 // FIXME: We can reduce the size of this table very easily. First, we change
2759 // it so that store the kinds in separate bit-fields for each index, which
2760 // only needs to be the max width used for classes at that index (we also need
2761 // to reject based on this during classification). If we then make sure to
2762 // order the match kinds appropriately (putting mnemonics last), then we
2763 // should only end up using a few bits for each class, especially the ones
2764 // following the mnemonic.
2765 OS << "namespace {\n";
2766 OS << " struct MatchEntry {\n";
2767 OS << " " << getMinimalTypeForRange(MaxMnemonicIndex)
2769 OS << " uint16_t Opcode;\n";
2770 OS << " " << getMinimalTypeForRange(Info.Matchables.size())
2772 OS << " " << getMinimalRequiredFeaturesType(Info)
2773 << " RequiredFeatures;\n";
2774 OS << " " << getMinimalTypeForRange(
2775 std::distance(Info.Classes.begin(), Info.Classes.end()))
2776 << " Classes[" << MaxNumOperands << "];\n";
2777 OS << " StringRef getMnemonic() const {\n";
2778 OS << " return StringRef(MnemonicTable + Mnemonic + 1,\n";
2779 OS << " MnemonicTable[Mnemonic]);\n";
2783 OS << " // Predicate for searching for an opcode.\n";
2784 OS << " struct LessOpcode {\n";
2785 OS << " bool operator()(const MatchEntry &LHS, StringRef RHS) {\n";
2786 OS << " return LHS.getMnemonic() < RHS;\n";
2788 OS << " bool operator()(StringRef LHS, const MatchEntry &RHS) {\n";
2789 OS << " return LHS < RHS.getMnemonic();\n";
2791 OS << " bool operator()(const MatchEntry &LHS, const MatchEntry &RHS) {\n";
2792 OS << " return LHS.getMnemonic() < RHS.getMnemonic();\n";
2796 OS << "} // end anonymous namespace.\n\n";
2798 unsigned VariantCount = Target.getAsmParserVariantCount();
2799 for (unsigned VC = 0; VC != VariantCount; ++VC) {
2800 Record *AsmVariant = Target.getAsmParserVariant(VC);
2801 int AsmVariantNo = AsmVariant->getValueAsInt("Variant");
2803 OS << "static const MatchEntry MatchTable" << VC << "[] = {\n";
2805 for (const auto &MI : Info.Matchables) {
2806 if (MI->AsmVariantID != AsmVariantNo)
2809 // Store a pascal-style length byte in the mnemonic.
2810 std::string LenMnemonic = char(MI->Mnemonic.size()) + MI->Mnemonic.str();
2811 OS << " { " << StringTable.GetOrAddStringOffset(LenMnemonic, false)
2812 << " /* " << MI->Mnemonic << " */, "
2813 << Target.getName() << "::"
2814 << MI->getResultInst()->TheDef->getName() << ", "
2815 << MI->ConversionFnKind << ", ";
2817 // Write the required features mask.
2818 if (!MI->RequiredFeatures.empty()) {
2819 for (unsigned i = 0, e = MI->RequiredFeatures.size(); i != e; ++i) {
2821 OS << MI->RequiredFeatures[i]->getEnumName();
2827 for (unsigned i = 0, e = MI->AsmOperands.size(); i != e; ++i) {
2828 const MatchableInfo::AsmOperand &Op = MI->AsmOperands[i];
2831 OS << Op.Class->Name;
2839 // A method to determine if a mnemonic is in the list.
2840 OS << "bool " << Target.getName() << ClassName << "::\n"
2841 << "mnemonicIsValid(StringRef Mnemonic, unsigned VariantID) {\n";
2842 OS << " // Find the appropriate table for this asm variant.\n";
2843 OS << " const MatchEntry *Start, *End;\n";
2844 OS << " switch (VariantID) {\n";
2845 OS << " default: // unreachable\n";
2846 for (unsigned VC = 0; VC != VariantCount; ++VC) {
2847 Record *AsmVariant = Target.getAsmParserVariant(VC);
2848 int AsmVariantNo = AsmVariant->getValueAsInt("Variant");
2849 OS << " case " << AsmVariantNo << ": Start = std::begin(MatchTable" << VC
2850 << "); End = std::end(MatchTable" << VC << "); break;\n";
2853 OS << " // Search the table.\n";
2854 OS << " std::pair<const MatchEntry*, const MatchEntry*> MnemonicRange =\n";
2855 OS << " std::equal_range(Start, End, Mnemonic, LessOpcode());\n";
2856 OS << " return MnemonicRange.first != MnemonicRange.second;\n";
2859 // Finally, build the match function.
2860 OS << "unsigned " << Target.getName() << ClassName << "::\n"
2861 << "MatchInstructionImpl(const OperandVector"
2863 OS << " MCInst &Inst,\n"
2864 << "uint64_t &ErrorInfo, bool matchingInlineAsm, unsigned VariantID) {\n";
2866 OS << " // Eliminate obvious mismatches.\n";
2867 OS << " if (Operands.size() > " << (MaxNumOperands+1) << ") {\n";
2868 OS << " ErrorInfo = " << (MaxNumOperands+1) << ";\n";
2869 OS << " return Match_InvalidOperand;\n";
2872 // Emit code to get the available features.
2873 OS << " // Get the current feature set.\n";
2874 OS << " uint64_t AvailableFeatures = getAvailableFeatures();\n\n";
2876 OS << " // Get the instruction mnemonic, which is the first token.\n";
2877 OS << " StringRef Mnemonic = ((" << Target.getName()
2878 << "Operand&)*Operands[0]).getToken();\n\n";
2880 if (HasMnemonicAliases) {
2881 OS << " // Process all MnemonicAliases to remap the mnemonic.\n";
2882 OS << " applyMnemonicAliases(Mnemonic, AvailableFeatures, VariantID);\n\n";
2885 // Emit code to compute the class list for this operand vector.
2886 OS << " // Some state to try to produce better error messages.\n";
2887 OS << " bool HadMatchOtherThanFeatures = false;\n";
2888 OS << " bool HadMatchOtherThanPredicate = false;\n";
2889 OS << " unsigned RetCode = Match_InvalidOperand;\n";
2890 OS << " uint64_t MissingFeatures = ~0ULL;\n";
2891 OS << " // Set ErrorInfo to the operand that mismatches if it is\n";
2892 OS << " // wrong for all instances of the instruction.\n";
2893 OS << " ErrorInfo = ~0U;\n";
2895 // Emit code to search the table.
2896 OS << " // Find the appropriate table for this asm variant.\n";
2897 OS << " const MatchEntry *Start, *End;\n";
2898 OS << " switch (VariantID) {\n";
2899 OS << " default: // unreachable\n";
2900 for (unsigned VC = 0; VC != VariantCount; ++VC) {
2901 Record *AsmVariant = Target.getAsmParserVariant(VC);
2902 int AsmVariantNo = AsmVariant->getValueAsInt("Variant");
2903 OS << " case " << AsmVariantNo << ": Start = std::begin(MatchTable" << VC
2904 << "); End = std::end(MatchTable" << VC << "); break;\n";
2907 OS << " // Search the table.\n";
2908 OS << " std::pair<const MatchEntry*, const MatchEntry*> MnemonicRange =\n";
2909 OS << " std::equal_range(Start, End, Mnemonic, LessOpcode());\n\n";
2911 OS << " // Return a more specific error code if no mnemonics match.\n";
2912 OS << " if (MnemonicRange.first == MnemonicRange.second)\n";
2913 OS << " return Match_MnemonicFail;\n\n";
2915 OS << " for (const MatchEntry *it = MnemonicRange.first, "
2916 << "*ie = MnemonicRange.second;\n";
2917 OS << " it != ie; ++it) {\n";
2919 OS << " // equal_range guarantees that instruction mnemonic matches.\n";
2920 OS << " assert(Mnemonic == it->getMnemonic());\n";
2922 // Emit check that the subclasses match.
2923 OS << " bool OperandsValid = true;\n";
2924 OS << " for (unsigned i = 0; i != " << MaxNumOperands << "; ++i) {\n";
2925 OS << " if (i + 1 >= Operands.size()) {\n";
2926 OS << " OperandsValid = (it->Classes[i] == " <<"InvalidMatchClass);\n";
2927 OS << " if (!OperandsValid) ErrorInfo = i + 1;\n";
2930 OS << " unsigned Diag = validateOperandClass(*Operands[i+1],\n";
2932 OS << "(MatchClassKind)it->Classes[i]);\n";
2933 OS << " if (Diag == Match_Success)\n";
2934 OS << " continue;\n";
2935 OS << " // If the generic handler indicates an invalid operand\n";
2936 OS << " // failure, check for a special case.\n";
2937 OS << " if (Diag == Match_InvalidOperand) {\n";
2938 OS << " Diag = validateTargetOperandClass(*Operands[i+1],\n";
2940 OS << "(MatchClassKind)it->Classes[i]);\n";
2941 OS << " if (Diag == Match_Success)\n";
2942 OS << " continue;\n";
2944 OS << " // If this operand is broken for all of the instances of this\n";
2945 OS << " // mnemonic, keep track of it so we can report loc info.\n";
2946 OS << " // If we already had a match that only failed due to a\n";
2947 OS << " // target predicate, that diagnostic is preferred.\n";
2948 OS << " if (!HadMatchOtherThanPredicate &&\n";
2949 OS << " (it == MnemonicRange.first || ErrorInfo <= i+1)) {\n";
2950 OS << " ErrorInfo = i+1;\n";
2951 OS << " // InvalidOperand is the default. Prefer specificity.\n";
2952 OS << " if (Diag != Match_InvalidOperand)\n";
2953 OS << " RetCode = Diag;\n";
2955 OS << " // Otherwise, just reject this instance of the mnemonic.\n";
2956 OS << " OperandsValid = false;\n";
2960 OS << " if (!OperandsValid) continue;\n";
2962 // Emit check that the required features are available.
2963 OS << " if ((AvailableFeatures & it->RequiredFeatures) "
2964 << "!= it->RequiredFeatures) {\n";
2965 OS << " HadMatchOtherThanFeatures = true;\n";
2966 OS << " uint64_t NewMissingFeatures = it->RequiredFeatures & "
2967 "~AvailableFeatures;\n";
2968 OS << " if (CountPopulation_64(NewMissingFeatures) <=\n"
2969 " CountPopulation_64(MissingFeatures))\n";
2970 OS << " MissingFeatures = NewMissingFeatures;\n";
2971 OS << " continue;\n";
2974 OS << " if (matchingInlineAsm) {\n";
2975 OS << " Inst.setOpcode(it->Opcode);\n";
2976 OS << " convertToMapAndConstraints(it->ConvertFn, Operands);\n";
2977 OS << " return Match_Success;\n";
2979 OS << " // We have selected a definite instruction, convert the parsed\n"
2980 << " // operands into the appropriate MCInst.\n";
2981 OS << " convertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands);\n";
2984 // Verify the instruction with the target-specific match predicate function.
2985 OS << " // We have a potential match. Check the target predicate to\n"
2986 << " // handle any context sensitive constraints.\n"
2987 << " unsigned MatchResult;\n"
2988 << " if ((MatchResult = checkTargetMatchPredicate(Inst)) !="
2989 << " Match_Success) {\n"
2990 << " Inst.clear();\n"
2991 << " RetCode = MatchResult;\n"
2992 << " HadMatchOtherThanPredicate = true;\n"
2996 // Call the post-processing function, if used.
2997 std::string InsnCleanupFn =
2998 AsmParser->getValueAsString("AsmParserInstCleanup");
2999 if (!InsnCleanupFn.empty())
3000 OS << " " << InsnCleanupFn << "(Inst);\n";
3002 if (HasDeprecation) {
3003 OS << " std::string Info;\n";
3004 OS << " if (MII.get(Inst.getOpcode()).getDeprecatedInfo(Inst, STI, Info)) {\n";
3005 OS << " SMLoc Loc = ((" << Target.getName()
3006 << "Operand&)*Operands[0]).getStartLoc();\n";
3007 OS << " getParser().Warning(Loc, Info, None);\n";
3011 OS << " return Match_Success;\n";
3014 OS << " // Okay, we had no match. Try to return a useful error code.\n";
3015 OS << " if (HadMatchOtherThanPredicate || !HadMatchOtherThanFeatures)\n";
3016 OS << " return RetCode;\n\n";
3017 OS << " // Missing feature matches return which features were missing\n";
3018 OS << " ErrorInfo = MissingFeatures;\n";
3019 OS << " return Match_MissingFeature;\n";
3022 if (Info.OperandMatchInfo.size())
3023 emitCustomOperandParsing(OS, Target, Info, ClassName, StringTable,
3026 OS << "#endif // GET_MATCHER_IMPLEMENTATION\n\n";
3031 void EmitAsmMatcher(RecordKeeper &RK, raw_ostream &OS) {
3032 emitSourceFileHeader("Assembly Matcher Source Fragment", OS);
3033 AsmMatcherEmitter(RK).run(OS);
3036 } // End llvm namespace