1 //===- AsmMatcherEmitter.cpp - Generate an assembly matcher ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend emits a target specifier matcher for converting parsed
11 // assembly operands in the MCInst structures.
13 // The input to the target specific matcher is a list of literal tokens and
14 // operands. The target specific parser should generally eliminate any syntax
15 // which is not relevant for matching; for example, comma tokens should have
16 // already been consumed and eliminated by the parser. Most instructions will
17 // end up with a single literal token (the instruction name) and some number of
20 // Some example inputs, for X86:
21 // 'addl' (immediate ...) (register ...)
22 // 'add' (immediate ...) (memory ...)
25 // The assembly matcher is responsible for converting this input into a precise
26 // machine instruction (i.e., an instruction with a well defined encoding). This
27 // mapping has several properties which complicate matching:
29 // - It may be ambiguous; many architectures can legally encode particular
30 // variants of an instruction in different ways (for example, using a smaller
31 // encoding for small immediates). Such ambiguities should never be
32 // arbitrarily resolved by the assembler, the assembler is always responsible
33 // for choosing the "best" available instruction.
35 // - It may depend on the subtarget or the assembler context. Instructions
36 // which are invalid for the current mode, but otherwise unambiguous (e.g.,
37 // an SSE instruction in a file being assembled for i486) should be accepted
38 // and rejected by the assembler front end. However, if the proper encoding
39 // for an instruction is dependent on the assembler context then the matcher
40 // is responsible for selecting the correct machine instruction for the
43 // The core matching algorithm attempts to exploit the regularity in most
44 // instruction sets to quickly determine the set of possibly matching
45 // instructions, and the simplify the generated code. Additionally, this helps
46 // to ensure that the ambiguities are intentionally resolved by the user.
48 // The matching is divided into two distinct phases:
50 // 1. Classification: Each operand is mapped to the unique set which (a)
51 // contains it, and (b) is the largest such subset for which a single
52 // instruction could match all members.
54 // For register classes, we can generate these subgroups automatically. For
55 // arbitrary operands, we expect the user to define the classes and their
56 // relations to one another (for example, 8-bit signed immediates as a
57 // subset of 32-bit immediates).
59 // By partitioning the operands in this way, we guarantee that for any
60 // tuple of classes, any single instruction must match either all or none
61 // of the sets of operands which could classify to that tuple.
63 // In addition, the subset relation amongst classes induces a partial order
64 // on such tuples, which we use to resolve ambiguities.
66 // 2. The input can now be treated as a tuple of classes (static tokens are
67 // simple singleton sets). Each such tuple should generally map to a single
68 // instruction (we currently ignore cases where this isn't true, whee!!!),
69 // which we can emit a simple matcher for.
71 //===----------------------------------------------------------------------===//
73 #include "AsmMatcherEmitter.h"
74 #include "CodeGenTarget.h"
76 #include "StringMatcher.h"
77 #include "llvm/ADT/OwningPtr.h"
78 #include "llvm/ADT/SmallPtrSet.h"
79 #include "llvm/ADT/SmallVector.h"
80 #include "llvm/ADT/STLExtras.h"
81 #include "llvm/ADT/StringExtras.h"
82 #include "llvm/Support/CommandLine.h"
83 #include "llvm/Support/Debug.h"
89 static cl::opt<std::string>
90 MatchPrefix("match-prefix", cl::init(""),
91 cl::desc("Only match instructions with the given prefix"));
96 struct SubtargetFeatureInfo;
98 /// ClassInfo - Helper class for storing the information about a particular
99 /// class of operands which can be matched.
102 /// Invalid kind, for use as a sentinel value.
105 /// The class for a particular token.
108 /// The (first) register class, subsequent register classes are
109 /// RegisterClass0+1, and so on.
112 /// The (first) user defined class, subsequent user defined classes are
113 /// UserClass0+1, and so on.
117 /// Kind - The class kind, which is either a predefined kind, or (UserClass0 +
118 /// N) for the Nth user defined class.
121 /// SuperClasses - The super classes of this class. Note that for simplicities
122 /// sake user operands only record their immediate super class, while register
123 /// operands include all superclasses.
124 std::vector<ClassInfo*> SuperClasses;
126 /// Name - The full class name, suitable for use in an enum.
129 /// ClassName - The unadorned generic name for this class (e.g., Token).
130 std::string ClassName;
132 /// ValueName - The name of the value this class represents; for a token this
133 /// is the literal token string, for an operand it is the TableGen class (or
134 /// empty if this is a derived class).
135 std::string ValueName;
137 /// PredicateMethod - The name of the operand method to test whether the
138 /// operand matches this class; this is not valid for Token or register kinds.
139 std::string PredicateMethod;
141 /// RenderMethod - The name of the operand method to add this operand to an
142 /// MCInst; this is not valid for Token or register kinds.
143 std::string RenderMethod;
145 /// For register classes, the records for all the registers in this class.
146 std::set<Record*> Registers;
149 /// isRegisterClass() - Check if this is a register class.
150 bool isRegisterClass() const {
151 return Kind >= RegisterClass0 && Kind < UserClass0;
154 /// isUserClass() - Check if this is a user defined class.
155 bool isUserClass() const {
156 return Kind >= UserClass0;
159 /// isRelatedTo - Check whether this class is "related" to \arg RHS. Classes
160 /// are related if they are in the same class hierarchy.
161 bool isRelatedTo(const ClassInfo &RHS) const {
162 // Tokens are only related to tokens.
163 if (Kind == Token || RHS.Kind == Token)
164 return Kind == Token && RHS.Kind == Token;
166 // Registers classes are only related to registers classes, and only if
167 // their intersection is non-empty.
168 if (isRegisterClass() || RHS.isRegisterClass()) {
169 if (!isRegisterClass() || !RHS.isRegisterClass())
172 std::set<Record*> Tmp;
173 std::insert_iterator< std::set<Record*> > II(Tmp, Tmp.begin());
174 std::set_intersection(Registers.begin(), Registers.end(),
175 RHS.Registers.begin(), RHS.Registers.end(),
181 // Otherwise we have two users operands; they are related if they are in the
182 // same class hierarchy.
184 // FIXME: This is an oversimplification, they should only be related if they
185 // intersect, however we don't have that information.
186 assert(isUserClass() && RHS.isUserClass() && "Unexpected class!");
187 const ClassInfo *Root = this;
188 while (!Root->SuperClasses.empty())
189 Root = Root->SuperClasses.front();
191 const ClassInfo *RHSRoot = &RHS;
192 while (!RHSRoot->SuperClasses.empty())
193 RHSRoot = RHSRoot->SuperClasses.front();
195 return Root == RHSRoot;
198 /// isSubsetOf - Test whether this class is a subset of \arg RHS;
199 bool isSubsetOf(const ClassInfo &RHS) const {
200 // This is a subset of RHS if it is the same class...
204 // ... or if any of its super classes are a subset of RHS.
205 for (std::vector<ClassInfo*>::const_iterator it = SuperClasses.begin(),
206 ie = SuperClasses.end(); it != ie; ++it)
207 if ((*it)->isSubsetOf(RHS))
213 /// operator< - Compare two classes.
214 bool operator<(const ClassInfo &RHS) const {
218 // Unrelated classes can be ordered by kind.
219 if (!isRelatedTo(RHS))
220 return Kind < RHS.Kind;
224 assert(0 && "Invalid kind!");
226 // Tokens are comparable by value.
228 // FIXME: Compare by enum value.
229 return ValueName < RHS.ValueName;
232 // This class preceeds the RHS if it is a proper subset of the RHS.
235 if (RHS.isSubsetOf(*this))
238 // Otherwise, order by name to ensure we have a total ordering.
239 return ValueName < RHS.ValueName;
244 /// MatchableInfo - Helper class for storing the necessary information for an
245 /// instruction or alias which is capable of being matched.
246 struct MatchableInfo {
248 /// Token - This is the token that the operand came from.
251 /// The unique class instance this operand should match.
254 /// The original operand this corresponds to. This is unset for singleton
255 /// registers and tokens, because they don't have a list in the ins/outs
256 /// list. If an operand is tied ($a=$b), this refers to source operand: $b.
257 const CGIOperandList::OperandInfo *OperandInfo;
259 explicit AsmOperand(StringRef T) : Token(T), Class(0), OperandInfo(0) {}
262 /// InstrName - The target name for this instruction.
263 std::string InstrName;
265 /// TheDef - This is the definition of the instruction or InstAlias that this
266 /// matchable came from.
267 Record *const TheDef;
269 /// OperandList - This is the operand list that came from the (ins) and (outs)
270 /// list of the alias or instruction.
271 const CGIOperandList &OperandList;
273 /// AsmString - The assembly string for this instruction (with variants
274 /// removed), e.g. "movsx $src, $dst".
275 std::string AsmString;
277 /// Mnemonic - This is the first token of the matched instruction, its
281 /// AsmOperands - The textual operands that this instruction matches,
282 /// annotated with a class and where in the OperandList they were defined.
283 /// This directly corresponds to the tokenized AsmString after the mnemonic is
285 SmallVector<AsmOperand, 4> AsmOperands;
287 /// Predicates - The required subtarget features to match this instruction.
288 SmallVector<SubtargetFeatureInfo*, 4> RequiredFeatures;
290 /// ConversionFnKind - The enum value which is passed to the generated
291 /// ConvertToMCInst to convert parsed operands into an MCInst for this
293 std::string ConversionFnKind;
295 MatchableInfo(const CodeGenInstruction &CGI)
296 : TheDef(CGI.TheDef), OperandList(CGI.Operands), AsmString(CGI.AsmString) {
297 InstrName = TheDef->getName();
300 MatchableInfo(const CodeGenInstAlias *Alias)
301 : TheDef(Alias->TheDef), OperandList(Alias->Operands),
302 AsmString(Alias->AsmString) {
305 DefInit *DI = dynamic_cast<DefInit*>(Alias->Result->getOperator());
308 InstrName = DI->getDef()->getName();
311 void Initialize(const AsmMatcherInfo &Info,
312 SmallPtrSet<Record*, 16> &SingletonRegisters);
314 /// Validate - Return true if this matchable is a valid thing to match against
315 /// and perform a bunch of validity checking.
316 bool Validate(StringRef CommentDelimiter, bool Hack) const;
318 /// getSingletonRegisterForAsmOperand - If the specified token is a singleton
319 /// register, return the Record for it, otherwise return null.
320 Record *getSingletonRegisterForAsmOperand(unsigned i,
321 const AsmMatcherInfo &Info) const;
323 /// operator< - Compare two matchables.
324 bool operator<(const MatchableInfo &RHS) const {
325 // The primary comparator is the instruction mnemonic.
326 if (Mnemonic != RHS.Mnemonic)
327 return Mnemonic < RHS.Mnemonic;
329 if (AsmOperands.size() != RHS.AsmOperands.size())
330 return AsmOperands.size() < RHS.AsmOperands.size();
332 // Compare lexicographically by operand. The matcher validates that other
333 // orderings wouldn't be ambiguous using \see CouldMatchAmiguouslyWith().
334 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
335 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class)
337 if (*RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
344 /// CouldMatchAmiguouslyWith - Check whether this matchable could
345 /// ambiguously match the same set of operands as \arg RHS (without being a
346 /// strictly superior match).
347 bool CouldMatchAmiguouslyWith(const MatchableInfo &RHS) {
348 // The primary comparator is the instruction mnemonic.
349 if (Mnemonic != RHS.Mnemonic)
352 // The number of operands is unambiguous.
353 if (AsmOperands.size() != RHS.AsmOperands.size())
356 // Otherwise, make sure the ordering of the two instructions is unambiguous
357 // by checking that either (a) a token or operand kind discriminates them,
358 // or (b) the ordering among equivalent kinds is consistent.
360 // Tokens and operand kinds are unambiguous (assuming a correct target
362 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i)
363 if (AsmOperands[i].Class->Kind != RHS.AsmOperands[i].Class->Kind ||
364 AsmOperands[i].Class->Kind == ClassInfo::Token)
365 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class ||
366 *RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
369 // Otherwise, this operand could commute if all operands are equivalent, or
370 // there is a pair of operands that compare less than and a pair that
371 // compare greater than.
372 bool HasLT = false, HasGT = false;
373 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
374 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class)
376 if (*RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
380 return !(HasLT ^ HasGT);
386 void TokenizeAsmString(const AsmMatcherInfo &Info);
389 /// SubtargetFeatureInfo - Helper class for storing information on a subtarget
390 /// feature which participates in instruction matching.
391 struct SubtargetFeatureInfo {
392 /// \brief The predicate record for this feature.
395 /// \brief An unique index assigned to represent this feature.
398 SubtargetFeatureInfo(Record *D, unsigned Idx) : TheDef(D), Index(Idx) {}
400 /// \brief The name of the enumerated constant identifying this feature.
401 std::string getEnumName() const {
402 return "Feature_" + TheDef->getName();
406 class AsmMatcherInfo {
408 /// The tablegen AsmParser record.
411 /// Target - The target information.
412 CodeGenTarget &Target;
414 /// The AsmParser "RegisterPrefix" value.
415 std::string RegisterPrefix;
417 /// The classes which are needed for matching.
418 std::vector<ClassInfo*> Classes;
420 /// The information on the matchables to match.
421 std::vector<MatchableInfo*> Matchables;
423 /// Map of Register records to their class information.
424 std::map<Record*, ClassInfo*> RegisterClasses;
426 /// Map of Predicate records to their subtarget information.
427 std::map<Record*, SubtargetFeatureInfo*> SubtargetFeatures;
430 /// Map of token to class information which has already been constructed.
431 std::map<std::string, ClassInfo*> TokenClasses;
433 /// Map of RegisterClass records to their class information.
434 std::map<Record*, ClassInfo*> RegisterClassClasses;
436 /// Map of AsmOperandClass records to their class information.
437 std::map<Record*, ClassInfo*> AsmOperandClasses;
440 /// getTokenClass - Lookup or create the class for the given token.
441 ClassInfo *getTokenClass(StringRef Token);
443 /// getOperandClass - Lookup or create the class for the given operand.
444 ClassInfo *getOperandClass(StringRef Token,
445 const CGIOperandList::OperandInfo &OI);
447 /// BuildRegisterClasses - Build the ClassInfo* instances for register
449 void BuildRegisterClasses(SmallPtrSet<Record*, 16> &SingletonRegisters);
451 /// BuildOperandClasses - Build the ClassInfo* instances for user defined
453 void BuildOperandClasses();
456 AsmMatcherInfo(Record *AsmParser, CodeGenTarget &Target);
458 /// BuildInfo - Construct the various tables used during matching.
461 /// getSubtargetFeature - Lookup or create the subtarget feature info for the
463 SubtargetFeatureInfo *getSubtargetFeature(Record *Def) const {
464 assert(Def->isSubClassOf("Predicate") && "Invalid predicate type!");
465 std::map<Record*, SubtargetFeatureInfo*>::const_iterator I =
466 SubtargetFeatures.find(Def);
467 return I == SubtargetFeatures.end() ? 0 : I->second;
473 void MatchableInfo::dump() {
474 errs() << InstrName << " -- " << "flattened:\"" << AsmString << "\"\n";
476 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
477 AsmOperand &Op = AsmOperands[i];
478 errs() << " op[" << i << "] = " << Op.Class->ClassName << " - ";
479 if (Op.Class->Kind == ClassInfo::Token) {
480 errs() << '\"' << Op.Token << "\"\n";
484 if (!Op.OperandInfo) {
485 errs() << "(singleton register)\n";
489 const CGIOperandList::OperandInfo &OI = *Op.OperandInfo;
490 errs() << OI.Name << " " << OI.Rec->getName()
491 << " (" << OI.MIOperandNo << ", " << OI.MINumOperands << ")\n";
495 void MatchableInfo::Initialize(const AsmMatcherInfo &Info,
496 SmallPtrSet<Record*, 16> &SingletonRegisters) {
497 // TODO: Eventually support asmparser for Variant != 0.
498 AsmString = CodeGenInstruction::FlattenAsmStringVariants(AsmString, 0);
500 TokenizeAsmString(Info);
502 // Compute the require features.
503 std::vector<Record*> Predicates =TheDef->getValueAsListOfDefs("Predicates");
504 for (unsigned i = 0, e = Predicates.size(); i != e; ++i)
505 if (SubtargetFeatureInfo *Feature =
506 Info.getSubtargetFeature(Predicates[i]))
507 RequiredFeatures.push_back(Feature);
509 // Collect singleton registers, if used.
510 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
511 if (Record *Reg = getSingletonRegisterForAsmOperand(i, Info))
512 SingletonRegisters.insert(Reg);
516 /// TokenizeAsmString - Tokenize a simplified assembly string.
517 void MatchableInfo::TokenizeAsmString(const AsmMatcherInfo &Info) {
518 StringRef String = AsmString;
521 for (unsigned i = 0, e = String.size(); i != e; ++i) {
531 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
534 if (!isspace(String[i]) && String[i] != ',')
535 AsmOperands.push_back(AsmOperand(String.substr(i, 1)));
541 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
545 assert(i != String.size() && "Invalid quoted character");
546 AsmOperands.push_back(AsmOperand(String.substr(i, 1)));
551 // If this isn't "${", treat like a normal token.
552 if (i + 1 == String.size() || String[i + 1] != '{') {
554 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
562 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
566 StringRef::iterator End = std::find(String.begin() + i, String.end(),'}');
567 assert(End != String.end() && "Missing brace in operand reference!");
568 size_t EndPos = End - String.begin();
569 AsmOperands.push_back(AsmOperand(String.slice(i, EndPos+1)));
577 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
586 if (InTok && Prev != String.size())
587 AsmOperands.push_back(AsmOperand(String.substr(Prev)));
589 // The first token of the instruction is the mnemonic, which must be a
590 // simple string, not a $foo variable or a singleton register.
591 assert(!AsmOperands.empty() && "Instruction has no tokens?");
592 Mnemonic = AsmOperands[0].Token;
593 if (Mnemonic[0] == '$' || getSingletonRegisterForAsmOperand(0, Info))
594 throw TGError(TheDef->getLoc(),
595 "Invalid instruction mnemonic '" + Mnemonic.str() + "'!");
597 // Remove the first operand, it is tracked in the mnemonic field.
598 AsmOperands.erase(AsmOperands.begin());
603 bool MatchableInfo::Validate(StringRef CommentDelimiter, bool Hack) const {
604 // Reject matchables with no .s string.
605 if (AsmString.empty())
606 throw TGError(TheDef->getLoc(), "instruction with empty asm string");
608 // Reject any matchables with a newline in them, they should be marked
609 // isCodeGenOnly if they are pseudo instructions.
610 if (AsmString.find('\n') != std::string::npos)
611 throw TGError(TheDef->getLoc(),
612 "multiline instruction is not valid for the asmparser, "
613 "mark it isCodeGenOnly");
615 // Remove comments from the asm string. We know that the asmstring only
617 if (!CommentDelimiter.empty() &&
618 StringRef(AsmString).find(CommentDelimiter) != StringRef::npos)
619 throw TGError(TheDef->getLoc(),
620 "asmstring for instruction has comment character in it, "
621 "mark it isCodeGenOnly");
623 // Reject matchables with operand modifiers, these aren't something we can
624 /// handle, the target should be refactored to use operands instead of
627 // Also, check for instructions which reference the operand multiple times;
628 // this implies a constraint we would not honor.
629 std::set<std::string> OperandNames;
630 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
631 StringRef Tok = AsmOperands[i].Token;
632 if (Tok[0] == '$' && Tok.find(':') != StringRef::npos)
633 throw TGError(TheDef->getLoc(),
634 "matchable with operand modifier '" + Tok.str() +
635 "' not supported by asm matcher. Mark isCodeGenOnly!");
637 // Verify that any operand is only mentioned once.
638 // We reject aliases and ignore instructions for now.
639 if (Tok[0] == '$' && !OperandNames.insert(Tok).second) {
641 throw TGError(TheDef->getLoc(),
642 "ERROR: matchable with tied operand '" + Tok.str() +
643 "' can never be matched!");
644 // FIXME: Should reject these. The ARM backend hits this with $lane in a
645 // bunch of instructions. It is unclear what the right answer is.
647 errs() << "warning: '" << InstrName << "': "
648 << "ignoring instruction with tied operand '"
649 << Tok.str() << "'\n";
655 // Validate the operand list to ensure we can handle this instruction.
656 for (unsigned i = 0, e = OperandList.size(); i != e; ++i) {
657 const CGIOperandList::OperandInfo &OI = OperandList[i];
659 // Validate tied operands.
660 if (OI.getTiedRegister() != -1) {
661 // If we have a tied operand that consists of multiple MCOperands, reject
662 // it. We reject aliases and ignore instructions for now.
663 if (OI.MINumOperands != 1) {
665 throw TGError(TheDef->getLoc(),
666 "ERROR: tied operand '" + OI.Name +
667 "' has multiple MCOperands!");
669 // FIXME: Should reject these. The ARM backend hits this with $lane in a
670 // bunch of instructions. It is unclear what the right answer is.
672 errs() << "warning: '" << InstrName << "': "
673 << "ignoring instruction with multi-operand tied operand '"
686 /// getSingletonRegisterForAsmOperand - If the specified token is a singleton
687 /// register, return the register name, otherwise return a null StringRef.
688 Record *MatchableInfo::
689 getSingletonRegisterForAsmOperand(unsigned i, const AsmMatcherInfo &Info) const{
690 StringRef Tok = AsmOperands[i].Token;
691 if (!Tok.startswith(Info.RegisterPrefix))
694 StringRef RegName = Tok.substr(Info.RegisterPrefix.size());
695 if (const CodeGenRegister *Reg = Info.Target.getRegisterByName(RegName))
698 // If there is no register prefix (i.e. "%" in "%eax"), then this may
699 // be some random non-register token, just ignore it.
700 if (Info.RegisterPrefix.empty())
703 // Otherwise, we have something invalid prefixed with the register prefix,
705 std::string Err = "unable to find register for '" + RegName.str() +
706 "' (which matches register prefix)";
707 throw TGError(TheDef->getLoc(), Err);
711 static std::string getEnumNameForToken(StringRef Str) {
714 for (StringRef::iterator it = Str.begin(), ie = Str.end(); it != ie; ++it) {
716 case '*': Res += "_STAR_"; break;
717 case '%': Res += "_PCT_"; break;
718 case ':': Res += "_COLON_"; break;
723 Res += "_" + utostr((unsigned) *it) + "_";
730 ClassInfo *AsmMatcherInfo::getTokenClass(StringRef Token) {
731 ClassInfo *&Entry = TokenClasses[Token];
734 Entry = new ClassInfo();
735 Entry->Kind = ClassInfo::Token;
736 Entry->ClassName = "Token";
737 Entry->Name = "MCK_" + getEnumNameForToken(Token);
738 Entry->ValueName = Token;
739 Entry->PredicateMethod = "<invalid>";
740 Entry->RenderMethod = "<invalid>";
741 Classes.push_back(Entry);
748 AsmMatcherInfo::getOperandClass(StringRef Token,
749 const CGIOperandList::OperandInfo &OI) {
750 if (OI.Rec->isSubClassOf("RegisterClass")) {
751 if (ClassInfo *CI = RegisterClassClasses[OI.Rec])
753 throw TGError(OI.Rec->getLoc(), "register class has no class info!");
756 assert(OI.Rec->isSubClassOf("Operand") && "Unexpected operand!");
757 Record *MatchClass = OI.Rec->getValueAsDef("ParserMatchClass");
758 if (ClassInfo *CI = AsmOperandClasses[MatchClass])
761 throw TGError(OI.Rec->getLoc(), "operand has no match class!");
764 void AsmMatcherInfo::
765 BuildRegisterClasses(SmallPtrSet<Record*, 16> &SingletonRegisters) {
766 const std::vector<CodeGenRegister> &Registers = Target.getRegisters();
767 const std::vector<CodeGenRegisterClass> &RegClassList =
768 Target.getRegisterClasses();
770 // The register sets used for matching.
771 std::set< std::set<Record*> > RegisterSets;
773 // Gather the defined sets.
774 for (std::vector<CodeGenRegisterClass>::const_iterator it =
775 RegClassList.begin(), ie = RegClassList.end(); it != ie; ++it)
776 RegisterSets.insert(std::set<Record*>(it->Elements.begin(),
777 it->Elements.end()));
779 // Add any required singleton sets.
780 for (SmallPtrSet<Record*, 16>::iterator it = SingletonRegisters.begin(),
781 ie = SingletonRegisters.end(); it != ie; ++it) {
783 RegisterSets.insert(std::set<Record*>(&Rec, &Rec + 1));
786 // Introduce derived sets where necessary (when a register does not determine
787 // a unique register set class), and build the mapping of registers to the set
788 // they should classify to.
789 std::map<Record*, std::set<Record*> > RegisterMap;
790 for (std::vector<CodeGenRegister>::const_iterator it = Registers.begin(),
791 ie = Registers.end(); it != ie; ++it) {
792 const CodeGenRegister &CGR = *it;
793 // Compute the intersection of all sets containing this register.
794 std::set<Record*> ContainingSet;
796 for (std::set< std::set<Record*> >::iterator it = RegisterSets.begin(),
797 ie = RegisterSets.end(); it != ie; ++it) {
798 if (!it->count(CGR.TheDef))
801 if (ContainingSet.empty()) {
806 std::set<Record*> Tmp;
807 std::swap(Tmp, ContainingSet);
808 std::insert_iterator< std::set<Record*> > II(ContainingSet,
809 ContainingSet.begin());
810 std::set_intersection(Tmp.begin(), Tmp.end(), it->begin(), it->end(), II);
813 if (!ContainingSet.empty()) {
814 RegisterSets.insert(ContainingSet);
815 RegisterMap.insert(std::make_pair(CGR.TheDef, ContainingSet));
819 // Construct the register classes.
820 std::map<std::set<Record*>, ClassInfo*> RegisterSetClasses;
822 for (std::set< std::set<Record*> >::iterator it = RegisterSets.begin(),
823 ie = RegisterSets.end(); it != ie; ++it, ++Index) {
824 ClassInfo *CI = new ClassInfo();
825 CI->Kind = ClassInfo::RegisterClass0 + Index;
826 CI->ClassName = "Reg" + utostr(Index);
827 CI->Name = "MCK_Reg" + utostr(Index);
829 CI->PredicateMethod = ""; // unused
830 CI->RenderMethod = "addRegOperands";
832 Classes.push_back(CI);
833 RegisterSetClasses.insert(std::make_pair(*it, CI));
836 // Find the superclasses; we could compute only the subgroup lattice edges,
837 // but there isn't really a point.
838 for (std::set< std::set<Record*> >::iterator it = RegisterSets.begin(),
839 ie = RegisterSets.end(); it != ie; ++it) {
840 ClassInfo *CI = RegisterSetClasses[*it];
841 for (std::set< std::set<Record*> >::iterator it2 = RegisterSets.begin(),
842 ie2 = RegisterSets.end(); it2 != ie2; ++it2)
844 std::includes(it2->begin(), it2->end(), it->begin(), it->end()))
845 CI->SuperClasses.push_back(RegisterSetClasses[*it2]);
848 // Name the register classes which correspond to a user defined RegisterClass.
849 for (std::vector<CodeGenRegisterClass>::const_iterator
850 it = RegClassList.begin(), ie = RegClassList.end(); it != ie; ++it) {
851 ClassInfo *CI = RegisterSetClasses[std::set<Record*>(it->Elements.begin(),
852 it->Elements.end())];
853 if (CI->ValueName.empty()) {
854 CI->ClassName = it->getName();
855 CI->Name = "MCK_" + it->getName();
856 CI->ValueName = it->getName();
858 CI->ValueName = CI->ValueName + "," + it->getName();
860 RegisterClassClasses.insert(std::make_pair(it->TheDef, CI));
863 // Populate the map for individual registers.
864 for (std::map<Record*, std::set<Record*> >::iterator it = RegisterMap.begin(),
865 ie = RegisterMap.end(); it != ie; ++it)
866 RegisterClasses[it->first] = RegisterSetClasses[it->second];
868 // Name the register classes which correspond to singleton registers.
869 for (SmallPtrSet<Record*, 16>::iterator it = SingletonRegisters.begin(),
870 ie = SingletonRegisters.end(); it != ie; ++it) {
872 ClassInfo *CI = RegisterClasses[Rec];
873 assert(CI && "Missing singleton register class info!");
875 if (CI->ValueName.empty()) {
876 CI->ClassName = Rec->getName();
877 CI->Name = "MCK_" + Rec->getName();
878 CI->ValueName = Rec->getName();
880 CI->ValueName = CI->ValueName + "," + Rec->getName();
884 void AsmMatcherInfo::BuildOperandClasses() {
885 std::vector<Record*> AsmOperands =
886 Records.getAllDerivedDefinitions("AsmOperandClass");
888 // Pre-populate AsmOperandClasses map.
889 for (std::vector<Record*>::iterator it = AsmOperands.begin(),
890 ie = AsmOperands.end(); it != ie; ++it)
891 AsmOperandClasses[*it] = new ClassInfo();
894 for (std::vector<Record*>::iterator it = AsmOperands.begin(),
895 ie = AsmOperands.end(); it != ie; ++it, ++Index) {
896 ClassInfo *CI = AsmOperandClasses[*it];
897 CI->Kind = ClassInfo::UserClass0 + Index;
899 ListInit *Supers = (*it)->getValueAsListInit("SuperClasses");
900 for (unsigned i = 0, e = Supers->getSize(); i != e; ++i) {
901 DefInit *DI = dynamic_cast<DefInit*>(Supers->getElement(i));
903 PrintError((*it)->getLoc(), "Invalid super class reference!");
907 ClassInfo *SC = AsmOperandClasses[DI->getDef()];
909 PrintError((*it)->getLoc(), "Invalid super class reference!");
911 CI->SuperClasses.push_back(SC);
913 CI->ClassName = (*it)->getValueAsString("Name");
914 CI->Name = "MCK_" + CI->ClassName;
915 CI->ValueName = (*it)->getName();
917 // Get or construct the predicate method name.
918 Init *PMName = (*it)->getValueInit("PredicateMethod");
919 if (StringInit *SI = dynamic_cast<StringInit*>(PMName)) {
920 CI->PredicateMethod = SI->getValue();
922 assert(dynamic_cast<UnsetInit*>(PMName) &&
923 "Unexpected PredicateMethod field!");
924 CI->PredicateMethod = "is" + CI->ClassName;
927 // Get or construct the render method name.
928 Init *RMName = (*it)->getValueInit("RenderMethod");
929 if (StringInit *SI = dynamic_cast<StringInit*>(RMName)) {
930 CI->RenderMethod = SI->getValue();
932 assert(dynamic_cast<UnsetInit*>(RMName) &&
933 "Unexpected RenderMethod field!");
934 CI->RenderMethod = "add" + CI->ClassName + "Operands";
937 AsmOperandClasses[*it] = CI;
938 Classes.push_back(CI);
942 AsmMatcherInfo::AsmMatcherInfo(Record *asmParser, CodeGenTarget &target)
943 : AsmParser(asmParser), Target(target),
944 RegisterPrefix(AsmParser->getValueAsString("RegisterPrefix")) {
948 void AsmMatcherInfo::BuildInfo() {
949 // Build information about all of the AssemblerPredicates.
950 std::vector<Record*> AllPredicates =
951 Records.getAllDerivedDefinitions("Predicate");
952 for (unsigned i = 0, e = AllPredicates.size(); i != e; ++i) {
953 Record *Pred = AllPredicates[i];
954 // Ignore predicates that are not intended for the assembler.
955 if (!Pred->getValueAsBit("AssemblerMatcherPredicate"))
958 if (Pred->getName().empty())
959 throw TGError(Pred->getLoc(), "Predicate has no name!");
961 unsigned FeatureNo = SubtargetFeatures.size();
962 SubtargetFeatures[Pred] = new SubtargetFeatureInfo(Pred, FeatureNo);
963 assert(FeatureNo < 32 && "Too many subtarget features!");
966 StringRef CommentDelimiter = AsmParser->getValueAsString("CommentDelimiter");
968 // Parse the instructions; we need to do this first so that we can gather the
969 // singleton register classes.
970 SmallPtrSet<Record*, 16> SingletonRegisters;
971 for (CodeGenTarget::inst_iterator I = Target.inst_begin(),
972 E = Target.inst_end(); I != E; ++I) {
973 const CodeGenInstruction &CGI = **I;
975 // If the tblgen -match-prefix option is specified (for tblgen hackers),
976 // filter the set of instructions we consider.
977 if (!StringRef(CGI.TheDef->getName()).startswith(MatchPrefix))
980 // Ignore "codegen only" instructions.
981 if (CGI.TheDef->getValueAsBit("isCodeGenOnly"))
984 OwningPtr<MatchableInfo> II(new MatchableInfo(CGI));
986 II->Initialize(*this, SingletonRegisters);
988 // Ignore instructions which shouldn't be matched and diagnose invalid
989 // instruction definitions with an error.
990 if (!II->Validate(CommentDelimiter, true))
993 // Ignore "Int_*" and "*_Int" instructions, which are internal aliases.
995 // FIXME: This is a total hack.
996 if (StringRef(II->InstrName).startswith("Int_") ||
997 StringRef(II->InstrName).endswith("_Int"))
1000 Matchables.push_back(II.take());
1003 // Parse all of the InstAlias definitions and stick them in the list of
1005 std::vector<Record*> AllInstAliases =
1006 Records.getAllDerivedDefinitions("InstAlias");
1007 for (unsigned i = 0, e = AllInstAliases.size(); i != e; ++i) {
1008 CodeGenInstAlias *Alias = new CodeGenInstAlias(AllInstAliases[i]);
1010 OwningPtr<MatchableInfo> II(new MatchableInfo(Alias));
1012 II->Initialize(*this, SingletonRegisters);
1014 // Validate the alias definitions.
1015 II->Validate(CommentDelimiter, false);
1017 Matchables.push_back(II.take());
1020 // Build info for the register classes.
1021 BuildRegisterClasses(SingletonRegisters);
1023 // Build info for the user defined assembly operand classes.
1024 BuildOperandClasses();
1026 // Build the information about matchables.
1027 for (std::vector<MatchableInfo*>::iterator it = Matchables.begin(),
1028 ie = Matchables.end(); it != ie; ++it) {
1029 MatchableInfo *II = *it;
1031 // Parse the tokens after the mnemonic.
1032 for (unsigned i = 0, e = II->AsmOperands.size(); i != e; ++i) {
1033 MatchableInfo::AsmOperand &Op = II->AsmOperands[i];
1034 StringRef Token = Op.Token;
1036 // Check for singleton registers.
1037 if (Record *RegRecord = II->getSingletonRegisterForAsmOperand(i, *this)) {
1038 Op.Class = RegisterClasses[RegRecord];
1039 assert(Op.Class && Op.Class->Registers.size() == 1 &&
1040 "Unexpected class for singleton register");
1044 // Check for simple tokens.
1045 if (Token[0] != '$') {
1046 Op.Class = getTokenClass(Token);
1050 // Otherwise this is an operand reference.
1051 StringRef OperandName;
1052 if (Token[1] == '{')
1053 OperandName = Token.substr(2, Token.size() - 3);
1055 OperandName = Token.substr(1);
1057 // Map this token to an operand. FIXME: Move elsewhere.
1059 if (!II->OperandList.hasOperandNamed(OperandName, Idx))
1060 throw TGError(II->TheDef->getLoc(), "error: unable to find operand: '" +
1061 OperandName.str() + "'");
1063 // FIXME: This is annoying, the named operand may be tied (e.g.,
1064 // XCHG8rm). What we want is the untied operand, which we now have to
1065 // grovel for. Only worry about this for single entry operands, we have to
1066 // clean this up anyway.
1067 const CGIOperandList::OperandInfo *OI = &II->OperandList[Idx];
1068 int OITied = OI->getTiedRegister();
1070 // The tied operand index is an MIOperand index, find the operand that
1072 for (unsigned i = 0, e = II->OperandList.size(); i != e; ++i) {
1073 if (II->OperandList[i].MIOperandNo == unsigned(OITied)) {
1074 OI = &II->OperandList[i];
1079 assert(OI && "Unable to find tied operand target!");
1082 Op.Class = getOperandClass(Token, *OI);
1083 Op.OperandInfo = OI;
1087 // Reorder classes so that classes preceed super classes.
1088 std::sort(Classes.begin(), Classes.end(), less_ptr<ClassInfo>());
1091 static void EmitConvertToMCInst(CodeGenTarget &Target,
1092 std::vector<MatchableInfo*> &Infos,
1094 // Write the convert function to a separate stream, so we can drop it after
1096 std::string ConvertFnBody;
1097 raw_string_ostream CvtOS(ConvertFnBody);
1099 // Function we have already generated.
1100 std::set<std::string> GeneratedFns;
1102 // Start the unified conversion function.
1104 CvtOS << "static void ConvertToMCInst(ConversionKind Kind, MCInst &Inst, "
1105 << "unsigned Opcode,\n"
1106 << " const SmallVectorImpl<MCParsedAsmOperand*"
1107 << "> &Operands) {\n";
1108 CvtOS << " Inst.setOpcode(Opcode);\n";
1109 CvtOS << " switch (Kind) {\n";
1110 CvtOS << " default:\n";
1112 // Start the enum, which we will generate inline.
1114 OS << "// Unified function for converting operands to MCInst instances.\n\n";
1115 OS << "enum ConversionKind {\n";
1117 // TargetOperandClass - This is the target's operand class, like X86Operand.
1118 std::string TargetOperandClass = Target.getName() + "Operand";
1120 /// OperandMap - This is a mapping from the MCInst operands (specified by the
1121 /// II.OperandList operands) to the AsmOperands that they filled in from.
1122 SmallVector<int, 16> OperandMap;
1124 for (std::vector<MatchableInfo*>::const_iterator it = Infos.begin(),
1125 ie = Infos.end(); it != ie; ++it) {
1126 MatchableInfo &II = **it;
1129 OperandMap.resize(II.OperandList.size(), -1);
1131 // Order the (class) operands by the order to convert them into an MCInst.
1132 for (unsigned i = 0, e = II.AsmOperands.size(); i != e; ++i) {
1133 MatchableInfo::AsmOperand &Op = II.AsmOperands[i];
1134 if (!Op.OperandInfo) continue;
1136 unsigned LogicalOpNum = Op.OperandInfo - &II.OperandList[0];
1137 assert(LogicalOpNum < OperandMap.size() && "Invalid operand number");
1138 OperandMap[LogicalOpNum] = i;
1141 // Build the conversion function signature.
1142 std::string Signature = "Convert";
1143 std::string CaseBody;
1144 raw_string_ostream CaseOS(CaseBody);
1146 // Compute the convert enum and the case body.
1147 for (unsigned i = 0, e = II.OperandList.size(); i != e; ++i) {
1148 const CGIOperandList::OperandInfo &OpInfo = II.OperandList[i];
1150 // Find out what operand from the asmparser that this MCInst operand comes
1152 int SrcOperand = OperandMap[i];
1153 if (SrcOperand != -1) {
1154 // Otherwise, this comes from something we parsed.
1155 MatchableInfo::AsmOperand &Op = II.AsmOperands[SrcOperand];
1157 // Registers are always converted the same, don't duplicate the
1158 // conversion function based on them.
1160 if (Op.Class->isRegisterClass())
1163 Signature += Op.Class->ClassName;
1164 Signature += utostr(Op.OperandInfo->MINumOperands);
1165 Signature += "_" + itostr(SrcOperand);
1167 CaseOS << " ((" << TargetOperandClass << "*)Operands["
1168 << SrcOperand << "+1])->" << Op.Class->RenderMethod
1169 << "(Inst, " << Op.OperandInfo->MINumOperands << ");\n";
1173 // Otherwise, this must be a tied operand if not, it is something that is
1174 // mentioned in the ins/outs list but not in the asm string.
1175 int TiedOp = OpInfo.getTiedRegister();
1177 throw TGError(II.TheDef->getLoc(), "Instruction '" +
1178 II.TheDef->getName() + "' has operand '" + OpInfo.Name +
1179 "' that doesn't appear in asm string!");
1181 // If this operand is tied to a previous one, just copy the MCInst operand
1182 // from the earlier one.
1183 // Copy the tied operand. We can only tie single MCOperand values.
1184 assert(OpInfo.MINumOperands == 1 && "Not a singular MCOperand");
1185 assert(i > unsigned(TiedOp) && "Tied operand preceeds its target!");
1186 CaseOS << " Inst.addOperand(Inst.getOperand(" << TiedOp << "));\n";
1187 Signature += "__Tie" + itostr(TiedOp);
1190 II.ConversionFnKind = Signature;
1192 // Check if we have already generated this signature.
1193 if (!GeneratedFns.insert(Signature).second)
1196 // If not, emit it now. Add to the enum list.
1197 OS << " " << Signature << ",\n";
1199 CvtOS << " case " << Signature << ":\n";
1200 CvtOS << CaseOS.str();
1201 CvtOS << " return;\n";
1204 // Finish the convert function.
1209 // Finish the enum, and drop the convert function after it.
1211 OS << " NumConversionVariants\n";
1217 /// EmitMatchClassEnumeration - Emit the enumeration for match class kinds.
1218 static void EmitMatchClassEnumeration(CodeGenTarget &Target,
1219 std::vector<ClassInfo*> &Infos,
1221 OS << "namespace {\n\n";
1223 OS << "/// MatchClassKind - The kinds of classes which participate in\n"
1224 << "/// instruction matching.\n";
1225 OS << "enum MatchClassKind {\n";
1226 OS << " InvalidMatchClass = 0,\n";
1227 for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
1228 ie = Infos.end(); it != ie; ++it) {
1229 ClassInfo &CI = **it;
1230 OS << " " << CI.Name << ", // ";
1231 if (CI.Kind == ClassInfo::Token) {
1232 OS << "'" << CI.ValueName << "'\n";
1233 } else if (CI.isRegisterClass()) {
1234 if (!CI.ValueName.empty())
1235 OS << "register class '" << CI.ValueName << "'\n";
1237 OS << "derived register class\n";
1239 OS << "user defined class '" << CI.ValueName << "'\n";
1242 OS << " NumMatchClassKinds\n";
1248 /// EmitClassifyOperand - Emit the function to classify an operand.
1249 static void EmitClassifyOperand(AsmMatcherInfo &Info,
1251 OS << "static MatchClassKind ClassifyOperand(MCParsedAsmOperand *GOp) {\n"
1252 << " " << Info.Target.getName() << "Operand &Operand = *("
1253 << Info.Target.getName() << "Operand*)GOp;\n";
1256 OS << " if (Operand.isToken())\n";
1257 OS << " return MatchTokenString(Operand.getToken());\n\n";
1259 // Classify registers.
1261 // FIXME: Don't hardcode isReg, getReg.
1262 OS << " if (Operand.isReg()) {\n";
1263 OS << " switch (Operand.getReg()) {\n";
1264 OS << " default: return InvalidMatchClass;\n";
1265 for (std::map<Record*, ClassInfo*>::iterator
1266 it = Info.RegisterClasses.begin(), ie = Info.RegisterClasses.end();
1268 OS << " case " << Info.Target.getName() << "::"
1269 << it->first->getName() << ": return " << it->second->Name << ";\n";
1273 // Classify user defined operands.
1274 for (std::vector<ClassInfo*>::iterator it = Info.Classes.begin(),
1275 ie = Info.Classes.end(); it != ie; ++it) {
1276 ClassInfo &CI = **it;
1278 if (!CI.isUserClass())
1281 OS << " // '" << CI.ClassName << "' class";
1282 if (!CI.SuperClasses.empty()) {
1283 OS << ", subclass of ";
1284 for (unsigned i = 0, e = CI.SuperClasses.size(); i != e; ++i) {
1286 OS << "'" << CI.SuperClasses[i]->ClassName << "'";
1287 assert(CI < *CI.SuperClasses[i] && "Invalid class relation!");
1292 OS << " if (Operand." << CI.PredicateMethod << "()) {\n";
1294 // Validate subclass relationships.
1295 if (!CI.SuperClasses.empty()) {
1296 for (unsigned i = 0, e = CI.SuperClasses.size(); i != e; ++i)
1297 OS << " assert(Operand." << CI.SuperClasses[i]->PredicateMethod
1298 << "() && \"Invalid class relationship!\");\n";
1301 OS << " return " << CI.Name << ";\n";
1304 OS << " return InvalidMatchClass;\n";
1308 /// EmitIsSubclass - Emit the subclass predicate function.
1309 static void EmitIsSubclass(CodeGenTarget &Target,
1310 std::vector<ClassInfo*> &Infos,
1312 OS << "/// IsSubclass - Compute whether \\arg A is a subclass of \\arg B.\n";
1313 OS << "static bool IsSubclass(MatchClassKind A, MatchClassKind B) {\n";
1314 OS << " if (A == B)\n";
1315 OS << " return true;\n\n";
1317 OS << " switch (A) {\n";
1318 OS << " default:\n";
1319 OS << " return false;\n";
1320 for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
1321 ie = Infos.end(); it != ie; ++it) {
1322 ClassInfo &A = **it;
1324 if (A.Kind != ClassInfo::Token) {
1325 std::vector<StringRef> SuperClasses;
1326 for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
1327 ie = Infos.end(); it != ie; ++it) {
1328 ClassInfo &B = **it;
1330 if (&A != &B && A.isSubsetOf(B))
1331 SuperClasses.push_back(B.Name);
1334 if (SuperClasses.empty())
1337 OS << "\n case " << A.Name << ":\n";
1339 if (SuperClasses.size() == 1) {
1340 OS << " return B == " << SuperClasses.back() << ";\n";
1344 OS << " switch (B) {\n";
1345 OS << " default: return false;\n";
1346 for (unsigned i = 0, e = SuperClasses.size(); i != e; ++i)
1347 OS << " case " << SuperClasses[i] << ": return true;\n";
1357 /// EmitMatchTokenString - Emit the function to match a token string to the
1358 /// appropriate match class value.
1359 static void EmitMatchTokenString(CodeGenTarget &Target,
1360 std::vector<ClassInfo*> &Infos,
1362 // Construct the match list.
1363 std::vector<StringMatcher::StringPair> Matches;
1364 for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
1365 ie = Infos.end(); it != ie; ++it) {
1366 ClassInfo &CI = **it;
1368 if (CI.Kind == ClassInfo::Token)
1369 Matches.push_back(StringMatcher::StringPair(CI.ValueName,
1370 "return " + CI.Name + ";"));
1373 OS << "static MatchClassKind MatchTokenString(StringRef Name) {\n";
1375 StringMatcher("Name", Matches, OS).Emit();
1377 OS << " return InvalidMatchClass;\n";
1381 /// EmitMatchRegisterName - Emit the function to match a string to the target
1382 /// specific register enum.
1383 static void EmitMatchRegisterName(CodeGenTarget &Target, Record *AsmParser,
1385 // Construct the match list.
1386 std::vector<StringMatcher::StringPair> Matches;
1387 for (unsigned i = 0, e = Target.getRegisters().size(); i != e; ++i) {
1388 const CodeGenRegister &Reg = Target.getRegisters()[i];
1389 if (Reg.TheDef->getValueAsString("AsmName").empty())
1392 Matches.push_back(StringMatcher::StringPair(
1393 Reg.TheDef->getValueAsString("AsmName"),
1394 "return " + utostr(i + 1) + ";"));
1397 OS << "static unsigned MatchRegisterName(StringRef Name) {\n";
1399 StringMatcher("Name", Matches, OS).Emit();
1401 OS << " return 0;\n";
1405 /// EmitSubtargetFeatureFlagEnumeration - Emit the subtarget feature flag
1407 static void EmitSubtargetFeatureFlagEnumeration(AsmMatcherInfo &Info,
1409 OS << "// Flags for subtarget features that participate in "
1410 << "instruction matching.\n";
1411 OS << "enum SubtargetFeatureFlag {\n";
1412 for (std::map<Record*, SubtargetFeatureInfo*>::const_iterator
1413 it = Info.SubtargetFeatures.begin(),
1414 ie = Info.SubtargetFeatures.end(); it != ie; ++it) {
1415 SubtargetFeatureInfo &SFI = *it->second;
1416 OS << " " << SFI.getEnumName() << " = (1 << " << SFI.Index << "),\n";
1418 OS << " Feature_None = 0\n";
1422 /// EmitComputeAvailableFeatures - Emit the function to compute the list of
1423 /// available features given a subtarget.
1424 static void EmitComputeAvailableFeatures(AsmMatcherInfo &Info,
1426 std::string ClassName =
1427 Info.AsmParser->getValueAsString("AsmParserClassName");
1429 OS << "unsigned " << Info.Target.getName() << ClassName << "::\n"
1430 << "ComputeAvailableFeatures(const " << Info.Target.getName()
1431 << "Subtarget *Subtarget) const {\n";
1432 OS << " unsigned Features = 0;\n";
1433 for (std::map<Record*, SubtargetFeatureInfo*>::const_iterator
1434 it = Info.SubtargetFeatures.begin(),
1435 ie = Info.SubtargetFeatures.end(); it != ie; ++it) {
1436 SubtargetFeatureInfo &SFI = *it->second;
1437 OS << " if (" << SFI.TheDef->getValueAsString("CondString")
1439 OS << " Features |= " << SFI.getEnumName() << ";\n";
1441 OS << " return Features;\n";
1445 static std::string GetAliasRequiredFeatures(Record *R,
1446 const AsmMatcherInfo &Info) {
1447 std::vector<Record*> ReqFeatures = R->getValueAsListOfDefs("Predicates");
1449 unsigned NumFeatures = 0;
1450 for (unsigned i = 0, e = ReqFeatures.size(); i != e; ++i) {
1451 SubtargetFeatureInfo *F = Info.getSubtargetFeature(ReqFeatures[i]);
1454 throw TGError(R->getLoc(), "Predicate '" + ReqFeatures[i]->getName() +
1455 "' is not marked as an AssemblerPredicate!");
1460 Result += F->getEnumName();
1464 if (NumFeatures > 1)
1465 Result = '(' + Result + ')';
1469 /// EmitMnemonicAliases - If the target has any MnemonicAlias<> definitions,
1470 /// emit a function for them and return true, otherwise return false.
1471 static bool EmitMnemonicAliases(raw_ostream &OS, const AsmMatcherInfo &Info) {
1472 std::vector<Record*> Aliases =
1473 Records.getAllDerivedDefinitions("MnemonicAlias");
1474 if (Aliases.empty()) return false;
1476 OS << "static void ApplyMnemonicAliases(StringRef &Mnemonic, "
1477 "unsigned Features) {\n";
1479 // Keep track of all the aliases from a mnemonic. Use an std::map so that the
1480 // iteration order of the map is stable.
1481 std::map<std::string, std::vector<Record*> > AliasesFromMnemonic;
1483 for (unsigned i = 0, e = Aliases.size(); i != e; ++i) {
1484 Record *R = Aliases[i];
1485 AliasesFromMnemonic[R->getValueAsString("FromMnemonic")].push_back(R);
1488 // Process each alias a "from" mnemonic at a time, building the code executed
1489 // by the string remapper.
1490 std::vector<StringMatcher::StringPair> Cases;
1491 for (std::map<std::string, std::vector<Record*> >::iterator
1492 I = AliasesFromMnemonic.begin(), E = AliasesFromMnemonic.end();
1494 const std::vector<Record*> &ToVec = I->second;
1496 // Loop through each alias and emit code that handles each case. If there
1497 // are two instructions without predicates, emit an error. If there is one,
1499 std::string MatchCode;
1500 int AliasWithNoPredicate = -1;
1502 for (unsigned i = 0, e = ToVec.size(); i != e; ++i) {
1503 Record *R = ToVec[i];
1504 std::string FeatureMask = GetAliasRequiredFeatures(R, Info);
1506 // If this unconditionally matches, remember it for later and diagnose
1508 if (FeatureMask.empty()) {
1509 if (AliasWithNoPredicate != -1) {
1510 // We can't have two aliases from the same mnemonic with no predicate.
1511 PrintError(ToVec[AliasWithNoPredicate]->getLoc(),
1512 "two MnemonicAliases with the same 'from' mnemonic!");
1513 throw TGError(R->getLoc(), "this is the other MnemonicAlias.");
1516 AliasWithNoPredicate = i;
1520 if (!MatchCode.empty())
1521 MatchCode += "else ";
1522 MatchCode += "if ((Features & " + FeatureMask + ") == "+FeatureMask+")\n";
1523 MatchCode += " Mnemonic = \"" +R->getValueAsString("ToMnemonic")+"\";\n";
1526 if (AliasWithNoPredicate != -1) {
1527 Record *R = ToVec[AliasWithNoPredicate];
1528 if (!MatchCode.empty())
1529 MatchCode += "else\n ";
1530 MatchCode += "Mnemonic = \"" + R->getValueAsString("ToMnemonic")+"\";\n";
1533 MatchCode += "return;";
1535 Cases.push_back(std::make_pair(I->first, MatchCode));
1539 StringMatcher("Mnemonic", Cases, OS).Emit();
1545 void AsmMatcherEmitter::run(raw_ostream &OS) {
1546 CodeGenTarget Target;
1547 Record *AsmParser = Target.getAsmParser();
1548 std::string ClassName = AsmParser->getValueAsString("AsmParserClassName");
1550 // Compute the information on the instructions to match.
1551 AsmMatcherInfo Info(AsmParser, Target);
1554 // Sort the instruction table using the partial order on classes. We use
1555 // stable_sort to ensure that ambiguous instructions are still
1556 // deterministically ordered.
1557 std::stable_sort(Info.Matchables.begin(), Info.Matchables.end(),
1558 less_ptr<MatchableInfo>());
1560 DEBUG_WITH_TYPE("instruction_info", {
1561 for (std::vector<MatchableInfo*>::iterator
1562 it = Info.Matchables.begin(), ie = Info.Matchables.end();
1567 // Check for ambiguous matchables.
1568 DEBUG_WITH_TYPE("ambiguous_instrs", {
1569 unsigned NumAmbiguous = 0;
1570 for (unsigned i = 0, e = Info.Matchables.size(); i != e; ++i) {
1571 for (unsigned j = i + 1; j != e; ++j) {
1572 MatchableInfo &A = *Info.Matchables[i];
1573 MatchableInfo &B = *Info.Matchables[j];
1575 if (A.CouldMatchAmiguouslyWith(B)) {
1576 errs() << "warning: ambiguous matchables:\n";
1578 errs() << "\nis incomparable with:\n";
1586 errs() << "warning: " << NumAmbiguous
1587 << " ambiguous matchables!\n";
1590 // Write the output.
1592 EmitSourceFileHeader("Assembly Matcher Source Fragment", OS);
1594 // Information for the class declaration.
1595 OS << "\n#ifdef GET_ASSEMBLER_HEADER\n";
1596 OS << "#undef GET_ASSEMBLER_HEADER\n";
1597 OS << " // This should be included into the middle of the declaration of \n";
1598 OS << " // your subclasses implementation of TargetAsmParser.\n";
1599 OS << " unsigned ComputeAvailableFeatures(const " <<
1600 Target.getName() << "Subtarget *Subtarget) const;\n";
1601 OS << " enum MatchResultTy {\n";
1602 OS << " Match_Success, Match_MnemonicFail, Match_InvalidOperand,\n";
1603 OS << " Match_MissingFeature\n";
1605 OS << " MatchResultTy MatchInstructionImpl(const "
1606 << "SmallVectorImpl<MCParsedAsmOperand*>"
1607 << " &Operands, MCInst &Inst, unsigned &ErrorInfo);\n\n";
1608 OS << "#endif // GET_ASSEMBLER_HEADER_INFO\n\n";
1613 OS << "\n#ifdef GET_REGISTER_MATCHER\n";
1614 OS << "#undef GET_REGISTER_MATCHER\n\n";
1616 // Emit the subtarget feature enumeration.
1617 EmitSubtargetFeatureFlagEnumeration(Info, OS);
1619 // Emit the function to match a register name to number.
1620 EmitMatchRegisterName(Target, AsmParser, OS);
1622 OS << "#endif // GET_REGISTER_MATCHER\n\n";
1625 OS << "\n#ifdef GET_MATCHER_IMPLEMENTATION\n";
1626 OS << "#undef GET_MATCHER_IMPLEMENTATION\n\n";
1628 // Generate the function that remaps for mnemonic aliases.
1629 bool HasMnemonicAliases = EmitMnemonicAliases(OS, Info);
1631 // Generate the unified function to convert operands into an MCInst.
1632 EmitConvertToMCInst(Target, Info.Matchables, OS);
1634 // Emit the enumeration for classes which participate in matching.
1635 EmitMatchClassEnumeration(Target, Info.Classes, OS);
1637 // Emit the routine to match token strings to their match class.
1638 EmitMatchTokenString(Target, Info.Classes, OS);
1640 // Emit the routine to classify an operand.
1641 EmitClassifyOperand(Info, OS);
1643 // Emit the subclass predicate routine.
1644 EmitIsSubclass(Target, Info.Classes, OS);
1646 // Emit the available features compute function.
1647 EmitComputeAvailableFeatures(Info, OS);
1650 size_t MaxNumOperands = 0;
1651 for (std::vector<MatchableInfo*>::const_iterator it =
1652 Info.Matchables.begin(), ie = Info.Matchables.end();
1654 MaxNumOperands = std::max(MaxNumOperands, (*it)->AsmOperands.size());
1657 // Emit the static match table; unused classes get initalized to 0 which is
1658 // guaranteed to be InvalidMatchClass.
1660 // FIXME: We can reduce the size of this table very easily. First, we change
1661 // it so that store the kinds in separate bit-fields for each index, which
1662 // only needs to be the max width used for classes at that index (we also need
1663 // to reject based on this during classification). If we then make sure to
1664 // order the match kinds appropriately (putting mnemonics last), then we
1665 // should only end up using a few bits for each class, especially the ones
1666 // following the mnemonic.
1667 OS << "namespace {\n";
1668 OS << " struct MatchEntry {\n";
1669 OS << " unsigned Opcode;\n";
1670 OS << " const char *Mnemonic;\n";
1671 OS << " ConversionKind ConvertFn;\n";
1672 OS << " MatchClassKind Classes[" << MaxNumOperands << "];\n";
1673 OS << " unsigned RequiredFeatures;\n";
1676 OS << "// Predicate for searching for an opcode.\n";
1677 OS << " struct LessOpcode {\n";
1678 OS << " bool operator()(const MatchEntry &LHS, StringRef RHS) {\n";
1679 OS << " return StringRef(LHS.Mnemonic) < RHS;\n";
1681 OS << " bool operator()(StringRef LHS, const MatchEntry &RHS) {\n";
1682 OS << " return LHS < StringRef(RHS.Mnemonic);\n";
1684 OS << " bool operator()(const MatchEntry &LHS, const MatchEntry &RHS) {\n";
1685 OS << " return StringRef(LHS.Mnemonic) < StringRef(RHS.Mnemonic);\n";
1689 OS << "} // end anonymous namespace.\n\n";
1691 OS << "static const MatchEntry MatchTable["
1692 << Info.Matchables.size() << "] = {\n";
1694 for (std::vector<MatchableInfo*>::const_iterator it =
1695 Info.Matchables.begin(), ie = Info.Matchables.end();
1697 MatchableInfo &II = **it;
1699 OS << " { " << Target.getName() << "::" << II.InstrName
1700 << ", \"" << II.Mnemonic << "\""
1701 << ", " << II.ConversionFnKind << ", { ";
1702 for (unsigned i = 0, e = II.AsmOperands.size(); i != e; ++i) {
1703 MatchableInfo::AsmOperand &Op = II.AsmOperands[i];
1706 OS << Op.Class->Name;
1710 // Write the required features mask.
1711 if (!II.RequiredFeatures.empty()) {
1712 for (unsigned i = 0, e = II.RequiredFeatures.size(); i != e; ++i) {
1714 OS << II.RequiredFeatures[i]->getEnumName();
1724 // Finally, build the match function.
1725 OS << Target.getName() << ClassName << "::MatchResultTy "
1726 << Target.getName() << ClassName << "::\n"
1727 << "MatchInstructionImpl(const SmallVectorImpl<MCParsedAsmOperand*>"
1729 OS << " MCInst &Inst, unsigned &ErrorInfo) {\n";
1731 // Emit code to get the available features.
1732 OS << " // Get the current feature set.\n";
1733 OS << " unsigned AvailableFeatures = getAvailableFeatures();\n\n";
1735 OS << " // Get the instruction mnemonic, which is the first token.\n";
1736 OS << " StringRef Mnemonic = ((" << Target.getName()
1737 << "Operand*)Operands[0])->getToken();\n\n";
1739 if (HasMnemonicAliases) {
1740 OS << " // Process all MnemonicAliases to remap the mnemonic.\n";
1741 OS << " ApplyMnemonicAliases(Mnemonic, AvailableFeatures);\n\n";
1744 // Emit code to compute the class list for this operand vector.
1745 OS << " // Eliminate obvious mismatches.\n";
1746 OS << " if (Operands.size() > " << (MaxNumOperands+1) << ") {\n";
1747 OS << " ErrorInfo = " << (MaxNumOperands+1) << ";\n";
1748 OS << " return Match_InvalidOperand;\n";
1751 OS << " // Compute the class list for this operand vector.\n";
1752 OS << " MatchClassKind Classes[" << MaxNumOperands << "];\n";
1753 OS << " for (unsigned i = 1, e = Operands.size(); i != e; ++i) {\n";
1754 OS << " Classes[i-1] = ClassifyOperand(Operands[i]);\n\n";
1756 OS << " // Check for invalid operands before matching.\n";
1757 OS << " if (Classes[i-1] == InvalidMatchClass) {\n";
1758 OS << " ErrorInfo = i;\n";
1759 OS << " return Match_InvalidOperand;\n";
1763 OS << " // Mark unused classes.\n";
1764 OS << " for (unsigned i = Operands.size()-1, e = " << MaxNumOperands << "; "
1765 << "i != e; ++i)\n";
1766 OS << " Classes[i] = InvalidMatchClass;\n\n";
1768 OS << " // Some state to try to produce better error messages.\n";
1769 OS << " bool HadMatchOtherThanFeatures = false;\n\n";
1770 OS << " // Set ErrorInfo to the operand that mismatches if it is \n";
1771 OS << " // wrong for all instances of the instruction.\n";
1772 OS << " ErrorInfo = ~0U;\n";
1774 // Emit code to search the table.
1775 OS << " // Search the table.\n";
1776 OS << " std::pair<const MatchEntry*, const MatchEntry*> MnemonicRange =\n";
1777 OS << " std::equal_range(MatchTable, MatchTable+"
1778 << Info.Matchables.size() << ", Mnemonic, LessOpcode());\n\n";
1780 OS << " // Return a more specific error code if no mnemonics match.\n";
1781 OS << " if (MnemonicRange.first == MnemonicRange.second)\n";
1782 OS << " return Match_MnemonicFail;\n\n";
1784 OS << " for (const MatchEntry *it = MnemonicRange.first, "
1785 << "*ie = MnemonicRange.second;\n";
1786 OS << " it != ie; ++it) {\n";
1788 OS << " // equal_range guarantees that instruction mnemonic matches.\n";
1789 OS << " assert(Mnemonic == it->Mnemonic);\n";
1791 // Emit check that the subclasses match.
1792 OS << " bool OperandsValid = true;\n";
1793 OS << " for (unsigned i = 0; i != " << MaxNumOperands << "; ++i) {\n";
1794 OS << " if (IsSubclass(Classes[i], it->Classes[i]))\n";
1795 OS << " continue;\n";
1796 OS << " // If this operand is broken for all of the instances of this\n";
1797 OS << " // mnemonic, keep track of it so we can report loc info.\n";
1798 OS << " if (it == MnemonicRange.first || ErrorInfo == i+1)\n";
1799 OS << " ErrorInfo = i+1;\n";
1801 OS << " ErrorInfo = ~0U;";
1802 OS << " // Otherwise, just reject this instance of the mnemonic.\n";
1803 OS << " OperandsValid = false;\n";
1807 OS << " if (!OperandsValid) continue;\n";
1809 // Emit check that the required features are available.
1810 OS << " if ((AvailableFeatures & it->RequiredFeatures) "
1811 << "!= it->RequiredFeatures) {\n";
1812 OS << " HadMatchOtherThanFeatures = true;\n";
1813 OS << " continue;\n";
1817 OS << " ConvertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands);\n";
1819 // Call the post-processing function, if used.
1820 std::string InsnCleanupFn =
1821 AsmParser->getValueAsString("AsmParserInstCleanup");
1822 if (!InsnCleanupFn.empty())
1823 OS << " " << InsnCleanupFn << "(Inst);\n";
1825 OS << " return Match_Success;\n";
1828 OS << " // Okay, we had no match. Try to return a useful error code.\n";
1829 OS << " if (HadMatchOtherThanFeatures) return Match_MissingFeature;\n";
1830 OS << " return Match_InvalidOperand;\n";
1833 OS << "#endif // GET_MATCHER_IMPLEMENTATION\n\n";