1 //===- AsmMatcherEmitter.cpp - Generate an assembly matcher ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend emits a target specifier matcher for converting parsed
11 // assembly operands in the MCInst structures. It also emits a matcher for
12 // custom operand parsing.
14 // Converting assembly operands into MCInst structures
15 // ---------------------------------------------------
17 // The input to the target specific matcher is a list of literal tokens and
18 // operands. The target specific parser should generally eliminate any syntax
19 // which is not relevant for matching; for example, comma tokens should have
20 // already been consumed and eliminated by the parser. Most instructions will
21 // end up with a single literal token (the instruction name) and some number of
24 // Some example inputs, for X86:
25 // 'addl' (immediate ...) (register ...)
26 // 'add' (immediate ...) (memory ...)
29 // The assembly matcher is responsible for converting this input into a precise
30 // machine instruction (i.e., an instruction with a well defined encoding). This
31 // mapping has several properties which complicate matching:
33 // - It may be ambiguous; many architectures can legally encode particular
34 // variants of an instruction in different ways (for example, using a smaller
35 // encoding for small immediates). Such ambiguities should never be
36 // arbitrarily resolved by the assembler, the assembler is always responsible
37 // for choosing the "best" available instruction.
39 // - It may depend on the subtarget or the assembler context. Instructions
40 // which are invalid for the current mode, but otherwise unambiguous (e.g.,
41 // an SSE instruction in a file being assembled for i486) should be accepted
42 // and rejected by the assembler front end. However, if the proper encoding
43 // for an instruction is dependent on the assembler context then the matcher
44 // is responsible for selecting the correct machine instruction for the
47 // The core matching algorithm attempts to exploit the regularity in most
48 // instruction sets to quickly determine the set of possibly matching
49 // instructions, and the simplify the generated code. Additionally, this helps
50 // to ensure that the ambiguities are intentionally resolved by the user.
52 // The matching is divided into two distinct phases:
54 // 1. Classification: Each operand is mapped to the unique set which (a)
55 // contains it, and (b) is the largest such subset for which a single
56 // instruction could match all members.
58 // For register classes, we can generate these subgroups automatically. For
59 // arbitrary operands, we expect the user to define the classes and their
60 // relations to one another (for example, 8-bit signed immediates as a
61 // subset of 32-bit immediates).
63 // By partitioning the operands in this way, we guarantee that for any
64 // tuple of classes, any single instruction must match either all or none
65 // of the sets of operands which could classify to that tuple.
67 // In addition, the subset relation amongst classes induces a partial order
68 // on such tuples, which we use to resolve ambiguities.
70 // 2. The input can now be treated as a tuple of classes (static tokens are
71 // simple singleton sets). Each such tuple should generally map to a single
72 // instruction (we currently ignore cases where this isn't true, whee!!!),
73 // which we can emit a simple matcher for.
75 // Custom Operand Parsing
76 // ----------------------
78 // Some targets need a custom way to parse operands, some specific instructions
79 // can contain arguments that can represent processor flags and other kinds of
80 // identifiers that need to be mapped to specific values in the final encoded
81 // instructions. The target specific custom operand parsing works in the
84 // 1. A operand match table is built, each entry contains a mnemonic, an
85 // operand class, a mask for all operand positions for that same
86 // class/mnemonic and target features to be checked while trying to match.
88 // 2. The operand matcher will try every possible entry with the same
89 // mnemonic and will check if the target feature for this mnemonic also
90 // matches. After that, if the operand to be matched has its index
91 // present in the mask, a successful match occurs. Otherwise, fallback
92 // to the regular operand parsing.
94 // 3. For a match success, each operand class that has a 'ParserMethod'
95 // becomes part of a switch from where the custom method is called.
97 //===----------------------------------------------------------------------===//
99 #include "CodeGenTarget.h"
100 #include "llvm/ADT/PointerUnion.h"
101 #include "llvm/ADT/STLExtras.h"
102 #include "llvm/ADT/SmallPtrSet.h"
103 #include "llvm/ADT/SmallVector.h"
104 #include "llvm/ADT/StringExtras.h"
105 #include "llvm/Support/CommandLine.h"
106 #include "llvm/Support/Debug.h"
107 #include "llvm/Support/ErrorHandling.h"
108 #include "llvm/TableGen/Error.h"
109 #include "llvm/TableGen/Record.h"
110 #include "llvm/TableGen/StringMatcher.h"
111 #include "llvm/TableGen/StringToOffsetTable.h"
112 #include "llvm/TableGen/TableGenBackend.h"
118 #include <forward_list>
119 using namespace llvm;
121 #define DEBUG_TYPE "asm-matcher-emitter"
123 static cl::opt<std::string>
124 MatchPrefix("match-prefix", cl::init(""),
125 cl::desc("Only match instructions with the given prefix"));
128 class AsmMatcherInfo;
129 struct SubtargetFeatureInfo;
131 // Register sets are used as keys in some second-order sets TableGen creates
132 // when generating its data structures. This means that the order of two
133 // RegisterSets can be seen in the outputted AsmMatcher tables occasionally, and
134 // can even affect compiler output (at least seen in diagnostics produced when
135 // all matches fail). So we use a type that sorts them consistently.
136 typedef std::set<Record*, LessRecordByID> RegisterSet;
138 class AsmMatcherEmitter {
139 RecordKeeper &Records;
141 AsmMatcherEmitter(RecordKeeper &R) : Records(R) {}
143 void run(raw_ostream &o);
146 /// ClassInfo - Helper class for storing the information about a particular
147 /// class of operands which can be matched.
150 /// Invalid kind, for use as a sentinel value.
153 /// The class for a particular token.
156 /// The (first) register class, subsequent register classes are
157 /// RegisterClass0+1, and so on.
160 /// The (first) user defined class, subsequent user defined classes are
161 /// UserClass0+1, and so on.
165 /// Kind - The class kind, which is either a predefined kind, or (UserClass0 +
166 /// N) for the Nth user defined class.
169 /// SuperClasses - The super classes of this class. Note that for simplicities
170 /// sake user operands only record their immediate super class, while register
171 /// operands include all superclasses.
172 std::vector<ClassInfo*> SuperClasses;
174 /// Name - The full class name, suitable for use in an enum.
177 /// ClassName - The unadorned generic name for this class (e.g., Token).
178 std::string ClassName;
180 /// ValueName - The name of the value this class represents; for a token this
181 /// is the literal token string, for an operand it is the TableGen class (or
182 /// empty if this is a derived class).
183 std::string ValueName;
185 /// PredicateMethod - The name of the operand method to test whether the
186 /// operand matches this class; this is not valid for Token or register kinds.
187 std::string PredicateMethod;
189 /// RenderMethod - The name of the operand method to add this operand to an
190 /// MCInst; this is not valid for Token or register kinds.
191 std::string RenderMethod;
193 /// ParserMethod - The name of the operand method to do a target specific
194 /// parsing on the operand.
195 std::string ParserMethod;
197 /// For register classes: the records for all the registers in this class.
198 RegisterSet Registers;
200 /// For custom match classes: the diagnostic kind for when the predicate fails.
201 std::string DiagnosticType;
203 /// isRegisterClass() - Check if this is a register class.
204 bool isRegisterClass() const {
205 return Kind >= RegisterClass0 && Kind < UserClass0;
208 /// isUserClass() - Check if this is a user defined class.
209 bool isUserClass() const {
210 return Kind >= UserClass0;
213 /// isRelatedTo - Check whether this class is "related" to \p RHS. Classes
214 /// are related if they are in the same class hierarchy.
215 bool isRelatedTo(const ClassInfo &RHS) const {
216 // Tokens are only related to tokens.
217 if (Kind == Token || RHS.Kind == Token)
218 return Kind == Token && RHS.Kind == Token;
220 // Registers classes are only related to registers classes, and only if
221 // their intersection is non-empty.
222 if (isRegisterClass() || RHS.isRegisterClass()) {
223 if (!isRegisterClass() || !RHS.isRegisterClass())
227 std::insert_iterator<RegisterSet> II(Tmp, Tmp.begin());
228 std::set_intersection(Registers.begin(), Registers.end(),
229 RHS.Registers.begin(), RHS.Registers.end(),
230 II, LessRecordByID());
235 // Otherwise we have two users operands; they are related if they are in the
236 // same class hierarchy.
238 // FIXME: This is an oversimplification, they should only be related if they
239 // intersect, however we don't have that information.
240 assert(isUserClass() && RHS.isUserClass() && "Unexpected class!");
241 const ClassInfo *Root = this;
242 while (!Root->SuperClasses.empty())
243 Root = Root->SuperClasses.front();
245 const ClassInfo *RHSRoot = &RHS;
246 while (!RHSRoot->SuperClasses.empty())
247 RHSRoot = RHSRoot->SuperClasses.front();
249 return Root == RHSRoot;
252 /// isSubsetOf - Test whether this class is a subset of \p RHS.
253 bool isSubsetOf(const ClassInfo &RHS) const {
254 // This is a subset of RHS if it is the same class...
258 // ... or if any of its super classes are a subset of RHS.
259 for (const ClassInfo *CI : SuperClasses)
260 if (CI->isSubsetOf(RHS))
266 /// operator< - Compare two classes.
267 // FIXME: This ordering seems to be broken. For example:
268 // u64 < i64, i64 < s8, s8 < u64, forming a cycle
269 // u64 is a subset of i64
270 // i64 and s8 are not subsets of each other, so are ordered by name
271 // s8 and u64 are not subsets of each other, so are ordered by name
272 bool operator<(const ClassInfo &RHS) const {
276 // Unrelated classes can be ordered by kind.
277 if (!isRelatedTo(RHS))
278 return Kind < RHS.Kind;
282 llvm_unreachable("Invalid kind!");
285 // This class precedes the RHS if it is a proper subset of the RHS.
288 if (RHS.isSubsetOf(*this))
291 // Otherwise, order by name to ensure we have a total ordering.
292 return ValueName < RHS.ValueName;
297 /// MatchableInfo - Helper class for storing the necessary information for an
298 /// instruction or alias which is capable of being matched.
299 struct MatchableInfo {
301 /// Token - This is the token that the operand came from.
304 /// The unique class instance this operand should match.
307 /// The operand name this is, if anything.
310 /// The suboperand index within SrcOpName, or -1 for the entire operand.
313 /// Register record if this token is singleton register.
314 Record *SingletonReg;
316 explicit AsmOperand(StringRef T) : Token(T), Class(nullptr), SubOpIdx(-1),
317 SingletonReg(nullptr) {}
320 /// ResOperand - This represents a single operand in the result instruction
321 /// generated by the match. In cases (like addressing modes) where a single
322 /// assembler operand expands to multiple MCOperands, this represents the
323 /// single assembler operand, not the MCOperand.
326 /// RenderAsmOperand - This represents an operand result that is
327 /// generated by calling the render method on the assembly operand. The
328 /// corresponding AsmOperand is specified by AsmOperandNum.
331 /// TiedOperand - This represents a result operand that is a duplicate of
332 /// a previous result operand.
335 /// ImmOperand - This represents an immediate value that is dumped into
339 /// RegOperand - This represents a fixed register that is dumped in.
344 /// This is the operand # in the AsmOperands list that this should be
346 unsigned AsmOperandNum;
348 /// TiedOperandNum - This is the (earlier) result operand that should be
350 unsigned TiedOperandNum;
352 /// ImmVal - This is the immediate value added to the instruction.
355 /// Register - This is the register record.
359 /// MINumOperands - The number of MCInst operands populated by this
361 unsigned MINumOperands;
363 static ResOperand getRenderedOp(unsigned AsmOpNum, unsigned NumOperands) {
365 X.Kind = RenderAsmOperand;
366 X.AsmOperandNum = AsmOpNum;
367 X.MINumOperands = NumOperands;
371 static ResOperand getTiedOp(unsigned TiedOperandNum) {
373 X.Kind = TiedOperand;
374 X.TiedOperandNum = TiedOperandNum;
379 static ResOperand getImmOp(int64_t Val) {
387 static ResOperand getRegOp(Record *Reg) {
396 /// AsmVariantID - Target's assembly syntax variant no.
399 /// AsmString - The assembly string for this instruction (with variants
400 /// removed), e.g. "movsx $src, $dst".
401 std::string AsmString;
403 /// TheDef - This is the definition of the instruction or InstAlias that this
404 /// matchable came from.
405 Record *const TheDef;
407 /// DefRec - This is the definition that it came from.
408 PointerUnion<const CodeGenInstruction*, const CodeGenInstAlias*> DefRec;
410 const CodeGenInstruction *getResultInst() const {
411 if (DefRec.is<const CodeGenInstruction*>())
412 return DefRec.get<const CodeGenInstruction*>();
413 return DefRec.get<const CodeGenInstAlias*>()->ResultInst;
416 /// ResOperands - This is the operand list that should be built for the result
418 SmallVector<ResOperand, 8> ResOperands;
420 /// Mnemonic - This is the first token of the matched instruction, its
424 /// AsmOperands - The textual operands that this instruction matches,
425 /// annotated with a class and where in the OperandList they were defined.
426 /// This directly corresponds to the tokenized AsmString after the mnemonic is
428 SmallVector<AsmOperand, 8> AsmOperands;
430 /// Predicates - The required subtarget features to match this instruction.
431 SmallVector<const SubtargetFeatureInfo *, 4> RequiredFeatures;
433 /// ConversionFnKind - The enum value which is passed to the generated
434 /// convertToMCInst to convert parsed operands into an MCInst for this
436 std::string ConversionFnKind;
438 /// If this instruction is deprecated in some form.
441 /// If this is an alias, this is use to determine whether or not to using
442 /// the conversion function defined by the instruction's AsmMatchConverter
443 /// or to use the function generated by the alias.
444 bool UseInstAsmMatchConverter;
446 MatchableInfo(const CodeGenInstruction &CGI)
447 : AsmVariantID(0), AsmString(CGI.AsmString), TheDef(CGI.TheDef), DefRec(&CGI),
448 UseInstAsmMatchConverter(true) {
451 MatchableInfo(std::unique_ptr<const CodeGenInstAlias> Alias)
452 : AsmVariantID(0), AsmString(Alias->AsmString), TheDef(Alias->TheDef),
453 DefRec(Alias.release()),
454 UseInstAsmMatchConverter(
455 TheDef->getValueAsBit("UseInstAsmMatchConverter")) {
459 delete DefRec.dyn_cast<const CodeGenInstAlias*>();
462 // Two-operand aliases clone from the main matchable, but mark the second
463 // operand as a tied operand of the first for purposes of the assembler.
464 void formTwoOperandAlias(StringRef Constraint);
466 void initialize(const AsmMatcherInfo &Info,
467 SmallPtrSetImpl<Record*> &SingletonRegisters,
468 int AsmVariantNo, std::string &RegisterPrefix);
470 /// validate - Return true if this matchable is a valid thing to match against
471 /// and perform a bunch of validity checking.
472 bool validate(StringRef CommentDelimiter, bool Hack) const;
474 /// extractSingletonRegisterForAsmOperand - Extract singleton register,
475 /// if present, from specified token.
477 extractSingletonRegisterForAsmOperand(unsigned i, const AsmMatcherInfo &Info,
478 std::string &RegisterPrefix);
480 /// findAsmOperand - Find the AsmOperand with the specified name and
481 /// suboperand index.
482 int findAsmOperand(StringRef N, int SubOpIdx) const {
483 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i)
484 if (N == AsmOperands[i].SrcOpName &&
485 SubOpIdx == AsmOperands[i].SubOpIdx)
490 /// findAsmOperandNamed - Find the first AsmOperand with the specified name.
491 /// This does not check the suboperand index.
492 int findAsmOperandNamed(StringRef N) const {
493 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i)
494 if (N == AsmOperands[i].SrcOpName)
499 void buildInstructionResultOperands();
500 void buildAliasResultOperands();
502 /// operator< - Compare two matchables.
503 bool operator<(const MatchableInfo &RHS) const {
504 // The primary comparator is the instruction mnemonic.
505 if (Mnemonic != RHS.Mnemonic)
506 return Mnemonic < RHS.Mnemonic;
508 if (AsmOperands.size() != RHS.AsmOperands.size())
509 return AsmOperands.size() < RHS.AsmOperands.size();
511 // Compare lexicographically by operand. The matcher validates that other
512 // orderings wouldn't be ambiguous using \see couldMatchAmbiguouslyWith().
513 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
514 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class)
516 if (*RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
520 // Give matches that require more features higher precedence. This is useful
521 // because we cannot define AssemblerPredicates with the negation of
522 // processor features. For example, ARM v6 "nop" may be either a HINT or
523 // MOV. With v6, we want to match HINT. The assembler has no way to
524 // predicate MOV under "NoV6", but HINT will always match first because it
525 // requires V6 while MOV does not.
526 if (RequiredFeatures.size() != RHS.RequiredFeatures.size())
527 return RequiredFeatures.size() > RHS.RequiredFeatures.size();
532 /// couldMatchAmbiguouslyWith - Check whether this matchable could
533 /// ambiguously match the same set of operands as \p RHS (without being a
534 /// strictly superior match).
535 bool couldMatchAmbiguouslyWith(const MatchableInfo &RHS) const {
536 // The primary comparator is the instruction mnemonic.
537 if (Mnemonic != RHS.Mnemonic)
540 // The number of operands is unambiguous.
541 if (AsmOperands.size() != RHS.AsmOperands.size())
544 // Otherwise, make sure the ordering of the two instructions is unambiguous
545 // by checking that either (a) a token or operand kind discriminates them,
546 // or (b) the ordering among equivalent kinds is consistent.
548 // Tokens and operand kinds are unambiguous (assuming a correct target
550 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i)
551 if (AsmOperands[i].Class->Kind != RHS.AsmOperands[i].Class->Kind ||
552 AsmOperands[i].Class->Kind == ClassInfo::Token)
553 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class ||
554 *RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
557 // Otherwise, this operand could commute if all operands are equivalent, or
558 // there is a pair of operands that compare less than and a pair that
559 // compare greater than.
560 bool HasLT = false, HasGT = false;
561 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
562 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class)
564 if (*RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
568 return !(HasLT ^ HasGT);
574 void tokenizeAsmString(const AsmMatcherInfo &Info);
575 void addAsmOperand(size_t Start, size_t End);
578 /// SubtargetFeatureInfo - Helper class for storing information on a subtarget
579 /// feature which participates in instruction matching.
580 struct SubtargetFeatureInfo {
581 /// \brief The predicate record for this feature.
584 /// \brief An unique index assigned to represent this feature.
587 SubtargetFeatureInfo(Record *D, uint64_t Idx) : TheDef(D), Index(Idx) {}
589 /// \brief The name of the enumerated constant identifying this feature.
590 std::string getEnumName() const {
591 return "Feature_" + TheDef->getName();
595 errs() << getEnumName() << " " << Index << "\n";
600 struct OperandMatchEntry {
601 unsigned OperandMask;
602 const MatchableInfo* MI;
605 static OperandMatchEntry create(const MatchableInfo *mi, ClassInfo *ci,
608 X.OperandMask = opMask;
616 class AsmMatcherInfo {
619 RecordKeeper &Records;
621 /// The tablegen AsmParser record.
624 /// Target - The target information.
625 CodeGenTarget &Target;
627 /// The classes which are needed for matching.
628 std::forward_list<ClassInfo> Classes;
630 /// The information on the matchables to match.
631 std::vector<std::unique_ptr<MatchableInfo>> Matchables;
633 /// Info for custom matching operands by user defined methods.
634 std::vector<OperandMatchEntry> OperandMatchInfo;
636 /// Map of Register records to their class information.
637 typedef std::map<Record*, ClassInfo*, LessRecordByID> RegisterClassesTy;
638 RegisterClassesTy RegisterClasses;
640 /// Map of Predicate records to their subtarget information.
641 std::map<Record *, SubtargetFeatureInfo, LessRecordByID> SubtargetFeatures;
643 /// Map of AsmOperandClass records to their class information.
644 std::map<Record*, ClassInfo*> AsmOperandClasses;
647 /// Map of token to class information which has already been constructed.
648 std::map<std::string, ClassInfo*> TokenClasses;
650 /// Map of RegisterClass records to their class information.
651 std::map<Record*, ClassInfo*> RegisterClassClasses;
654 /// getTokenClass - Lookup or create the class for the given token.
655 ClassInfo *getTokenClass(StringRef Token);
657 /// getOperandClass - Lookup or create the class for the given operand.
658 ClassInfo *getOperandClass(const CGIOperandList::OperandInfo &OI,
660 ClassInfo *getOperandClass(Record *Rec, int SubOpIdx);
662 /// buildRegisterClasses - Build the ClassInfo* instances for register
664 void buildRegisterClasses(SmallPtrSetImpl<Record*> &SingletonRegisters);
666 /// buildOperandClasses - Build the ClassInfo* instances for user defined
668 void buildOperandClasses();
670 void buildInstructionOperandReference(MatchableInfo *II, StringRef OpName,
672 void buildAliasOperandReference(MatchableInfo *II, StringRef OpName,
673 MatchableInfo::AsmOperand &Op);
676 AsmMatcherInfo(Record *AsmParser,
677 CodeGenTarget &Target,
678 RecordKeeper &Records);
680 /// buildInfo - Construct the various tables used during matching.
683 /// buildOperandMatchInfo - Build the necessary information to handle user
684 /// defined operand parsing methods.
685 void buildOperandMatchInfo();
687 /// getSubtargetFeature - Lookup or create the subtarget feature info for the
689 const SubtargetFeatureInfo *getSubtargetFeature(Record *Def) const {
690 assert(Def->isSubClassOf("Predicate") && "Invalid predicate type!");
691 const auto &I = SubtargetFeatures.find(Def);
692 return I == SubtargetFeatures.end() ? nullptr : &I->second;
695 RecordKeeper &getRecords() const {
700 } // End anonymous namespace
702 void MatchableInfo::dump() const {
703 errs() << TheDef->getName() << " -- " << "flattened:\"" << AsmString <<"\"\n";
705 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
706 const AsmOperand &Op = AsmOperands[i];
707 errs() << " op[" << i << "] = " << Op.Class->ClassName << " - ";
708 errs() << '\"' << Op.Token << "\"\n";
712 static std::pair<StringRef, StringRef>
713 parseTwoOperandConstraint(StringRef S, ArrayRef<SMLoc> Loc) {
714 // Split via the '='.
715 std::pair<StringRef, StringRef> Ops = S.split('=');
716 if (Ops.second == "")
717 PrintFatalError(Loc, "missing '=' in two-operand alias constraint");
718 // Trim whitespace and the leading '$' on the operand names.
719 size_t start = Ops.first.find_first_of('$');
720 if (start == std::string::npos)
721 PrintFatalError(Loc, "expected '$' prefix on asm operand name");
722 Ops.first = Ops.first.slice(start + 1, std::string::npos);
723 size_t end = Ops.first.find_last_of(" \t");
724 Ops.first = Ops.first.slice(0, end);
725 // Now the second operand.
726 start = Ops.second.find_first_of('$');
727 if (start == std::string::npos)
728 PrintFatalError(Loc, "expected '$' prefix on asm operand name");
729 Ops.second = Ops.second.slice(start + 1, std::string::npos);
730 end = Ops.second.find_last_of(" \t");
731 Ops.first = Ops.first.slice(0, end);
735 void MatchableInfo::formTwoOperandAlias(StringRef Constraint) {
736 // Figure out which operands are aliased and mark them as tied.
737 std::pair<StringRef, StringRef> Ops =
738 parseTwoOperandConstraint(Constraint, TheDef->getLoc());
740 // Find the AsmOperands that refer to the operands we're aliasing.
741 int SrcAsmOperand = findAsmOperandNamed(Ops.first);
742 int DstAsmOperand = findAsmOperandNamed(Ops.second);
743 if (SrcAsmOperand == -1)
744 PrintFatalError(TheDef->getLoc(),
745 "unknown source two-operand alias operand '" + Ops.first +
747 if (DstAsmOperand == -1)
748 PrintFatalError(TheDef->getLoc(),
749 "unknown destination two-operand alias operand '" +
752 // Find the ResOperand that refers to the operand we're aliasing away
753 // and update it to refer to the combined operand instead.
754 for (unsigned i = 0, e = ResOperands.size(); i != e; ++i) {
755 ResOperand &Op = ResOperands[i];
756 if (Op.Kind == ResOperand::RenderAsmOperand &&
757 Op.AsmOperandNum == (unsigned)SrcAsmOperand) {
758 Op.AsmOperandNum = DstAsmOperand;
762 // Remove the AsmOperand for the alias operand.
763 AsmOperands.erase(AsmOperands.begin() + SrcAsmOperand);
764 // Adjust the ResOperand references to any AsmOperands that followed
765 // the one we just deleted.
766 for (unsigned i = 0, e = ResOperands.size(); i != e; ++i) {
767 ResOperand &Op = ResOperands[i];
770 // Nothing to do for operands that don't reference AsmOperands.
772 case ResOperand::RenderAsmOperand:
773 if (Op.AsmOperandNum > (unsigned)SrcAsmOperand)
776 case ResOperand::TiedOperand:
777 if (Op.TiedOperandNum > (unsigned)SrcAsmOperand)
784 void MatchableInfo::initialize(const AsmMatcherInfo &Info,
785 SmallPtrSetImpl<Record*> &SingletonRegisters,
786 int AsmVariantNo, std::string &RegisterPrefix) {
787 AsmVariantID = AsmVariantNo;
789 CodeGenInstruction::FlattenAsmStringVariants(AsmString, AsmVariantNo);
791 tokenizeAsmString(Info);
793 // Compute the require features.
794 std::vector<Record*> Predicates =TheDef->getValueAsListOfDefs("Predicates");
795 for (unsigned i = 0, e = Predicates.size(); i != e; ++i)
796 if (const SubtargetFeatureInfo *Feature =
797 Info.getSubtargetFeature(Predicates[i]))
798 RequiredFeatures.push_back(Feature);
800 // Collect singleton registers, if used.
801 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
802 extractSingletonRegisterForAsmOperand(i, Info, RegisterPrefix);
803 if (Record *Reg = AsmOperands[i].SingletonReg)
804 SingletonRegisters.insert(Reg);
807 const RecordVal *DepMask = TheDef->getValue("DeprecatedFeatureMask");
809 DepMask = TheDef->getValue("ComplexDeprecationPredicate");
812 DepMask ? !DepMask->getValue()->getAsUnquotedString().empty() : false;
815 /// Append an AsmOperand for the given substring of AsmString.
816 void MatchableInfo::addAsmOperand(size_t Start, size_t End) {
817 StringRef String = AsmString;
818 AsmOperands.push_back(AsmOperand(String.slice(Start, End)));
821 /// tokenizeAsmString - Tokenize a simplified assembly string.
822 void MatchableInfo::tokenizeAsmString(const AsmMatcherInfo &Info) {
823 StringRef String = AsmString;
826 for (unsigned i = 0, e = String.size(); i != e; ++i) {
836 addAsmOperand(Prev, i);
839 if (!isspace(String[i]) && String[i] != ',')
840 addAsmOperand(i, i + 1);
846 addAsmOperand(Prev, i);
850 assert(i != String.size() && "Invalid quoted character");
851 addAsmOperand(i, i + 1);
857 addAsmOperand(Prev, i);
861 // If this isn't "${", treat like a normal token.
862 if (i + 1 == String.size() || String[i + 1] != '{') {
867 StringRef::iterator End = std::find(String.begin() + i, String.end(),'}');
868 assert(End != String.end() && "Missing brace in operand reference!");
869 size_t EndPos = End - String.begin();
870 addAsmOperand(i, EndPos+1);
877 if (!Info.AsmParser->getValueAsBit("MnemonicContainsDot")) {
879 addAsmOperand(Prev, i);
889 if (InTok && Prev != String.size())
890 addAsmOperand(Prev, StringRef::npos);
892 // The first token of the instruction is the mnemonic, which must be a
893 // simple string, not a $foo variable or a singleton register.
894 if (AsmOperands.empty())
895 PrintFatalError(TheDef->getLoc(),
896 "Instruction '" + TheDef->getName() + "' has no tokens");
897 Mnemonic = AsmOperands[0].Token;
898 if (Mnemonic.empty())
899 PrintFatalError(TheDef->getLoc(),
900 "Missing instruction mnemonic");
901 // FIXME : Check and raise an error if it is a register.
902 if (Mnemonic[0] == '$')
903 PrintFatalError(TheDef->getLoc(),
904 "Invalid instruction mnemonic '" + Mnemonic + "'!");
906 // Remove the first operand, it is tracked in the mnemonic field.
907 AsmOperands.erase(AsmOperands.begin());
910 bool MatchableInfo::validate(StringRef CommentDelimiter, bool Hack) const {
911 // Reject matchables with no .s string.
912 if (AsmString.empty())
913 PrintFatalError(TheDef->getLoc(), "instruction with empty asm string");
915 // Reject any matchables with a newline in them, they should be marked
916 // isCodeGenOnly if they are pseudo instructions.
917 if (AsmString.find('\n') != std::string::npos)
918 PrintFatalError(TheDef->getLoc(),
919 "multiline instruction is not valid for the asmparser, "
920 "mark it isCodeGenOnly");
922 // Remove comments from the asm string. We know that the asmstring only
924 if (!CommentDelimiter.empty() &&
925 StringRef(AsmString).find(CommentDelimiter) != StringRef::npos)
926 PrintFatalError(TheDef->getLoc(),
927 "asmstring for instruction has comment character in it, "
928 "mark it isCodeGenOnly");
930 // Reject matchables with operand modifiers, these aren't something we can
931 // handle, the target should be refactored to use operands instead of
934 // Also, check for instructions which reference the operand multiple times;
935 // this implies a constraint we would not honor.
936 std::set<std::string> OperandNames;
937 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
938 StringRef Tok = AsmOperands[i].Token;
939 if (Tok[0] == '$' && Tok.find(':') != StringRef::npos)
940 PrintFatalError(TheDef->getLoc(),
941 "matchable with operand modifier '" + Tok +
942 "' not supported by asm matcher. Mark isCodeGenOnly!");
944 // Verify that any operand is only mentioned once.
945 // We reject aliases and ignore instructions for now.
946 if (Tok[0] == '$' && !OperandNames.insert(Tok).second) {
948 PrintFatalError(TheDef->getLoc(),
949 "ERROR: matchable with tied operand '" + Tok +
950 "' can never be matched!");
951 // FIXME: Should reject these. The ARM backend hits this with $lane in a
952 // bunch of instructions. It is unclear what the right answer is.
954 errs() << "warning: '" << TheDef->getName() << "': "
955 << "ignoring instruction with tied operand '"
965 /// extractSingletonRegisterForAsmOperand - Extract singleton register,
966 /// if present, from specified token.
968 extractSingletonRegisterForAsmOperand(unsigned OperandNo,
969 const AsmMatcherInfo &Info,
970 std::string &RegisterPrefix) {
971 StringRef Tok = AsmOperands[OperandNo].Token;
972 if (RegisterPrefix.empty()) {
973 std::string LoweredTok = Tok.lower();
974 if (const CodeGenRegister *Reg = Info.Target.getRegisterByName(LoweredTok))
975 AsmOperands[OperandNo].SingletonReg = Reg->TheDef;
979 if (!Tok.startswith(RegisterPrefix))
982 StringRef RegName = Tok.substr(RegisterPrefix.size());
983 if (const CodeGenRegister *Reg = Info.Target.getRegisterByName(RegName))
984 AsmOperands[OperandNo].SingletonReg = Reg->TheDef;
986 // If there is no register prefix (i.e. "%" in "%eax"), then this may
987 // be some random non-register token, just ignore it.
991 static std::string getEnumNameForToken(StringRef Str) {
994 for (StringRef::iterator it = Str.begin(), ie = Str.end(); it != ie; ++it) {
996 case '*': Res += "_STAR_"; break;
997 case '%': Res += "_PCT_"; break;
998 case ':': Res += "_COLON_"; break;
999 case '!': Res += "_EXCLAIM_"; break;
1000 case '.': Res += "_DOT_"; break;
1001 case '<': Res += "_LT_"; break;
1002 case '>': Res += "_GT_"; break;
1003 case '-': Res += "_MINUS_"; break;
1005 if ((*it >= 'A' && *it <= 'Z') ||
1006 (*it >= 'a' && *it <= 'z') ||
1007 (*it >= '0' && *it <= '9'))
1010 Res += "_" + utostr((unsigned) *it) + "_";
1017 ClassInfo *AsmMatcherInfo::getTokenClass(StringRef Token) {
1018 ClassInfo *&Entry = TokenClasses[Token];
1021 Classes.emplace_front();
1022 Entry = &Classes.front();
1023 Entry->Kind = ClassInfo::Token;
1024 Entry->ClassName = "Token";
1025 Entry->Name = "MCK_" + getEnumNameForToken(Token);
1026 Entry->ValueName = Token;
1027 Entry->PredicateMethod = "<invalid>";
1028 Entry->RenderMethod = "<invalid>";
1029 Entry->ParserMethod = "";
1030 Entry->DiagnosticType = "";
1037 AsmMatcherInfo::getOperandClass(const CGIOperandList::OperandInfo &OI,
1039 Record *Rec = OI.Rec;
1041 Rec = cast<DefInit>(OI.MIOperandInfo->getArg(SubOpIdx))->getDef();
1042 return getOperandClass(Rec, SubOpIdx);
1046 AsmMatcherInfo::getOperandClass(Record *Rec, int SubOpIdx) {
1047 if (Rec->isSubClassOf("RegisterOperand")) {
1048 // RegisterOperand may have an associated ParserMatchClass. If it does,
1049 // use it, else just fall back to the underlying register class.
1050 const RecordVal *R = Rec->getValue("ParserMatchClass");
1051 if (!R || !R->getValue())
1052 PrintFatalError("Record `" + Rec->getName() +
1053 "' does not have a ParserMatchClass!\n");
1055 if (DefInit *DI= dyn_cast<DefInit>(R->getValue())) {
1056 Record *MatchClass = DI->getDef();
1057 if (ClassInfo *CI = AsmOperandClasses[MatchClass])
1061 // No custom match class. Just use the register class.
1062 Record *ClassRec = Rec->getValueAsDef("RegClass");
1064 PrintFatalError(Rec->getLoc(), "RegisterOperand `" + Rec->getName() +
1065 "' has no associated register class!\n");
1066 if (ClassInfo *CI = RegisterClassClasses[ClassRec])
1068 PrintFatalError(Rec->getLoc(), "register class has no class info!");
1072 if (Rec->isSubClassOf("RegisterClass")) {
1073 if (ClassInfo *CI = RegisterClassClasses[Rec])
1075 PrintFatalError(Rec->getLoc(), "register class has no class info!");
1078 if (!Rec->isSubClassOf("Operand"))
1079 PrintFatalError(Rec->getLoc(), "Operand `" + Rec->getName() +
1080 "' does not derive from class Operand!\n");
1081 Record *MatchClass = Rec->getValueAsDef("ParserMatchClass");
1082 if (ClassInfo *CI = AsmOperandClasses[MatchClass])
1085 PrintFatalError(Rec->getLoc(), "operand has no match class!");
1088 struct LessRegisterSet {
1089 bool operator() (const RegisterSet &LHS, const RegisterSet & RHS) const {
1090 // std::set<T> defines its own compariso "operator<", but it
1091 // performs a lexicographical comparison by T's innate comparison
1092 // for some reason. We don't want non-deterministic pointer
1093 // comparisons so use this instead.
1094 return std::lexicographical_compare(LHS.begin(), LHS.end(),
1095 RHS.begin(), RHS.end(),
1100 void AsmMatcherInfo::
1101 buildRegisterClasses(SmallPtrSetImpl<Record*> &SingletonRegisters) {
1102 const auto &Registers = Target.getRegBank().getRegisters();
1103 auto &RegClassList = Target.getRegBank().getRegClasses();
1105 typedef std::set<RegisterSet, LessRegisterSet> RegisterSetSet;
1107 // The register sets used for matching.
1108 RegisterSetSet RegisterSets;
1110 // Gather the defined sets.
1111 for (const CodeGenRegisterClass &RC : RegClassList)
1112 RegisterSets.insert(
1113 RegisterSet(RC.getOrder().begin(), RC.getOrder().end()));
1115 // Add any required singleton sets.
1116 for (Record *Rec : SingletonRegisters) {
1117 RegisterSets.insert(RegisterSet(&Rec, &Rec + 1));
1120 // Introduce derived sets where necessary (when a register does not determine
1121 // a unique register set class), and build the mapping of registers to the set
1122 // they should classify to.
1123 std::map<Record*, RegisterSet> RegisterMap;
1124 for (const CodeGenRegister &CGR : Registers) {
1125 // Compute the intersection of all sets containing this register.
1126 RegisterSet ContainingSet;
1128 for (const RegisterSet &RS : RegisterSets) {
1129 if (!RS.count(CGR.TheDef))
1132 if (ContainingSet.empty()) {
1138 std::swap(Tmp, ContainingSet);
1139 std::insert_iterator<RegisterSet> II(ContainingSet,
1140 ContainingSet.begin());
1141 std::set_intersection(Tmp.begin(), Tmp.end(), RS.begin(), RS.end(), II,
1145 if (!ContainingSet.empty()) {
1146 RegisterSets.insert(ContainingSet);
1147 RegisterMap.insert(std::make_pair(CGR.TheDef, ContainingSet));
1151 // Construct the register classes.
1152 std::map<RegisterSet, ClassInfo*, LessRegisterSet> RegisterSetClasses;
1154 for (const RegisterSet &RS : RegisterSets) {
1155 Classes.emplace_front();
1156 ClassInfo *CI = &Classes.front();
1157 CI->Kind = ClassInfo::RegisterClass0 + Index;
1158 CI->ClassName = "Reg" + utostr(Index);
1159 CI->Name = "MCK_Reg" + utostr(Index);
1161 CI->PredicateMethod = ""; // unused
1162 CI->RenderMethod = "addRegOperands";
1164 // FIXME: diagnostic type.
1165 CI->DiagnosticType = "";
1166 RegisterSetClasses.insert(std::make_pair(RS, CI));
1170 // Find the superclasses; we could compute only the subgroup lattice edges,
1171 // but there isn't really a point.
1172 for (const RegisterSet &RS : RegisterSets) {
1173 ClassInfo *CI = RegisterSetClasses[RS];
1174 for (const RegisterSet &RS2 : RegisterSets)
1176 std::includes(RS2.begin(), RS2.end(), RS.begin(), RS.end(),
1178 CI->SuperClasses.push_back(RegisterSetClasses[RS2]);
1181 // Name the register classes which correspond to a user defined RegisterClass.
1182 for (const CodeGenRegisterClass &RC : RegClassList) {
1183 // Def will be NULL for non-user defined register classes.
1184 Record *Def = RC.getDef();
1187 ClassInfo *CI = RegisterSetClasses[RegisterSet(RC.getOrder().begin(),
1188 RC.getOrder().end())];
1189 if (CI->ValueName.empty()) {
1190 CI->ClassName = RC.getName();
1191 CI->Name = "MCK_" + RC.getName();
1192 CI->ValueName = RC.getName();
1194 CI->ValueName = CI->ValueName + "," + RC.getName();
1196 RegisterClassClasses.insert(std::make_pair(Def, CI));
1199 // Populate the map for individual registers.
1200 for (std::map<Record*, RegisterSet>::iterator it = RegisterMap.begin(),
1201 ie = RegisterMap.end(); it != ie; ++it)
1202 RegisterClasses[it->first] = RegisterSetClasses[it->second];
1204 // Name the register classes which correspond to singleton registers.
1205 for (Record *Rec : SingletonRegisters) {
1206 ClassInfo *CI = RegisterClasses[Rec];
1207 assert(CI && "Missing singleton register class info!");
1209 if (CI->ValueName.empty()) {
1210 CI->ClassName = Rec->getName();
1211 CI->Name = "MCK_" + Rec->getName();
1212 CI->ValueName = Rec->getName();
1214 CI->ValueName = CI->ValueName + "," + Rec->getName();
1218 void AsmMatcherInfo::buildOperandClasses() {
1219 std::vector<Record*> AsmOperands =
1220 Records.getAllDerivedDefinitions("AsmOperandClass");
1222 // Pre-populate AsmOperandClasses map.
1223 for (Record *Rec : AsmOperands) {
1224 Classes.emplace_front();
1225 AsmOperandClasses[Rec] = &Classes.front();
1229 for (Record *Rec : AsmOperands) {
1230 ClassInfo *CI = AsmOperandClasses[Rec];
1231 CI->Kind = ClassInfo::UserClass0 + Index;
1233 ListInit *Supers = Rec->getValueAsListInit("SuperClasses");
1234 for (unsigned i = 0, e = Supers->getSize(); i != e; ++i) {
1235 DefInit *DI = dyn_cast<DefInit>(Supers->getElement(i));
1237 PrintError(Rec->getLoc(), "Invalid super class reference!");
1241 ClassInfo *SC = AsmOperandClasses[DI->getDef()];
1243 PrintError(Rec->getLoc(), "Invalid super class reference!");
1245 CI->SuperClasses.push_back(SC);
1247 CI->ClassName = Rec->getValueAsString("Name");
1248 CI->Name = "MCK_" + CI->ClassName;
1249 CI->ValueName = Rec->getName();
1251 // Get or construct the predicate method name.
1252 Init *PMName = Rec->getValueInit("PredicateMethod");
1253 if (StringInit *SI = dyn_cast<StringInit>(PMName)) {
1254 CI->PredicateMethod = SI->getValue();
1256 assert(isa<UnsetInit>(PMName) && "Unexpected PredicateMethod field!");
1257 CI->PredicateMethod = "is" + CI->ClassName;
1260 // Get or construct the render method name.
1261 Init *RMName = Rec->getValueInit("RenderMethod");
1262 if (StringInit *SI = dyn_cast<StringInit>(RMName)) {
1263 CI->RenderMethod = SI->getValue();
1265 assert(isa<UnsetInit>(RMName) && "Unexpected RenderMethod field!");
1266 CI->RenderMethod = "add" + CI->ClassName + "Operands";
1269 // Get the parse method name or leave it as empty.
1270 Init *PRMName = Rec->getValueInit("ParserMethod");
1271 if (StringInit *SI = dyn_cast<StringInit>(PRMName))
1272 CI->ParserMethod = SI->getValue();
1274 // Get the diagnostic type or leave it as empty.
1275 // Get the parse method name or leave it as empty.
1276 Init *DiagnosticType = Rec->getValueInit("DiagnosticType");
1277 if (StringInit *SI = dyn_cast<StringInit>(DiagnosticType))
1278 CI->DiagnosticType = SI->getValue();
1284 AsmMatcherInfo::AsmMatcherInfo(Record *asmParser,
1285 CodeGenTarget &target,
1286 RecordKeeper &records)
1287 : Records(records), AsmParser(asmParser), Target(target) {
1290 /// buildOperandMatchInfo - Build the necessary information to handle user
1291 /// defined operand parsing methods.
1292 void AsmMatcherInfo::buildOperandMatchInfo() {
1294 /// Map containing a mask with all operands indices that can be found for
1295 /// that class inside a instruction.
1296 typedef std::map<ClassInfo *, unsigned, less_ptr<ClassInfo>> OpClassMaskTy;
1297 OpClassMaskTy OpClassMask;
1299 for (const auto &MI : Matchables) {
1300 OpClassMask.clear();
1302 // Keep track of all operands of this instructions which belong to the
1304 for (unsigned i = 0, e = MI->AsmOperands.size(); i != e; ++i) {
1305 const MatchableInfo::AsmOperand &Op = MI->AsmOperands[i];
1306 if (Op.Class->ParserMethod.empty())
1308 unsigned &OperandMask = OpClassMask[Op.Class];
1309 OperandMask |= (1 << i);
1312 // Generate operand match info for each mnemonic/operand class pair.
1313 for (const auto &OCM : OpClassMask) {
1314 unsigned OpMask = OCM.second;
1315 ClassInfo *CI = OCM.first;
1316 OperandMatchInfo.push_back(OperandMatchEntry::create(MI.get(), CI,
1322 void AsmMatcherInfo::buildInfo() {
1323 // Build information about all of the AssemblerPredicates.
1324 std::vector<Record*> AllPredicates =
1325 Records.getAllDerivedDefinitions("Predicate");
1326 for (unsigned i = 0, e = AllPredicates.size(); i != e; ++i) {
1327 Record *Pred = AllPredicates[i];
1328 // Ignore predicates that are not intended for the assembler.
1329 if (!Pred->getValueAsBit("AssemblerMatcherPredicate"))
1332 if (Pred->getName().empty())
1333 PrintFatalError(Pred->getLoc(), "Predicate has no name!");
1335 SubtargetFeatures.insert(std::make_pair(
1336 Pred, SubtargetFeatureInfo(Pred, SubtargetFeatures.size())));
1337 DEBUG(SubtargetFeatures.find(Pred)->second.dump());
1338 assert(SubtargetFeatures.size() <= 64 && "Too many subtarget features!");
1341 // Parse the instructions; we need to do this first so that we can gather the
1342 // singleton register classes.
1343 SmallPtrSet<Record*, 16> SingletonRegisters;
1344 unsigned VariantCount = Target.getAsmParserVariantCount();
1345 for (unsigned VC = 0; VC != VariantCount; ++VC) {
1346 Record *AsmVariant = Target.getAsmParserVariant(VC);
1347 std::string CommentDelimiter =
1348 AsmVariant->getValueAsString("CommentDelimiter");
1349 std::string RegisterPrefix = AsmVariant->getValueAsString("RegisterPrefix");
1350 int AsmVariantNo = AsmVariant->getValueAsInt("Variant");
1352 for (const CodeGenInstruction *CGI : Target.instructions()) {
1354 // If the tblgen -match-prefix option is specified (for tblgen hackers),
1355 // filter the set of instructions we consider.
1356 if (!StringRef(CGI->TheDef->getName()).startswith(MatchPrefix))
1359 // Ignore "codegen only" instructions.
1360 if (CGI->TheDef->getValueAsBit("isCodeGenOnly"))
1363 std::unique_ptr<MatchableInfo> II(new MatchableInfo(*CGI));
1365 II->initialize(*this, SingletonRegisters, AsmVariantNo, RegisterPrefix);
1367 // Ignore instructions which shouldn't be matched and diagnose invalid
1368 // instruction definitions with an error.
1369 if (!II->validate(CommentDelimiter, true))
1372 Matchables.push_back(std::move(II));
1375 // Parse all of the InstAlias definitions and stick them in the list of
1377 std::vector<Record*> AllInstAliases =
1378 Records.getAllDerivedDefinitions("InstAlias");
1379 for (unsigned i = 0, e = AllInstAliases.size(); i != e; ++i) {
1380 auto Alias = llvm::make_unique<CodeGenInstAlias>(AllInstAliases[i],
1381 AsmVariantNo, Target);
1383 // If the tblgen -match-prefix option is specified (for tblgen hackers),
1384 // filter the set of instruction aliases we consider, based on the target
1386 if (!StringRef(Alias->ResultInst->TheDef->getName())
1387 .startswith( MatchPrefix))
1390 std::unique_ptr<MatchableInfo> II(new MatchableInfo(std::move(Alias)));
1392 II->initialize(*this, SingletonRegisters, AsmVariantNo, RegisterPrefix);
1394 // Validate the alias definitions.
1395 II->validate(CommentDelimiter, false);
1397 Matchables.push_back(std::move(II));
1401 // Build info for the register classes.
1402 buildRegisterClasses(SingletonRegisters);
1404 // Build info for the user defined assembly operand classes.
1405 buildOperandClasses();
1407 // Build the information about matchables, now that we have fully formed
1409 std::vector<std::unique_ptr<MatchableInfo>> NewMatchables;
1410 for (auto &II : Matchables) {
1411 // Parse the tokens after the mnemonic.
1412 // Note: buildInstructionOperandReference may insert new AsmOperands, so
1413 // don't precompute the loop bound.
1414 for (unsigned i = 0; i != II->AsmOperands.size(); ++i) {
1415 MatchableInfo::AsmOperand &Op = II->AsmOperands[i];
1416 StringRef Token = Op.Token;
1418 // Check for singleton registers.
1419 if (Record *RegRecord = II->AsmOperands[i].SingletonReg) {
1420 Op.Class = RegisterClasses[RegRecord];
1421 assert(Op.Class && Op.Class->Registers.size() == 1 &&
1422 "Unexpected class for singleton register");
1426 // Check for simple tokens.
1427 if (Token[0] != '$') {
1428 Op.Class = getTokenClass(Token);
1432 if (Token.size() > 1 && isdigit(Token[1])) {
1433 Op.Class = getTokenClass(Token);
1437 // Otherwise this is an operand reference.
1438 StringRef OperandName;
1439 if (Token[1] == '{')
1440 OperandName = Token.substr(2, Token.size() - 3);
1442 OperandName = Token.substr(1);
1444 if (II->DefRec.is<const CodeGenInstruction*>())
1445 buildInstructionOperandReference(II.get(), OperandName, i);
1447 buildAliasOperandReference(II.get(), OperandName, Op);
1450 if (II->DefRec.is<const CodeGenInstruction*>()) {
1451 II->buildInstructionResultOperands();
1452 // If the instruction has a two-operand alias, build up the
1453 // matchable here. We'll add them in bulk at the end to avoid
1454 // confusing this loop.
1455 std::string Constraint =
1456 II->TheDef->getValueAsString("TwoOperandAliasConstraint");
1457 if (Constraint != "") {
1458 // Start by making a copy of the original matchable.
1459 std::unique_ptr<MatchableInfo> AliasII(new MatchableInfo(*II));
1461 // Adjust it to be a two-operand alias.
1462 AliasII->formTwoOperandAlias(Constraint);
1464 // Add the alias to the matchables list.
1465 NewMatchables.push_back(std::move(AliasII));
1468 II->buildAliasResultOperands();
1470 if (!NewMatchables.empty())
1471 Matchables.insert(Matchables.end(),
1472 std::make_move_iterator(NewMatchables.begin()),
1473 std::make_move_iterator(NewMatchables.end()));
1475 // Process token alias definitions and set up the associated superclass
1477 std::vector<Record*> AllTokenAliases =
1478 Records.getAllDerivedDefinitions("TokenAlias");
1479 for (unsigned i = 0, e = AllTokenAliases.size(); i != e; ++i) {
1480 Record *Rec = AllTokenAliases[i];
1481 ClassInfo *FromClass = getTokenClass(Rec->getValueAsString("FromToken"));
1482 ClassInfo *ToClass = getTokenClass(Rec->getValueAsString("ToToken"));
1483 if (FromClass == ToClass)
1484 PrintFatalError(Rec->getLoc(),
1485 "error: Destination value identical to source value.");
1486 FromClass->SuperClasses.push_back(ToClass);
1489 // Reorder classes so that classes precede super classes.
1493 /// buildInstructionOperandReference - The specified operand is a reference to a
1494 /// named operand such as $src. Resolve the Class and OperandInfo pointers.
1495 void AsmMatcherInfo::
1496 buildInstructionOperandReference(MatchableInfo *II,
1497 StringRef OperandName,
1498 unsigned AsmOpIdx) {
1499 const CodeGenInstruction &CGI = *II->DefRec.get<const CodeGenInstruction*>();
1500 const CGIOperandList &Operands = CGI.Operands;
1501 MatchableInfo::AsmOperand *Op = &II->AsmOperands[AsmOpIdx];
1503 // Map this token to an operand.
1505 if (!Operands.hasOperandNamed(OperandName, Idx))
1506 PrintFatalError(II->TheDef->getLoc(),
1507 "error: unable to find operand: '" + OperandName + "'");
1509 // If the instruction operand has multiple suboperands, but the parser
1510 // match class for the asm operand is still the default "ImmAsmOperand",
1511 // then handle each suboperand separately.
1512 if (Op->SubOpIdx == -1 && Operands[Idx].MINumOperands > 1) {
1513 Record *Rec = Operands[Idx].Rec;
1514 assert(Rec->isSubClassOf("Operand") && "Unexpected operand!");
1515 Record *MatchClass = Rec->getValueAsDef("ParserMatchClass");
1516 if (MatchClass && MatchClass->getValueAsString("Name") == "Imm") {
1517 // Insert remaining suboperands after AsmOpIdx in II->AsmOperands.
1518 StringRef Token = Op->Token; // save this in case Op gets moved
1519 for (unsigned SI = 1, SE = Operands[Idx].MINumOperands; SI != SE; ++SI) {
1520 MatchableInfo::AsmOperand NewAsmOp(Token);
1521 NewAsmOp.SubOpIdx = SI;
1522 II->AsmOperands.insert(II->AsmOperands.begin()+AsmOpIdx+SI, NewAsmOp);
1524 // Replace Op with first suboperand.
1525 Op = &II->AsmOperands[AsmOpIdx]; // update the pointer in case it moved
1530 // Set up the operand class.
1531 Op->Class = getOperandClass(Operands[Idx], Op->SubOpIdx);
1533 // If the named operand is tied, canonicalize it to the untied operand.
1534 // For example, something like:
1535 // (outs GPR:$dst), (ins GPR:$src)
1536 // with an asmstring of
1538 // we want to canonicalize to:
1540 // so that we know how to provide the $dst operand when filling in the result.
1542 if (Operands[Idx].MINumOperands == 1)
1543 OITied = Operands[Idx].getTiedRegister();
1545 // The tied operand index is an MIOperand index, find the operand that
1547 std::pair<unsigned, unsigned> Idx = Operands.getSubOperandNumber(OITied);
1548 OperandName = Operands[Idx.first].Name;
1549 Op->SubOpIdx = Idx.second;
1552 Op->SrcOpName = OperandName;
1555 /// buildAliasOperandReference - When parsing an operand reference out of the
1556 /// matching string (e.g. "movsx $src, $dst"), determine what the class of the
1557 /// operand reference is by looking it up in the result pattern definition.
1558 void AsmMatcherInfo::buildAliasOperandReference(MatchableInfo *II,
1559 StringRef OperandName,
1560 MatchableInfo::AsmOperand &Op) {
1561 const CodeGenInstAlias &CGA = *II->DefRec.get<const CodeGenInstAlias*>();
1563 // Set up the operand class.
1564 for (unsigned i = 0, e = CGA.ResultOperands.size(); i != e; ++i)
1565 if (CGA.ResultOperands[i].isRecord() &&
1566 CGA.ResultOperands[i].getName() == OperandName) {
1567 // It's safe to go with the first one we find, because CodeGenInstAlias
1568 // validates that all operands with the same name have the same record.
1569 Op.SubOpIdx = CGA.ResultInstOperandIndex[i].second;
1570 // Use the match class from the Alias definition, not the
1571 // destination instruction, as we may have an immediate that's
1572 // being munged by the match class.
1573 Op.Class = getOperandClass(CGA.ResultOperands[i].getRecord(),
1575 Op.SrcOpName = OperandName;
1579 PrintFatalError(II->TheDef->getLoc(),
1580 "error: unable to find operand: '" + OperandName + "'");
1583 void MatchableInfo::buildInstructionResultOperands() {
1584 const CodeGenInstruction *ResultInst = getResultInst();
1586 // Loop over all operands of the result instruction, determining how to
1588 for (unsigned i = 0, e = ResultInst->Operands.size(); i != e; ++i) {
1589 const CGIOperandList::OperandInfo &OpInfo = ResultInst->Operands[i];
1591 // If this is a tied operand, just copy from the previously handled operand.
1593 if (OpInfo.MINumOperands == 1)
1594 TiedOp = OpInfo.getTiedRegister();
1596 ResOperands.push_back(ResOperand::getTiedOp(TiedOp));
1600 // Find out what operand from the asmparser this MCInst operand comes from.
1601 int SrcOperand = findAsmOperandNamed(OpInfo.Name);
1602 if (OpInfo.Name.empty() || SrcOperand == -1) {
1603 // This may happen for operands that are tied to a suboperand of a
1604 // complex operand. Simply use a dummy value here; nobody should
1605 // use this operand slot.
1606 // FIXME: The long term goal is for the MCOperand list to not contain
1607 // tied operands at all.
1608 ResOperands.push_back(ResOperand::getImmOp(0));
1612 // Check if the one AsmOperand populates the entire operand.
1613 unsigned NumOperands = OpInfo.MINumOperands;
1614 if (AsmOperands[SrcOperand].SubOpIdx == -1) {
1615 ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand, NumOperands));
1619 // Add a separate ResOperand for each suboperand.
1620 for (unsigned AI = 0; AI < NumOperands; ++AI) {
1621 assert(AsmOperands[SrcOperand+AI].SubOpIdx == (int)AI &&
1622 AsmOperands[SrcOperand+AI].SrcOpName == OpInfo.Name &&
1623 "unexpected AsmOperands for suboperands");
1624 ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand + AI, 1));
1629 void MatchableInfo::buildAliasResultOperands() {
1630 const CodeGenInstAlias &CGA = *DefRec.get<const CodeGenInstAlias*>();
1631 const CodeGenInstruction *ResultInst = getResultInst();
1633 // Loop over all operands of the result instruction, determining how to
1635 unsigned AliasOpNo = 0;
1636 unsigned LastOpNo = CGA.ResultInstOperandIndex.size();
1637 for (unsigned i = 0, e = ResultInst->Operands.size(); i != e; ++i) {
1638 const CGIOperandList::OperandInfo *OpInfo = &ResultInst->Operands[i];
1640 // If this is a tied operand, just copy from the previously handled operand.
1642 if (OpInfo->MINumOperands == 1)
1643 TiedOp = OpInfo->getTiedRegister();
1645 ResOperands.push_back(ResOperand::getTiedOp(TiedOp));
1649 // Handle all the suboperands for this operand.
1650 const std::string &OpName = OpInfo->Name;
1651 for ( ; AliasOpNo < LastOpNo &&
1652 CGA.ResultInstOperandIndex[AliasOpNo].first == i; ++AliasOpNo) {
1653 int SubIdx = CGA.ResultInstOperandIndex[AliasOpNo].second;
1655 // Find out what operand from the asmparser that this MCInst operand
1657 switch (CGA.ResultOperands[AliasOpNo].Kind) {
1658 case CodeGenInstAlias::ResultOperand::K_Record: {
1659 StringRef Name = CGA.ResultOperands[AliasOpNo].getName();
1660 int SrcOperand = findAsmOperand(Name, SubIdx);
1661 if (SrcOperand == -1)
1662 PrintFatalError(TheDef->getLoc(), "Instruction '" +
1663 TheDef->getName() + "' has operand '" + OpName +
1664 "' that doesn't appear in asm string!");
1665 unsigned NumOperands = (SubIdx == -1 ? OpInfo->MINumOperands : 1);
1666 ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand,
1670 case CodeGenInstAlias::ResultOperand::K_Imm: {
1671 int64_t ImmVal = CGA.ResultOperands[AliasOpNo].getImm();
1672 ResOperands.push_back(ResOperand::getImmOp(ImmVal));
1675 case CodeGenInstAlias::ResultOperand::K_Reg: {
1676 Record *Reg = CGA.ResultOperands[AliasOpNo].getRegister();
1677 ResOperands.push_back(ResOperand::getRegOp(Reg));
1685 static unsigned getConverterOperandID(const std::string &Name,
1686 SetVector<std::string> &Table,
1688 IsNew = Table.insert(Name);
1690 unsigned ID = IsNew ? Table.size() - 1 :
1691 std::find(Table.begin(), Table.end(), Name) - Table.begin();
1693 assert(ID < Table.size());
1699 static void emitConvertFuncs(CodeGenTarget &Target, StringRef ClassName,
1700 std::vector<std::unique_ptr<MatchableInfo>> &Infos,
1702 SetVector<std::string> OperandConversionKinds;
1703 SetVector<std::string> InstructionConversionKinds;
1704 std::vector<std::vector<uint8_t> > ConversionTable;
1705 size_t MaxRowLength = 2; // minimum is custom converter plus terminator.
1707 // TargetOperandClass - This is the target's operand class, like X86Operand.
1708 std::string TargetOperandClass = Target.getName() + "Operand";
1710 // Write the convert function to a separate stream, so we can drop it after
1711 // the enum. We'll build up the conversion handlers for the individual
1712 // operand types opportunistically as we encounter them.
1713 std::string ConvertFnBody;
1714 raw_string_ostream CvtOS(ConvertFnBody);
1715 // Start the unified conversion function.
1716 CvtOS << "void " << Target.getName() << ClassName << "::\n"
1717 << "convertToMCInst(unsigned Kind, MCInst &Inst, "
1718 << "unsigned Opcode,\n"
1719 << " const OperandVector"
1720 << " &Operands) {\n"
1721 << " assert(Kind < CVT_NUM_SIGNATURES && \"Invalid signature!\");\n"
1722 << " const uint8_t *Converter = ConversionTable[Kind];\n"
1723 << " Inst.setOpcode(Opcode);\n"
1724 << " for (const uint8_t *p = Converter; *p; p+= 2) {\n"
1725 << " switch (*p) {\n"
1726 << " default: llvm_unreachable(\"invalid conversion entry!\");\n"
1727 << " case CVT_Reg:\n"
1728 << " static_cast<" << TargetOperandClass
1729 << "&>(*Operands[*(p + 1)]).addRegOperands(Inst, 1);\n"
1731 << " case CVT_Tied:\n"
1732 << " Inst.addOperand(Inst.getOperand(*(p + 1)));\n"
1735 std::string OperandFnBody;
1736 raw_string_ostream OpOS(OperandFnBody);
1737 // Start the operand number lookup function.
1738 OpOS << "void " << Target.getName() << ClassName << "::\n"
1739 << "convertToMapAndConstraints(unsigned Kind,\n";
1741 OpOS << "const OperandVector &Operands) {\n"
1742 << " assert(Kind < CVT_NUM_SIGNATURES && \"Invalid signature!\");\n"
1743 << " unsigned NumMCOperands = 0;\n"
1744 << " const uint8_t *Converter = ConversionTable[Kind];\n"
1745 << " for (const uint8_t *p = Converter; *p; p+= 2) {\n"
1746 << " switch (*p) {\n"
1747 << " default: llvm_unreachable(\"invalid conversion entry!\");\n"
1748 << " case CVT_Reg:\n"
1749 << " Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n"
1750 << " Operands[*(p + 1)]->setConstraint(\"r\");\n"
1751 << " ++NumMCOperands;\n"
1753 << " case CVT_Tied:\n"
1754 << " ++NumMCOperands;\n"
1757 // Pre-populate the operand conversion kinds with the standard always
1758 // available entries.
1759 OperandConversionKinds.insert("CVT_Done");
1760 OperandConversionKinds.insert("CVT_Reg");
1761 OperandConversionKinds.insert("CVT_Tied");
1762 enum { CVT_Done, CVT_Reg, CVT_Tied };
1764 for (auto &II : Infos) {
1765 // Check if we have a custom match function.
1766 std::string AsmMatchConverter =
1767 II->getResultInst()->TheDef->getValueAsString("AsmMatchConverter");
1768 if (!AsmMatchConverter.empty() && II->UseInstAsmMatchConverter) {
1769 std::string Signature = "ConvertCustom_" + AsmMatchConverter;
1770 II->ConversionFnKind = Signature;
1772 // Check if we have already generated this signature.
1773 if (!InstructionConversionKinds.insert(Signature))
1776 // Remember this converter for the kind enum.
1777 unsigned KindID = OperandConversionKinds.size();
1778 OperandConversionKinds.insert("CVT_" +
1779 getEnumNameForToken(AsmMatchConverter));
1781 // Add the converter row for this instruction.
1782 ConversionTable.push_back(std::vector<uint8_t>());
1783 ConversionTable.back().push_back(KindID);
1784 ConversionTable.back().push_back(CVT_Done);
1786 // Add the handler to the conversion driver function.
1787 CvtOS << " case CVT_"
1788 << getEnumNameForToken(AsmMatchConverter) << ":\n"
1789 << " " << AsmMatchConverter << "(Inst, Operands);\n"
1792 // FIXME: Handle the operand number lookup for custom match functions.
1796 // Build the conversion function signature.
1797 std::string Signature = "Convert";
1799 std::vector<uint8_t> ConversionRow;
1801 // Compute the convert enum and the case body.
1802 MaxRowLength = std::max(MaxRowLength, II->ResOperands.size()*2 + 1 );
1804 for (unsigned i = 0, e = II->ResOperands.size(); i != e; ++i) {
1805 const MatchableInfo::ResOperand &OpInfo = II->ResOperands[i];
1807 // Generate code to populate each result operand.
1808 switch (OpInfo.Kind) {
1809 case MatchableInfo::ResOperand::RenderAsmOperand: {
1810 // This comes from something we parsed.
1811 const MatchableInfo::AsmOperand &Op =
1812 II->AsmOperands[OpInfo.AsmOperandNum];
1814 // Registers are always converted the same, don't duplicate the
1815 // conversion function based on them.
1818 Class = Op.Class->isRegisterClass() ? "Reg" : Op.Class->ClassName;
1820 Signature += utostr(OpInfo.MINumOperands);
1821 Signature += "_" + itostr(OpInfo.AsmOperandNum);
1823 // Add the conversion kind, if necessary, and get the associated ID
1824 // the index of its entry in the vector).
1825 std::string Name = "CVT_" + (Op.Class->isRegisterClass() ? "Reg" :
1826 Op.Class->RenderMethod);
1827 Name = getEnumNameForToken(Name);
1829 bool IsNewConverter = false;
1830 unsigned ID = getConverterOperandID(Name, OperandConversionKinds,
1833 // Add the operand entry to the instruction kind conversion row.
1834 ConversionRow.push_back(ID);
1835 ConversionRow.push_back(OpInfo.AsmOperandNum + 1);
1837 if (!IsNewConverter)
1840 // This is a new operand kind. Add a handler for it to the
1841 // converter driver.
1842 CvtOS << " case " << Name << ":\n"
1843 << " static_cast<" << TargetOperandClass
1844 << "&>(*Operands[*(p + 1)])." << Op.Class->RenderMethod
1845 << "(Inst, " << OpInfo.MINumOperands << ");\n"
1848 // Add a handler for the operand number lookup.
1849 OpOS << " case " << Name << ":\n"
1850 << " Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n";
1852 if (Op.Class->isRegisterClass())
1853 OpOS << " Operands[*(p + 1)]->setConstraint(\"r\");\n";
1855 OpOS << " Operands[*(p + 1)]->setConstraint(\"m\");\n";
1856 OpOS << " NumMCOperands += " << OpInfo.MINumOperands << ";\n"
1860 case MatchableInfo::ResOperand::TiedOperand: {
1861 // If this operand is tied to a previous one, just copy the MCInst
1862 // operand from the earlier one.We can only tie single MCOperand values.
1863 assert(OpInfo.MINumOperands == 1 && "Not a singular MCOperand");
1864 unsigned TiedOp = OpInfo.TiedOperandNum;
1865 assert(i > TiedOp && "Tied operand precedes its target!");
1866 Signature += "__Tie" + utostr(TiedOp);
1867 ConversionRow.push_back(CVT_Tied);
1868 ConversionRow.push_back(TiedOp);
1871 case MatchableInfo::ResOperand::ImmOperand: {
1872 int64_t Val = OpInfo.ImmVal;
1873 std::string Ty = "imm_" + itostr(Val);
1874 Ty = getEnumNameForToken(Ty);
1875 Signature += "__" + Ty;
1877 std::string Name = "CVT_" + Ty;
1878 bool IsNewConverter = false;
1879 unsigned ID = getConverterOperandID(Name, OperandConversionKinds,
1881 // Add the operand entry to the instruction kind conversion row.
1882 ConversionRow.push_back(ID);
1883 ConversionRow.push_back(0);
1885 if (!IsNewConverter)
1888 CvtOS << " case " << Name << ":\n"
1889 << " Inst.addOperand(MCOperand::createImm(" << Val << "));\n"
1892 OpOS << " case " << Name << ":\n"
1893 << " Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n"
1894 << " Operands[*(p + 1)]->setConstraint(\"\");\n"
1895 << " ++NumMCOperands;\n"
1899 case MatchableInfo::ResOperand::RegOperand: {
1900 std::string Reg, Name;
1901 if (!OpInfo.Register) {
1905 Reg = getQualifiedName(OpInfo.Register);
1906 Name = "reg" + OpInfo.Register->getName();
1908 Signature += "__" + Name;
1909 Name = "CVT_" + Name;
1910 bool IsNewConverter = false;
1911 unsigned ID = getConverterOperandID(Name, OperandConversionKinds,
1913 // Add the operand entry to the instruction kind conversion row.
1914 ConversionRow.push_back(ID);
1915 ConversionRow.push_back(0);
1917 if (!IsNewConverter)
1919 CvtOS << " case " << Name << ":\n"
1920 << " Inst.addOperand(MCOperand::createReg(" << Reg << "));\n"
1923 OpOS << " case " << Name << ":\n"
1924 << " Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n"
1925 << " Operands[*(p + 1)]->setConstraint(\"m\");\n"
1926 << " ++NumMCOperands;\n"
1932 // If there were no operands, add to the signature to that effect
1933 if (Signature == "Convert")
1934 Signature += "_NoOperands";
1936 II->ConversionFnKind = Signature;
1938 // Save the signature. If we already have it, don't add a new row
1940 if (!InstructionConversionKinds.insert(Signature))
1943 // Add the row to the table.
1944 ConversionTable.push_back(ConversionRow);
1947 // Finish up the converter driver function.
1948 CvtOS << " }\n }\n}\n\n";
1950 // Finish up the operand number lookup function.
1951 OpOS << " }\n }\n}\n\n";
1953 OS << "namespace {\n";
1955 // Output the operand conversion kind enum.
1956 OS << "enum OperatorConversionKind {\n";
1957 for (unsigned i = 0, e = OperandConversionKinds.size(); i != e; ++i)
1958 OS << " " << OperandConversionKinds[i] << ",\n";
1959 OS << " CVT_NUM_CONVERTERS\n";
1962 // Output the instruction conversion kind enum.
1963 OS << "enum InstructionConversionKind {\n";
1964 for (SetVector<std::string>::const_iterator
1965 i = InstructionConversionKinds.begin(),
1966 e = InstructionConversionKinds.end(); i != e; ++i)
1967 OS << " " << *i << ",\n";
1968 OS << " CVT_NUM_SIGNATURES\n";
1972 OS << "} // end anonymous namespace\n\n";
1974 // Output the conversion table.
1975 OS << "static const uint8_t ConversionTable[CVT_NUM_SIGNATURES]["
1976 << MaxRowLength << "] = {\n";
1978 for (unsigned Row = 0, ERow = ConversionTable.size(); Row != ERow; ++Row) {
1979 assert(ConversionTable[Row].size() % 2 == 0 && "bad conversion row!");
1980 OS << " // " << InstructionConversionKinds[Row] << "\n";
1982 for (unsigned i = 0, e = ConversionTable[Row].size(); i != e; i += 2)
1983 OS << OperandConversionKinds[ConversionTable[Row][i]] << ", "
1984 << (unsigned)(ConversionTable[Row][i + 1]) << ", ";
1985 OS << "CVT_Done },\n";
1990 // Spit out the conversion driver function.
1993 // Spit out the operand number lookup function.
1997 /// emitMatchClassEnumeration - Emit the enumeration for match class kinds.
1998 static void emitMatchClassEnumeration(CodeGenTarget &Target,
1999 std::forward_list<ClassInfo> &Infos,
2001 OS << "namespace {\n\n";
2003 OS << "/// MatchClassKind - The kinds of classes which participate in\n"
2004 << "/// instruction matching.\n";
2005 OS << "enum MatchClassKind {\n";
2006 OS << " InvalidMatchClass = 0,\n";
2007 for (const auto &CI : Infos) {
2008 OS << " " << CI.Name << ", // ";
2009 if (CI.Kind == ClassInfo::Token) {
2010 OS << "'" << CI.ValueName << "'\n";
2011 } else if (CI.isRegisterClass()) {
2012 if (!CI.ValueName.empty())
2013 OS << "register class '" << CI.ValueName << "'\n";
2015 OS << "derived register class\n";
2017 OS << "user defined class '" << CI.ValueName << "'\n";
2020 OS << " NumMatchClassKinds\n";
2026 /// emitValidateOperandClass - Emit the function to validate an operand class.
2027 static void emitValidateOperandClass(AsmMatcherInfo &Info,
2029 OS << "static unsigned validateOperandClass(MCParsedAsmOperand &GOp, "
2030 << "MatchClassKind Kind) {\n";
2031 OS << " " << Info.Target.getName() << "Operand &Operand = ("
2032 << Info.Target.getName() << "Operand&)GOp;\n";
2034 // The InvalidMatchClass is not to match any operand.
2035 OS << " if (Kind == InvalidMatchClass)\n";
2036 OS << " return MCTargetAsmParser::Match_InvalidOperand;\n\n";
2038 // Check for Token operands first.
2039 // FIXME: Use a more specific diagnostic type.
2040 OS << " if (Operand.isToken())\n";
2041 OS << " return isSubclass(matchTokenString(Operand.getToken()), Kind) ?\n"
2042 << " MCTargetAsmParser::Match_Success :\n"
2043 << " MCTargetAsmParser::Match_InvalidOperand;\n\n";
2045 // Check the user classes. We don't care what order since we're only
2046 // actually matching against one of them.
2047 for (const auto &CI : Info.Classes) {
2048 if (!CI.isUserClass())
2051 OS << " // '" << CI.ClassName << "' class\n";
2052 OS << " if (Kind == " << CI.Name << ") {\n";
2053 OS << " if (Operand." << CI.PredicateMethod << "())\n";
2054 OS << " return MCTargetAsmParser::Match_Success;\n";
2055 if (!CI.DiagnosticType.empty())
2056 OS << " return " << Info.Target.getName() << "AsmParser::Match_"
2057 << CI.DiagnosticType << ";\n";
2061 // Check for register operands, including sub-classes.
2062 OS << " if (Operand.isReg()) {\n";
2063 OS << " MatchClassKind OpKind;\n";
2064 OS << " switch (Operand.getReg()) {\n";
2065 OS << " default: OpKind = InvalidMatchClass; break;\n";
2066 for (const auto &RC : Info.RegisterClasses)
2067 OS << " case " << Info.Target.getName() << "::"
2068 << RC.first->getName() << ": OpKind = " << RC.second->Name
2071 OS << " return isSubclass(OpKind, Kind) ? "
2072 << "MCTargetAsmParser::Match_Success :\n "
2073 << " MCTargetAsmParser::Match_InvalidOperand;\n }\n\n";
2075 // Generic fallthrough match failure case for operands that don't have
2076 // specialized diagnostic types.
2077 OS << " return MCTargetAsmParser::Match_InvalidOperand;\n";
2081 /// emitIsSubclass - Emit the subclass predicate function.
2082 static void emitIsSubclass(CodeGenTarget &Target,
2083 std::forward_list<ClassInfo> &Infos,
2085 OS << "/// isSubclass - Compute whether \\p A is a subclass of \\p B.\n";
2086 OS << "static bool isSubclass(MatchClassKind A, MatchClassKind B) {\n";
2087 OS << " if (A == B)\n";
2088 OS << " return true;\n\n";
2091 raw_string_ostream SS(OStr);
2093 SS << " switch (A) {\n";
2094 SS << " default:\n";
2095 SS << " return false;\n";
2096 for (const auto &A : Infos) {
2097 std::vector<StringRef> SuperClasses;
2098 for (const auto &B : Infos) {
2099 if (&A != &B && A.isSubsetOf(B))
2100 SuperClasses.push_back(B.Name);
2103 if (SuperClasses.empty())
2107 SS << "\n case " << A.Name << ":\n";
2109 if (SuperClasses.size() == 1) {
2110 SS << " return B == " << SuperClasses.back().str() << ";\n";
2114 if (!SuperClasses.empty()) {
2115 SS << " switch (B) {\n";
2116 SS << " default: return false;\n";
2117 for (unsigned i = 0, e = SuperClasses.size(); i != e; ++i)
2118 SS << " case " << SuperClasses[i].str() << ": return true;\n";
2121 // No case statement to emit
2122 SS << " return false;\n";
2127 // If there were case statements emitted into the string stream, write them
2128 // to the output stream, otherwise write the default.
2132 OS << " return false;\n";
2137 /// emitMatchTokenString - Emit the function to match a token string to the
2138 /// appropriate match class value.
2139 static void emitMatchTokenString(CodeGenTarget &Target,
2140 std::forward_list<ClassInfo> &Infos,
2142 // Construct the match list.
2143 std::vector<StringMatcher::StringPair> Matches;
2144 for (const auto &CI : Infos) {
2145 if (CI.Kind == ClassInfo::Token)
2147 StringMatcher::StringPair(CI.ValueName, "return " + CI.Name + ";"));
2150 OS << "static MatchClassKind matchTokenString(StringRef Name) {\n";
2152 StringMatcher("Name", Matches, OS).Emit();
2154 OS << " return InvalidMatchClass;\n";
2158 /// emitMatchRegisterName - Emit the function to match a string to the target
2159 /// specific register enum.
2160 static void emitMatchRegisterName(CodeGenTarget &Target, Record *AsmParser,
2162 // Construct the match list.
2163 std::vector<StringMatcher::StringPair> Matches;
2164 const auto &Regs = Target.getRegBank().getRegisters();
2165 for (const CodeGenRegister &Reg : Regs) {
2166 if (Reg.TheDef->getValueAsString("AsmName").empty())
2170 StringMatcher::StringPair(Reg.TheDef->getValueAsString("AsmName"),
2171 "return " + utostr(Reg.EnumValue) + ";"));
2174 OS << "static unsigned MatchRegisterName(StringRef Name) {\n";
2176 StringMatcher("Name", Matches, OS).Emit();
2178 OS << " return 0;\n";
2182 static const char *getMinimalTypeForRange(uint64_t Range) {
2183 assert(Range <= 0xFFFFFFFFFFFFFFFFULL && "Enum too large");
2184 if (Range > 0xFFFFFFFFULL)
2193 static const char *getMinimalRequiredFeaturesType(const AsmMatcherInfo &Info) {
2194 uint64_t MaxIndex = Info.SubtargetFeatures.size();
2197 return getMinimalTypeForRange(1ULL << MaxIndex);
2200 /// emitSubtargetFeatureFlagEnumeration - Emit the subtarget feature flag
2202 static void emitSubtargetFeatureFlagEnumeration(AsmMatcherInfo &Info,
2204 OS << "// Flags for subtarget features that participate in "
2205 << "instruction matching.\n";
2206 OS << "enum SubtargetFeatureFlag : " << getMinimalRequiredFeaturesType(Info)
2208 for (const auto &SF : Info.SubtargetFeatures) {
2209 const SubtargetFeatureInfo &SFI = SF.second;
2210 OS << " " << SFI.getEnumName() << " = (1ULL << " << SFI.Index << "),\n";
2212 OS << " Feature_None = 0\n";
2216 /// emitOperandDiagnosticTypes - Emit the operand matching diagnostic types.
2217 static void emitOperandDiagnosticTypes(AsmMatcherInfo &Info, raw_ostream &OS) {
2218 // Get the set of diagnostic types from all of the operand classes.
2219 std::set<StringRef> Types;
2220 for (std::map<Record*, ClassInfo*>::const_iterator
2221 I = Info.AsmOperandClasses.begin(),
2222 E = Info.AsmOperandClasses.end(); I != E; ++I) {
2223 if (!I->second->DiagnosticType.empty())
2224 Types.insert(I->second->DiagnosticType);
2227 if (Types.empty()) return;
2229 // Now emit the enum entries.
2230 for (std::set<StringRef>::const_iterator I = Types.begin(), E = Types.end();
2232 OS << " Match_" << *I << ",\n";
2233 OS << " END_OPERAND_DIAGNOSTIC_TYPES\n";
2236 /// emitGetSubtargetFeatureName - Emit the helper function to get the
2237 /// user-level name for a subtarget feature.
2238 static void emitGetSubtargetFeatureName(AsmMatcherInfo &Info, raw_ostream &OS) {
2239 OS << "// User-level names for subtarget features that participate in\n"
2240 << "// instruction matching.\n"
2241 << "static const char *getSubtargetFeatureName(uint64_t Val) {\n";
2242 if (!Info.SubtargetFeatures.empty()) {
2243 OS << " switch(Val) {\n";
2244 for (const auto &SF : Info.SubtargetFeatures) {
2245 const SubtargetFeatureInfo &SFI = SF.second;
2246 // FIXME: Totally just a placeholder name to get the algorithm working.
2247 OS << " case " << SFI.getEnumName() << ": return \""
2248 << SFI.TheDef->getValueAsString("PredicateName") << "\";\n";
2250 OS << " default: return \"(unknown)\";\n";
2253 // Nothing to emit, so skip the switch
2254 OS << " return \"(unknown)\";\n";
2259 /// emitComputeAvailableFeatures - Emit the function to compute the list of
2260 /// available features given a subtarget.
2261 static void emitComputeAvailableFeatures(AsmMatcherInfo &Info,
2263 std::string ClassName =
2264 Info.AsmParser->getValueAsString("AsmParserClassName");
2266 OS << "uint64_t " << Info.Target.getName() << ClassName << "::\n"
2267 << "ComputeAvailableFeatures(const FeatureBitset& FB) const {\n";
2268 OS << " uint64_t Features = 0;\n";
2269 for (const auto &SF : Info.SubtargetFeatures) {
2270 const SubtargetFeatureInfo &SFI = SF.second;
2273 std::string CondStorage =
2274 SFI.TheDef->getValueAsString("AssemblerCondString");
2275 StringRef Conds = CondStorage;
2276 std::pair<StringRef,StringRef> Comma = Conds.split(',');
2283 StringRef Cond = Comma.first;
2284 if (Cond[0] == '!') {
2286 Cond = Cond.substr(1);
2292 OS << "FB[" << Info.Target.getName() << "::" << Cond << "])";
2294 if (Comma.second.empty())
2298 Comma = Comma.second.split(',');
2302 OS << " Features |= " << SFI.getEnumName() << ";\n";
2304 OS << " return Features;\n";
2308 static std::string GetAliasRequiredFeatures(Record *R,
2309 const AsmMatcherInfo &Info) {
2310 std::vector<Record*> ReqFeatures = R->getValueAsListOfDefs("Predicates");
2312 unsigned NumFeatures = 0;
2313 for (unsigned i = 0, e = ReqFeatures.size(); i != e; ++i) {
2314 const SubtargetFeatureInfo *F = Info.getSubtargetFeature(ReqFeatures[i]);
2317 PrintFatalError(R->getLoc(), "Predicate '" + ReqFeatures[i]->getName() +
2318 "' is not marked as an AssemblerPredicate!");
2323 Result += F->getEnumName();
2327 if (NumFeatures > 1)
2328 Result = '(' + Result + ')';
2332 static void emitMnemonicAliasVariant(raw_ostream &OS,const AsmMatcherInfo &Info,
2333 std::vector<Record*> &Aliases,
2334 unsigned Indent = 0,
2335 StringRef AsmParserVariantName = StringRef()){
2336 // Keep track of all the aliases from a mnemonic. Use an std::map so that the
2337 // iteration order of the map is stable.
2338 std::map<std::string, std::vector<Record*> > AliasesFromMnemonic;
2340 for (unsigned i = 0, e = Aliases.size(); i != e; ++i) {
2341 Record *R = Aliases[i];
2342 // FIXME: Allow AssemblerVariantName to be a comma separated list.
2343 std::string AsmVariantName = R->getValueAsString("AsmVariantName");
2344 if (AsmVariantName != AsmParserVariantName)
2346 AliasesFromMnemonic[R->getValueAsString("FromMnemonic")].push_back(R);
2348 if (AliasesFromMnemonic.empty())
2351 // Process each alias a "from" mnemonic at a time, building the code executed
2352 // by the string remapper.
2353 std::vector<StringMatcher::StringPair> Cases;
2354 for (std::map<std::string, std::vector<Record*> >::iterator
2355 I = AliasesFromMnemonic.begin(), E = AliasesFromMnemonic.end();
2357 const std::vector<Record*> &ToVec = I->second;
2359 // Loop through each alias and emit code that handles each case. If there
2360 // are two instructions without predicates, emit an error. If there is one,
2362 std::string MatchCode;
2363 int AliasWithNoPredicate = -1;
2365 for (unsigned i = 0, e = ToVec.size(); i != e; ++i) {
2366 Record *R = ToVec[i];
2367 std::string FeatureMask = GetAliasRequiredFeatures(R, Info);
2369 // If this unconditionally matches, remember it for later and diagnose
2371 if (FeatureMask.empty()) {
2372 if (AliasWithNoPredicate != -1) {
2373 // We can't have two aliases from the same mnemonic with no predicate.
2374 PrintError(ToVec[AliasWithNoPredicate]->getLoc(),
2375 "two MnemonicAliases with the same 'from' mnemonic!");
2376 PrintFatalError(R->getLoc(), "this is the other MnemonicAlias.");
2379 AliasWithNoPredicate = i;
2382 if (R->getValueAsString("ToMnemonic") == I->first)
2383 PrintFatalError(R->getLoc(), "MnemonicAlias to the same string");
2385 if (!MatchCode.empty())
2386 MatchCode += "else ";
2387 MatchCode += "if ((Features & " + FeatureMask + ") == "+FeatureMask+")\n";
2388 MatchCode += " Mnemonic = \"" +R->getValueAsString("ToMnemonic")+"\";\n";
2391 if (AliasWithNoPredicate != -1) {
2392 Record *R = ToVec[AliasWithNoPredicate];
2393 if (!MatchCode.empty())
2394 MatchCode += "else\n ";
2395 MatchCode += "Mnemonic = \"" + R->getValueAsString("ToMnemonic")+"\";\n";
2398 MatchCode += "return;";
2400 Cases.push_back(std::make_pair(I->first, MatchCode));
2402 StringMatcher("Mnemonic", Cases, OS).Emit(Indent);
2405 /// emitMnemonicAliases - If the target has any MnemonicAlias<> definitions,
2406 /// emit a function for them and return true, otherwise return false.
2407 static bool emitMnemonicAliases(raw_ostream &OS, const AsmMatcherInfo &Info,
2408 CodeGenTarget &Target) {
2409 // Ignore aliases when match-prefix is set.
2410 if (!MatchPrefix.empty())
2413 std::vector<Record*> Aliases =
2414 Info.getRecords().getAllDerivedDefinitions("MnemonicAlias");
2415 if (Aliases.empty()) return false;
2417 OS << "static void applyMnemonicAliases(StringRef &Mnemonic, "
2418 "uint64_t Features, unsigned VariantID) {\n";
2419 OS << " switch (VariantID) {\n";
2420 unsigned VariantCount = Target.getAsmParserVariantCount();
2421 for (unsigned VC = 0; VC != VariantCount; ++VC) {
2422 Record *AsmVariant = Target.getAsmParserVariant(VC);
2423 int AsmParserVariantNo = AsmVariant->getValueAsInt("Variant");
2424 std::string AsmParserVariantName = AsmVariant->getValueAsString("Name");
2425 OS << " case " << AsmParserVariantNo << ":\n";
2426 emitMnemonicAliasVariant(OS, Info, Aliases, /*Indent=*/2,
2427 AsmParserVariantName);
2432 // Emit aliases that apply to all variants.
2433 emitMnemonicAliasVariant(OS, Info, Aliases);
2440 static void emitCustomOperandParsing(raw_ostream &OS, CodeGenTarget &Target,
2441 const AsmMatcherInfo &Info, StringRef ClassName,
2442 StringToOffsetTable &StringTable,
2443 unsigned MaxMnemonicIndex) {
2444 unsigned MaxMask = 0;
2445 for (std::vector<OperandMatchEntry>::const_iterator it =
2446 Info.OperandMatchInfo.begin(), ie = Info.OperandMatchInfo.end();
2448 MaxMask |= it->OperandMask;
2451 // Emit the static custom operand parsing table;
2452 OS << "namespace {\n";
2453 OS << " struct OperandMatchEntry {\n";
2454 OS << " " << getMinimalRequiredFeaturesType(Info)
2455 << " RequiredFeatures;\n";
2456 OS << " " << getMinimalTypeForRange(MaxMnemonicIndex)
2458 OS << " " << getMinimalTypeForRange(std::distance(
2459 Info.Classes.begin(), Info.Classes.end())) << " Class;\n";
2460 OS << " " << getMinimalTypeForRange(MaxMask)
2461 << " OperandMask;\n\n";
2462 OS << " StringRef getMnemonic() const {\n";
2463 OS << " return StringRef(MnemonicTable + Mnemonic + 1,\n";
2464 OS << " MnemonicTable[Mnemonic]);\n";
2468 OS << " // Predicate for searching for an opcode.\n";
2469 OS << " struct LessOpcodeOperand {\n";
2470 OS << " bool operator()(const OperandMatchEntry &LHS, StringRef RHS) {\n";
2471 OS << " return LHS.getMnemonic() < RHS;\n";
2473 OS << " bool operator()(StringRef LHS, const OperandMatchEntry &RHS) {\n";
2474 OS << " return LHS < RHS.getMnemonic();\n";
2476 OS << " bool operator()(const OperandMatchEntry &LHS,";
2477 OS << " const OperandMatchEntry &RHS) {\n";
2478 OS << " return LHS.getMnemonic() < RHS.getMnemonic();\n";
2482 OS << "} // end anonymous namespace.\n\n";
2484 OS << "static const OperandMatchEntry OperandMatchTable["
2485 << Info.OperandMatchInfo.size() << "] = {\n";
2487 OS << " /* Operand List Mask, Mnemonic, Operand Class, Features */\n";
2488 for (std::vector<OperandMatchEntry>::const_iterator it =
2489 Info.OperandMatchInfo.begin(), ie = Info.OperandMatchInfo.end();
2491 const OperandMatchEntry &OMI = *it;
2492 const MatchableInfo &II = *OMI.MI;
2496 // Write the required features mask.
2497 if (!II.RequiredFeatures.empty()) {
2498 for (unsigned i = 0, e = II.RequiredFeatures.size(); i != e; ++i) {
2500 OS << II.RequiredFeatures[i]->getEnumName();
2505 // Store a pascal-style length byte in the mnemonic.
2506 std::string LenMnemonic = char(II.Mnemonic.size()) + II.Mnemonic.str();
2507 OS << ", " << StringTable.GetOrAddStringOffset(LenMnemonic, false)
2508 << " /* " << II.Mnemonic << " */, ";
2512 OS << ", " << OMI.OperandMask;
2514 bool printComma = false;
2515 for (int i = 0, e = 31; i !=e; ++i)
2516 if (OMI.OperandMask & (1 << i)) {
2528 // Emit the operand class switch to call the correct custom parser for
2529 // the found operand class.
2530 OS << Target.getName() << ClassName << "::OperandMatchResultTy "
2531 << Target.getName() << ClassName << "::\n"
2532 << "tryCustomParseOperand(OperandVector"
2533 << " &Operands,\n unsigned MCK) {\n\n"
2534 << " switch(MCK) {\n";
2536 for (const auto &CI : Info.Classes) {
2537 if (CI.ParserMethod.empty())
2539 OS << " case " << CI.Name << ":\n"
2540 << " return " << CI.ParserMethod << "(Operands);\n";
2543 OS << " default:\n";
2544 OS << " return MatchOperand_NoMatch;\n";
2546 OS << " return MatchOperand_NoMatch;\n";
2549 // Emit the static custom operand parser. This code is very similar with
2550 // the other matcher. Also use MatchResultTy here just in case we go for
2551 // a better error handling.
2552 OS << Target.getName() << ClassName << "::OperandMatchResultTy "
2553 << Target.getName() << ClassName << "::\n"
2554 << "MatchOperandParserImpl(OperandVector"
2555 << " &Operands,\n StringRef Mnemonic) {\n";
2557 // Emit code to get the available features.
2558 OS << " // Get the current feature set.\n";
2559 OS << " uint64_t AvailableFeatures = getAvailableFeatures();\n\n";
2561 OS << " // Get the next operand index.\n";
2562 OS << " unsigned NextOpNum = Operands.size()-1;\n";
2564 // Emit code to search the table.
2565 OS << " // Search the table.\n";
2566 OS << " std::pair<const OperandMatchEntry*, const OperandMatchEntry*>";
2567 OS << " MnemonicRange =\n";
2568 OS << " std::equal_range(OperandMatchTable, OperandMatchTable+"
2569 << Info.OperandMatchInfo.size() << ", Mnemonic,\n"
2570 << " LessOpcodeOperand());\n\n";
2572 OS << " if (MnemonicRange.first == MnemonicRange.second)\n";
2573 OS << " return MatchOperand_NoMatch;\n\n";
2575 OS << " for (const OperandMatchEntry *it = MnemonicRange.first,\n"
2576 << " *ie = MnemonicRange.second; it != ie; ++it) {\n";
2578 OS << " // equal_range guarantees that instruction mnemonic matches.\n";
2579 OS << " assert(Mnemonic == it->getMnemonic());\n\n";
2581 // Emit check that the required features are available.
2582 OS << " // check if the available features match\n";
2583 OS << " if ((AvailableFeatures & it->RequiredFeatures) "
2584 << "!= it->RequiredFeatures) {\n";
2585 OS << " continue;\n";
2588 // Emit check to ensure the operand number matches.
2589 OS << " // check if the operand in question has a custom parser.\n";
2590 OS << " if (!(it->OperandMask & (1 << NextOpNum)))\n";
2591 OS << " continue;\n\n";
2593 // Emit call to the custom parser method
2594 OS << " // call custom parse method to handle the operand\n";
2595 OS << " OperandMatchResultTy Result = ";
2596 OS << "tryCustomParseOperand(Operands, it->Class);\n";
2597 OS << " if (Result != MatchOperand_NoMatch)\n";
2598 OS << " return Result;\n";
2601 OS << " // Okay, we had no match.\n";
2602 OS << " return MatchOperand_NoMatch;\n";
2606 void AsmMatcherEmitter::run(raw_ostream &OS) {
2607 CodeGenTarget Target(Records);
2608 Record *AsmParser = Target.getAsmParser();
2609 std::string ClassName = AsmParser->getValueAsString("AsmParserClassName");
2611 // Compute the information on the instructions to match.
2612 AsmMatcherInfo Info(AsmParser, Target, Records);
2615 // Sort the instruction table using the partial order on classes. We use
2616 // stable_sort to ensure that ambiguous instructions are still
2617 // deterministically ordered.
2618 std::stable_sort(Info.Matchables.begin(), Info.Matchables.end(),
2619 [](const std::unique_ptr<MatchableInfo> &a,
2620 const std::unique_ptr<MatchableInfo> &b){
2623 DEBUG_WITH_TYPE("instruction_info", {
2624 for (const auto &MI : Info.Matchables)
2628 // Check for ambiguous matchables.
2629 DEBUG_WITH_TYPE("ambiguous_instrs", {
2630 unsigned NumAmbiguous = 0;
2631 for (auto I = Info.Matchables.begin(), E = Info.Matchables.end(); I != E;
2633 for (auto J = std::next(I); J != E; ++J) {
2634 const MatchableInfo &A = **I;
2635 const MatchableInfo &B = **J;
2637 if (A.couldMatchAmbiguouslyWith(B)) {
2638 errs() << "warning: ambiguous matchables:\n";
2640 errs() << "\nis incomparable with:\n";
2648 errs() << "warning: " << NumAmbiguous
2649 << " ambiguous matchables!\n";
2652 // Compute the information on the custom operand parsing.
2653 Info.buildOperandMatchInfo();
2655 // Write the output.
2657 // Information for the class declaration.
2658 OS << "\n#ifdef GET_ASSEMBLER_HEADER\n";
2659 OS << "#undef GET_ASSEMBLER_HEADER\n";
2660 OS << " // This should be included into the middle of the declaration of\n";
2661 OS << " // your subclasses implementation of MCTargetAsmParser.\n";
2662 OS << " uint64_t ComputeAvailableFeatures(const FeatureBitset& FB) const;\n";
2663 OS << " void convertToMCInst(unsigned Kind, MCInst &Inst, "
2664 << "unsigned Opcode,\n"
2665 << " const OperandVector "
2667 OS << " void convertToMapAndConstraints(unsigned Kind,\n ";
2668 OS << " const OperandVector &Operands) override;\n";
2669 OS << " bool mnemonicIsValid(StringRef Mnemonic, unsigned VariantID) override;\n";
2670 OS << " unsigned MatchInstructionImpl(const OperandVector &Operands,\n"
2671 << " MCInst &Inst,\n"
2672 << " uint64_t &ErrorInfo,"
2673 << " bool matchingInlineAsm,\n"
2674 << " unsigned VariantID = 0);\n";
2676 if (!Info.OperandMatchInfo.empty()) {
2677 OS << "\n enum OperandMatchResultTy {\n";
2678 OS << " MatchOperand_Success, // operand matched successfully\n";
2679 OS << " MatchOperand_NoMatch, // operand did not match\n";
2680 OS << " MatchOperand_ParseFail // operand matched but had errors\n";
2682 OS << " OperandMatchResultTy MatchOperandParserImpl(\n";
2683 OS << " OperandVector &Operands,\n";
2684 OS << " StringRef Mnemonic);\n";
2686 OS << " OperandMatchResultTy tryCustomParseOperand(\n";
2687 OS << " OperandVector &Operands,\n";
2688 OS << " unsigned MCK);\n\n";
2691 OS << "#endif // GET_ASSEMBLER_HEADER_INFO\n\n";
2693 // Emit the operand match diagnostic enum names.
2694 OS << "\n#ifdef GET_OPERAND_DIAGNOSTIC_TYPES\n";
2695 OS << "#undef GET_OPERAND_DIAGNOSTIC_TYPES\n\n";
2696 emitOperandDiagnosticTypes(Info, OS);
2697 OS << "#endif // GET_OPERAND_DIAGNOSTIC_TYPES\n\n";
2700 OS << "\n#ifdef GET_REGISTER_MATCHER\n";
2701 OS << "#undef GET_REGISTER_MATCHER\n\n";
2703 // Emit the subtarget feature enumeration.
2704 emitSubtargetFeatureFlagEnumeration(Info, OS);
2706 // Emit the function to match a register name to number.
2707 // This should be omitted for Mips target
2708 if (AsmParser->getValueAsBit("ShouldEmitMatchRegisterName"))
2709 emitMatchRegisterName(Target, AsmParser, OS);
2711 OS << "#endif // GET_REGISTER_MATCHER\n\n";
2713 OS << "\n#ifdef GET_SUBTARGET_FEATURE_NAME\n";
2714 OS << "#undef GET_SUBTARGET_FEATURE_NAME\n\n";
2716 // Generate the helper function to get the names for subtarget features.
2717 emitGetSubtargetFeatureName(Info, OS);
2719 OS << "#endif // GET_SUBTARGET_FEATURE_NAME\n\n";
2721 OS << "\n#ifdef GET_MATCHER_IMPLEMENTATION\n";
2722 OS << "#undef GET_MATCHER_IMPLEMENTATION\n\n";
2724 // Generate the function that remaps for mnemonic aliases.
2725 bool HasMnemonicAliases = emitMnemonicAliases(OS, Info, Target);
2727 // Generate the convertToMCInst function to convert operands into an MCInst.
2728 // Also, generate the convertToMapAndConstraints function for MS-style inline
2729 // assembly. The latter doesn't actually generate a MCInst.
2730 emitConvertFuncs(Target, ClassName, Info.Matchables, OS);
2732 // Emit the enumeration for classes which participate in matching.
2733 emitMatchClassEnumeration(Target, Info.Classes, OS);
2735 // Emit the routine to match token strings to their match class.
2736 emitMatchTokenString(Target, Info.Classes, OS);
2738 // Emit the subclass predicate routine.
2739 emitIsSubclass(Target, Info.Classes, OS);
2741 // Emit the routine to validate an operand against a match class.
2742 emitValidateOperandClass(Info, OS);
2744 // Emit the available features compute function.
2745 emitComputeAvailableFeatures(Info, OS);
2748 StringToOffsetTable StringTable;
2750 size_t MaxNumOperands = 0;
2751 unsigned MaxMnemonicIndex = 0;
2752 bool HasDeprecation = false;
2753 for (const auto &MI : Info.Matchables) {
2754 MaxNumOperands = std::max(MaxNumOperands, MI->AsmOperands.size());
2755 HasDeprecation |= MI->HasDeprecation;
2757 // Store a pascal-style length byte in the mnemonic.
2758 std::string LenMnemonic = char(MI->Mnemonic.size()) + MI->Mnemonic.str();
2759 MaxMnemonicIndex = std::max(MaxMnemonicIndex,
2760 StringTable.GetOrAddStringOffset(LenMnemonic, false));
2763 OS << "static const char *const MnemonicTable =\n";
2764 StringTable.EmitString(OS);
2767 // Emit the static match table; unused classes get initalized to 0 which is
2768 // guaranteed to be InvalidMatchClass.
2770 // FIXME: We can reduce the size of this table very easily. First, we change
2771 // it so that store the kinds in separate bit-fields for each index, which
2772 // only needs to be the max width used for classes at that index (we also need
2773 // to reject based on this during classification). If we then make sure to
2774 // order the match kinds appropriately (putting mnemonics last), then we
2775 // should only end up using a few bits for each class, especially the ones
2776 // following the mnemonic.
2777 OS << "namespace {\n";
2778 OS << " struct MatchEntry {\n";
2779 OS << " " << getMinimalTypeForRange(MaxMnemonicIndex)
2781 OS << " uint16_t Opcode;\n";
2782 OS << " " << getMinimalTypeForRange(Info.Matchables.size())
2784 OS << " " << getMinimalRequiredFeaturesType(Info)
2785 << " RequiredFeatures;\n";
2786 OS << " " << getMinimalTypeForRange(
2787 std::distance(Info.Classes.begin(), Info.Classes.end()))
2788 << " Classes[" << MaxNumOperands << "];\n";
2789 OS << " StringRef getMnemonic() const {\n";
2790 OS << " return StringRef(MnemonicTable + Mnemonic + 1,\n";
2791 OS << " MnemonicTable[Mnemonic]);\n";
2795 OS << " // Predicate for searching for an opcode.\n";
2796 OS << " struct LessOpcode {\n";
2797 OS << " bool operator()(const MatchEntry &LHS, StringRef RHS) {\n";
2798 OS << " return LHS.getMnemonic() < RHS;\n";
2800 OS << " bool operator()(StringRef LHS, const MatchEntry &RHS) {\n";
2801 OS << " return LHS < RHS.getMnemonic();\n";
2803 OS << " bool operator()(const MatchEntry &LHS, const MatchEntry &RHS) {\n";
2804 OS << " return LHS.getMnemonic() < RHS.getMnemonic();\n";
2808 OS << "} // end anonymous namespace.\n\n";
2810 unsigned VariantCount = Target.getAsmParserVariantCount();
2811 for (unsigned VC = 0; VC != VariantCount; ++VC) {
2812 Record *AsmVariant = Target.getAsmParserVariant(VC);
2813 int AsmVariantNo = AsmVariant->getValueAsInt("Variant");
2815 OS << "static const MatchEntry MatchTable" << VC << "[] = {\n";
2817 for (const auto &MI : Info.Matchables) {
2818 if (MI->AsmVariantID != AsmVariantNo)
2821 // Store a pascal-style length byte in the mnemonic.
2822 std::string LenMnemonic = char(MI->Mnemonic.size()) + MI->Mnemonic.str();
2823 OS << " { " << StringTable.GetOrAddStringOffset(LenMnemonic, false)
2824 << " /* " << MI->Mnemonic << " */, "
2825 << Target.getName() << "::"
2826 << MI->getResultInst()->TheDef->getName() << ", "
2827 << MI->ConversionFnKind << ", ";
2829 // Write the required features mask.
2830 if (!MI->RequiredFeatures.empty()) {
2831 for (unsigned i = 0, e = MI->RequiredFeatures.size(); i != e; ++i) {
2833 OS << MI->RequiredFeatures[i]->getEnumName();
2839 for (unsigned i = 0, e = MI->AsmOperands.size(); i != e; ++i) {
2840 const MatchableInfo::AsmOperand &Op = MI->AsmOperands[i];
2843 OS << Op.Class->Name;
2851 // A method to determine if a mnemonic is in the list.
2852 OS << "bool " << Target.getName() << ClassName << "::\n"
2853 << "mnemonicIsValid(StringRef Mnemonic, unsigned VariantID) {\n";
2854 OS << " // Find the appropriate table for this asm variant.\n";
2855 OS << " const MatchEntry *Start, *End;\n";
2856 OS << " switch (VariantID) {\n";
2857 OS << " default: llvm_unreachable(\"invalid variant!\");\n";
2858 for (unsigned VC = 0; VC != VariantCount; ++VC) {
2859 Record *AsmVariant = Target.getAsmParserVariant(VC);
2860 int AsmVariantNo = AsmVariant->getValueAsInt("Variant");
2861 OS << " case " << AsmVariantNo << ": Start = std::begin(MatchTable" << VC
2862 << "); End = std::end(MatchTable" << VC << "); break;\n";
2865 OS << " // Search the table.\n";
2866 OS << " std::pair<const MatchEntry*, const MatchEntry*> MnemonicRange =\n";
2867 OS << " std::equal_range(Start, End, Mnemonic, LessOpcode());\n";
2868 OS << " return MnemonicRange.first != MnemonicRange.second;\n";
2871 // Finally, build the match function.
2872 OS << "unsigned " << Target.getName() << ClassName << "::\n"
2873 << "MatchInstructionImpl(const OperandVector &Operands,\n";
2874 OS << " MCInst &Inst, uint64_t &ErrorInfo,\n"
2875 << " bool matchingInlineAsm, unsigned VariantID) {\n";
2877 OS << " // Eliminate obvious mismatches.\n";
2878 OS << " if (Operands.size() > " << (MaxNumOperands+1) << ") {\n";
2879 OS << " ErrorInfo = " << (MaxNumOperands+1) << ";\n";
2880 OS << " return Match_InvalidOperand;\n";
2883 // Emit code to get the available features.
2884 OS << " // Get the current feature set.\n";
2885 OS << " uint64_t AvailableFeatures = getAvailableFeatures();\n\n";
2887 OS << " // Get the instruction mnemonic, which is the first token.\n";
2888 OS << " StringRef Mnemonic = ((" << Target.getName()
2889 << "Operand&)*Operands[0]).getToken();\n\n";
2891 if (HasMnemonicAliases) {
2892 OS << " // Process all MnemonicAliases to remap the mnemonic.\n";
2893 OS << " applyMnemonicAliases(Mnemonic, AvailableFeatures, VariantID);\n\n";
2896 // Emit code to compute the class list for this operand vector.
2897 OS << " // Some state to try to produce better error messages.\n";
2898 OS << " bool HadMatchOtherThanFeatures = false;\n";
2899 OS << " bool HadMatchOtherThanPredicate = false;\n";
2900 OS << " unsigned RetCode = Match_InvalidOperand;\n";
2901 OS << " uint64_t MissingFeatures = ~0ULL;\n";
2902 OS << " // Set ErrorInfo to the operand that mismatches if it is\n";
2903 OS << " // wrong for all instances of the instruction.\n";
2904 OS << " ErrorInfo = ~0ULL;\n";
2906 // Emit code to search the table.
2907 OS << " // Find the appropriate table for this asm variant.\n";
2908 OS << " const MatchEntry *Start, *End;\n";
2909 OS << " switch (VariantID) {\n";
2910 OS << " default: llvm_unreachable(\"invalid variant!\");\n";
2911 for (unsigned VC = 0; VC != VariantCount; ++VC) {
2912 Record *AsmVariant = Target.getAsmParserVariant(VC);
2913 int AsmVariantNo = AsmVariant->getValueAsInt("Variant");
2914 OS << " case " << AsmVariantNo << ": Start = std::begin(MatchTable" << VC
2915 << "); End = std::end(MatchTable" << VC << "); break;\n";
2918 OS << " // Search the table.\n";
2919 OS << " std::pair<const MatchEntry*, const MatchEntry*> MnemonicRange =\n";
2920 OS << " std::equal_range(Start, End, Mnemonic, LessOpcode());\n\n";
2922 OS << " // Return a more specific error code if no mnemonics match.\n";
2923 OS << " if (MnemonicRange.first == MnemonicRange.second)\n";
2924 OS << " return Match_MnemonicFail;\n\n";
2926 OS << " for (const MatchEntry *it = MnemonicRange.first, "
2927 << "*ie = MnemonicRange.second;\n";
2928 OS << " it != ie; ++it) {\n";
2930 OS << " // equal_range guarantees that instruction mnemonic matches.\n";
2931 OS << " assert(Mnemonic == it->getMnemonic());\n";
2933 // Emit check that the subclasses match.
2934 OS << " bool OperandsValid = true;\n";
2935 OS << " for (unsigned i = 0; i != " << MaxNumOperands << "; ++i) {\n";
2936 OS << " if (i + 1 >= Operands.size()) {\n";
2937 OS << " OperandsValid = (it->Classes[i] == " <<"InvalidMatchClass);\n";
2938 OS << " if (!OperandsValid) ErrorInfo = i + 1;\n";
2941 OS << " unsigned Diag = validateOperandClass(*Operands[i+1],\n";
2943 OS << "(MatchClassKind)it->Classes[i]);\n";
2944 OS << " if (Diag == Match_Success)\n";
2945 OS << " continue;\n";
2946 OS << " // If the generic handler indicates an invalid operand\n";
2947 OS << " // failure, check for a special case.\n";
2948 OS << " if (Diag == Match_InvalidOperand) {\n";
2949 OS << " Diag = validateTargetOperandClass(*Operands[i+1],\n";
2951 OS << "(MatchClassKind)it->Classes[i]);\n";
2952 OS << " if (Diag == Match_Success)\n";
2953 OS << " continue;\n";
2955 OS << " // If this operand is broken for all of the instances of this\n";
2956 OS << " // mnemonic, keep track of it so we can report loc info.\n";
2957 OS << " // If we already had a match that only failed due to a\n";
2958 OS << " // target predicate, that diagnostic is preferred.\n";
2959 OS << " if (!HadMatchOtherThanPredicate &&\n";
2960 OS << " (it == MnemonicRange.first || ErrorInfo <= i+1)) {\n";
2961 OS << " ErrorInfo = i+1;\n";
2962 OS << " // InvalidOperand is the default. Prefer specificity.\n";
2963 OS << " if (Diag != Match_InvalidOperand)\n";
2964 OS << " RetCode = Diag;\n";
2966 OS << " // Otherwise, just reject this instance of the mnemonic.\n";
2967 OS << " OperandsValid = false;\n";
2971 OS << " if (!OperandsValid) continue;\n";
2973 // Emit check that the required features are available.
2974 OS << " if ((AvailableFeatures & it->RequiredFeatures) "
2975 << "!= it->RequiredFeatures) {\n";
2976 OS << " HadMatchOtherThanFeatures = true;\n";
2977 OS << " uint64_t NewMissingFeatures = it->RequiredFeatures & "
2978 "~AvailableFeatures;\n";
2979 OS << " if (countPopulation(NewMissingFeatures) <=\n"
2980 " countPopulation(MissingFeatures))\n";
2981 OS << " MissingFeatures = NewMissingFeatures;\n";
2982 OS << " continue;\n";
2985 OS << " Inst.clear();\n\n";
2986 OS << " if (matchingInlineAsm) {\n";
2987 OS << " Inst.setOpcode(it->Opcode);\n";
2988 OS << " convertToMapAndConstraints(it->ConvertFn, Operands);\n";
2989 OS << " return Match_Success;\n";
2991 OS << " // We have selected a definite instruction, convert the parsed\n"
2992 << " // operands into the appropriate MCInst.\n";
2993 OS << " convertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands);\n";
2996 // Verify the instruction with the target-specific match predicate function.
2997 OS << " // We have a potential match. Check the target predicate to\n"
2998 << " // handle any context sensitive constraints.\n"
2999 << " unsigned MatchResult;\n"
3000 << " if ((MatchResult = checkTargetMatchPredicate(Inst)) !="
3001 << " Match_Success) {\n"
3002 << " Inst.clear();\n"
3003 << " RetCode = MatchResult;\n"
3004 << " HadMatchOtherThanPredicate = true;\n"
3008 // Call the post-processing function, if used.
3009 std::string InsnCleanupFn =
3010 AsmParser->getValueAsString("AsmParserInstCleanup");
3011 if (!InsnCleanupFn.empty())
3012 OS << " " << InsnCleanupFn << "(Inst);\n";
3014 if (HasDeprecation) {
3015 OS << " std::string Info;\n";
3016 OS << " if (MII.get(Inst.getOpcode()).getDeprecatedInfo(Inst, STI, Info)) {\n";
3017 OS << " SMLoc Loc = ((" << Target.getName()
3018 << "Operand&)*Operands[0]).getStartLoc();\n";
3019 OS << " getParser().Warning(Loc, Info, None);\n";
3023 OS << " return Match_Success;\n";
3026 OS << " // Okay, we had no match. Try to return a useful error code.\n";
3027 OS << " if (HadMatchOtherThanPredicate || !HadMatchOtherThanFeatures)\n";
3028 OS << " return RetCode;\n\n";
3029 OS << " // Missing feature matches return which features were missing\n";
3030 OS << " ErrorInfo = MissingFeatures;\n";
3031 OS << " return Match_MissingFeature;\n";
3034 if (!Info.OperandMatchInfo.empty())
3035 emitCustomOperandParsing(OS, Target, Info, ClassName, StringTable,
3038 OS << "#endif // GET_MATCHER_IMPLEMENTATION\n\n";
3043 void EmitAsmMatcher(RecordKeeper &RK, raw_ostream &OS) {
3044 emitSourceFileHeader("Assembly Matcher Source Fragment", OS);
3045 AsmMatcherEmitter(RK).run(OS);
3048 } // End llvm namespace