1 //===- AsmMatcherEmitter.cpp - Generate an assembly matcher ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend emits a target specifier matcher for converting parsed
11 // assembly operands in the MCInst structures. It also emits a matcher for
12 // custom operand parsing.
14 // Converting assembly operands into MCInst structures
15 // ---------------------------------------------------
17 // The input to the target specific matcher is a list of literal tokens and
18 // operands. The target specific parser should generally eliminate any syntax
19 // which is not relevant for matching; for example, comma tokens should have
20 // already been consumed and eliminated by the parser. Most instructions will
21 // end up with a single literal token (the instruction name) and some number of
24 // Some example inputs, for X86:
25 // 'addl' (immediate ...) (register ...)
26 // 'add' (immediate ...) (memory ...)
29 // The assembly matcher is responsible for converting this input into a precise
30 // machine instruction (i.e., an instruction with a well defined encoding). This
31 // mapping has several properties which complicate matching:
33 // - It may be ambiguous; many architectures can legally encode particular
34 // variants of an instruction in different ways (for example, using a smaller
35 // encoding for small immediates). Such ambiguities should never be
36 // arbitrarily resolved by the assembler, the assembler is always responsible
37 // for choosing the "best" available instruction.
39 // - It may depend on the subtarget or the assembler context. Instructions
40 // which are invalid for the current mode, but otherwise unambiguous (e.g.,
41 // an SSE instruction in a file being assembled for i486) should be accepted
42 // and rejected by the assembler front end. However, if the proper encoding
43 // for an instruction is dependent on the assembler context then the matcher
44 // is responsible for selecting the correct machine instruction for the
47 // The core matching algorithm attempts to exploit the regularity in most
48 // instruction sets to quickly determine the set of possibly matching
49 // instructions, and the simplify the generated code. Additionally, this helps
50 // to ensure that the ambiguities are intentionally resolved by the user.
52 // The matching is divided into two distinct phases:
54 // 1. Classification: Each operand is mapped to the unique set which (a)
55 // contains it, and (b) is the largest such subset for which a single
56 // instruction could match all members.
58 // For register classes, we can generate these subgroups automatically. For
59 // arbitrary operands, we expect the user to define the classes and their
60 // relations to one another (for example, 8-bit signed immediates as a
61 // subset of 32-bit immediates).
63 // By partitioning the operands in this way, we guarantee that for any
64 // tuple of classes, any single instruction must match either all or none
65 // of the sets of operands which could classify to that tuple.
67 // In addition, the subset relation amongst classes induces a partial order
68 // on such tuples, which we use to resolve ambiguities.
70 // 2. The input can now be treated as a tuple of classes (static tokens are
71 // simple singleton sets). Each such tuple should generally map to a single
72 // instruction (we currently ignore cases where this isn't true, whee!!!),
73 // which we can emit a simple matcher for.
75 // Custom Operand Parsing
76 // ----------------------
78 // Some targets need a custom way to parse operands, some specific instructions
79 // can contain arguments that can represent processor flags and other kinds of
80 // identifiers that need to be mapped to specific values in the final encoded
81 // instructions. The target specific custom operand parsing works in the
84 // 1. A operand match table is built, each entry contains a mnemonic, an
85 // operand class, a mask for all operand positions for that same
86 // class/mnemonic and target features to be checked while trying to match.
88 // 2. The operand matcher will try every possible entry with the same
89 // mnemonic and will check if the target feature for this mnemonic also
90 // matches. After that, if the operand to be matched has its index
91 // present in the mask, a successful match occurs. Otherwise, fallback
92 // to the regular operand parsing.
94 // 3. For a match success, each operand class that has a 'ParserMethod'
95 // becomes part of a switch from where the custom method is called.
97 //===----------------------------------------------------------------------===//
99 #include "CodeGenTarget.h"
100 #include "llvm/ADT/OwningPtr.h"
101 #include "llvm/ADT/PointerUnion.h"
102 #include "llvm/ADT/STLExtras.h"
103 #include "llvm/ADT/SmallPtrSet.h"
104 #include "llvm/ADT/SmallVector.h"
105 #include "llvm/ADT/StringExtras.h"
106 #include "llvm/Support/CommandLine.h"
107 #include "llvm/Support/Debug.h"
108 #include "llvm/Support/ErrorHandling.h"
109 #include "llvm/TableGen/Error.h"
110 #include "llvm/TableGen/Record.h"
111 #include "llvm/TableGen/StringMatcher.h"
112 #include "llvm/TableGen/StringToOffsetTable.h"
113 #include "llvm/TableGen/TableGenBackend.h"
118 using namespace llvm;
120 static cl::opt<std::string>
121 MatchPrefix("match-prefix", cl::init(""),
122 cl::desc("Only match instructions with the given prefix"));
125 class AsmMatcherInfo;
126 struct SubtargetFeatureInfo;
128 // Register sets are used as keys in some second-order sets TableGen creates
129 // when generating its data structures. This means that the order of two
130 // RegisterSets can be seen in the outputted AsmMatcher tables occasionally, and
131 // can even affect compiler output (at least seen in diagnostics produced when
132 // all matches fail). So we use a type that sorts them consistently.
133 typedef std::set<Record*, LessRecordByID> RegisterSet;
135 class AsmMatcherEmitter {
136 RecordKeeper &Records;
138 AsmMatcherEmitter(RecordKeeper &R) : Records(R) {}
140 void run(raw_ostream &o);
143 /// ClassInfo - Helper class for storing the information about a particular
144 /// class of operands which can be matched.
147 /// Invalid kind, for use as a sentinel value.
150 /// The class for a particular token.
153 /// The (first) register class, subsequent register classes are
154 /// RegisterClass0+1, and so on.
157 /// The (first) user defined class, subsequent user defined classes are
158 /// UserClass0+1, and so on.
162 /// Kind - The class kind, which is either a predefined kind, or (UserClass0 +
163 /// N) for the Nth user defined class.
166 /// SuperClasses - The super classes of this class. Note that for simplicities
167 /// sake user operands only record their immediate super class, while register
168 /// operands include all superclasses.
169 std::vector<ClassInfo*> SuperClasses;
171 /// Name - The full class name, suitable for use in an enum.
174 /// ClassName - The unadorned generic name for this class (e.g., Token).
175 std::string ClassName;
177 /// ValueName - The name of the value this class represents; for a token this
178 /// is the literal token string, for an operand it is the TableGen class (or
179 /// empty if this is a derived class).
180 std::string ValueName;
182 /// PredicateMethod - The name of the operand method to test whether the
183 /// operand matches this class; this is not valid for Token or register kinds.
184 std::string PredicateMethod;
186 /// RenderMethod - The name of the operand method to add this operand to an
187 /// MCInst; this is not valid for Token or register kinds.
188 std::string RenderMethod;
190 /// ParserMethod - The name of the operand method to do a target specific
191 /// parsing on the operand.
192 std::string ParserMethod;
194 /// For register classes, the records for all the registers in this class.
195 RegisterSet Registers;
197 /// For custom match classes, he diagnostic kind for when the predicate fails.
198 std::string DiagnosticType;
200 /// isRegisterClass() - Check if this is a register class.
201 bool isRegisterClass() const {
202 return Kind >= RegisterClass0 && Kind < UserClass0;
205 /// isUserClass() - Check if this is a user defined class.
206 bool isUserClass() const {
207 return Kind >= UserClass0;
210 /// isRelatedTo - Check whether this class is "related" to \p RHS. Classes
211 /// are related if they are in the same class hierarchy.
212 bool isRelatedTo(const ClassInfo &RHS) const {
213 // Tokens are only related to tokens.
214 if (Kind == Token || RHS.Kind == Token)
215 return Kind == Token && RHS.Kind == Token;
217 // Registers classes are only related to registers classes, and only if
218 // their intersection is non-empty.
219 if (isRegisterClass() || RHS.isRegisterClass()) {
220 if (!isRegisterClass() || !RHS.isRegisterClass())
224 std::insert_iterator<RegisterSet> II(Tmp, Tmp.begin());
225 std::set_intersection(Registers.begin(), Registers.end(),
226 RHS.Registers.begin(), RHS.Registers.end(),
227 II, LessRecordByID());
232 // Otherwise we have two users operands; they are related if they are in the
233 // same class hierarchy.
235 // FIXME: This is an oversimplification, they should only be related if they
236 // intersect, however we don't have that information.
237 assert(isUserClass() && RHS.isUserClass() && "Unexpected class!");
238 const ClassInfo *Root = this;
239 while (!Root->SuperClasses.empty())
240 Root = Root->SuperClasses.front();
242 const ClassInfo *RHSRoot = &RHS;
243 while (!RHSRoot->SuperClasses.empty())
244 RHSRoot = RHSRoot->SuperClasses.front();
246 return Root == RHSRoot;
249 /// isSubsetOf - Test whether this class is a subset of \p RHS.
250 bool isSubsetOf(const ClassInfo &RHS) const {
251 // This is a subset of RHS if it is the same class...
255 // ... or if any of its super classes are a subset of RHS.
256 for (std::vector<ClassInfo*>::const_iterator it = SuperClasses.begin(),
257 ie = SuperClasses.end(); it != ie; ++it)
258 if ((*it)->isSubsetOf(RHS))
264 /// operator< - Compare two classes.
265 bool operator<(const ClassInfo &RHS) const {
269 // Unrelated classes can be ordered by kind.
270 if (!isRelatedTo(RHS))
271 return Kind < RHS.Kind;
275 llvm_unreachable("Invalid kind!");
278 // This class precedes the RHS if it is a proper subset of the RHS.
281 if (RHS.isSubsetOf(*this))
284 // Otherwise, order by name to ensure we have a total ordering.
285 return ValueName < RHS.ValueName;
291 /// Sort ClassInfo pointers independently of pointer value.
292 struct LessClassInfoPtr {
293 bool operator()(const ClassInfo *LHS, const ClassInfo *RHS) const {
299 /// MatchableInfo - Helper class for storing the necessary information for an
300 /// instruction or alias which is capable of being matched.
301 struct MatchableInfo {
303 /// Token - This is the token that the operand came from.
306 /// The unique class instance this operand should match.
309 /// The operand name this is, if anything.
312 /// The suboperand index within SrcOpName, or -1 for the entire operand.
315 /// Register record if this token is singleton register.
316 Record *SingletonReg;
318 explicit AsmOperand(StringRef T) : Token(T), Class(0), SubOpIdx(-1),
322 /// ResOperand - This represents a single operand in the result instruction
323 /// generated by the match. In cases (like addressing modes) where a single
324 /// assembler operand expands to multiple MCOperands, this represents the
325 /// single assembler operand, not the MCOperand.
328 /// RenderAsmOperand - This represents an operand result that is
329 /// generated by calling the render method on the assembly operand. The
330 /// corresponding AsmOperand is specified by AsmOperandNum.
333 /// TiedOperand - This represents a result operand that is a duplicate of
334 /// a previous result operand.
337 /// ImmOperand - This represents an immediate value that is dumped into
341 /// RegOperand - This represents a fixed register that is dumped in.
346 /// This is the operand # in the AsmOperands list that this should be
348 unsigned AsmOperandNum;
350 /// TiedOperandNum - This is the (earlier) result operand that should be
352 unsigned TiedOperandNum;
354 /// ImmVal - This is the immediate value added to the instruction.
357 /// Register - This is the register record.
361 /// MINumOperands - The number of MCInst operands populated by this
363 unsigned MINumOperands;
365 static ResOperand getRenderedOp(unsigned AsmOpNum, unsigned NumOperands) {
367 X.Kind = RenderAsmOperand;
368 X.AsmOperandNum = AsmOpNum;
369 X.MINumOperands = NumOperands;
373 static ResOperand getTiedOp(unsigned TiedOperandNum) {
375 X.Kind = TiedOperand;
376 X.TiedOperandNum = TiedOperandNum;
381 static ResOperand getImmOp(int64_t Val) {
389 static ResOperand getRegOp(Record *Reg) {
398 /// AsmVariantID - Target's assembly syntax variant no.
401 /// TheDef - This is the definition of the instruction or InstAlias that this
402 /// matchable came from.
403 Record *const TheDef;
405 /// DefRec - This is the definition that it came from.
406 PointerUnion<const CodeGenInstruction*, const CodeGenInstAlias*> DefRec;
408 const CodeGenInstruction *getResultInst() const {
409 if (DefRec.is<const CodeGenInstruction*>())
410 return DefRec.get<const CodeGenInstruction*>();
411 return DefRec.get<const CodeGenInstAlias*>()->ResultInst;
414 /// ResOperands - This is the operand list that should be built for the result
416 SmallVector<ResOperand, 8> ResOperands;
418 /// AsmString - The assembly string for this instruction (with variants
419 /// removed), e.g. "movsx $src, $dst".
420 std::string AsmString;
422 /// Mnemonic - This is the first token of the matched instruction, its
426 /// AsmOperands - The textual operands that this instruction matches,
427 /// annotated with a class and where in the OperandList they were defined.
428 /// This directly corresponds to the tokenized AsmString after the mnemonic is
430 SmallVector<AsmOperand, 8> AsmOperands;
432 /// Predicates - The required subtarget features to match this instruction.
433 SmallVector<SubtargetFeatureInfo*, 4> RequiredFeatures;
435 /// ConversionFnKind - The enum value which is passed to the generated
436 /// convertToMCInst to convert parsed operands into an MCInst for this
438 std::string ConversionFnKind;
440 /// If this instruction is deprecated in some form.
443 MatchableInfo(const CodeGenInstruction &CGI)
444 : AsmVariantID(0), TheDef(CGI.TheDef), DefRec(&CGI),
445 AsmString(CGI.AsmString) {
448 MatchableInfo(const CodeGenInstAlias *Alias)
449 : AsmVariantID(0), TheDef(Alias->TheDef), DefRec(Alias),
450 AsmString(Alias->AsmString) {
453 // Two-operand aliases clone from the main matchable, but mark the second
454 // operand as a tied operand of the first for purposes of the assembler.
455 void formTwoOperandAlias(StringRef Constraint);
457 void initialize(const AsmMatcherInfo &Info,
458 SmallPtrSet<Record*, 16> &SingletonRegisters,
459 int AsmVariantNo, std::string &RegisterPrefix);
461 /// validate - Return true if this matchable is a valid thing to match against
462 /// and perform a bunch of validity checking.
463 bool validate(StringRef CommentDelimiter, bool Hack) const;
465 /// extractSingletonRegisterForAsmOperand - Extract singleton register,
466 /// if present, from specified token.
468 extractSingletonRegisterForAsmOperand(unsigned i, const AsmMatcherInfo &Info,
469 std::string &RegisterPrefix);
471 /// findAsmOperand - Find the AsmOperand with the specified name and
472 /// suboperand index.
473 int findAsmOperand(StringRef N, int SubOpIdx) const {
474 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i)
475 if (N == AsmOperands[i].SrcOpName &&
476 SubOpIdx == AsmOperands[i].SubOpIdx)
481 /// findAsmOperandNamed - Find the first AsmOperand with the specified name.
482 /// This does not check the suboperand index.
483 int findAsmOperandNamed(StringRef N) const {
484 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i)
485 if (N == AsmOperands[i].SrcOpName)
490 void buildInstructionResultOperands();
491 void buildAliasResultOperands();
493 /// operator< - Compare two matchables.
494 bool operator<(const MatchableInfo &RHS) const {
495 // The primary comparator is the instruction mnemonic.
496 if (Mnemonic != RHS.Mnemonic)
497 return Mnemonic < RHS.Mnemonic;
499 if (AsmOperands.size() != RHS.AsmOperands.size())
500 return AsmOperands.size() < RHS.AsmOperands.size();
502 // Compare lexicographically by operand. The matcher validates that other
503 // orderings wouldn't be ambiguous using \see couldMatchAmbiguouslyWith().
504 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
505 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class)
507 if (*RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
511 // Give matches that require more features higher precedence. This is useful
512 // because we cannot define AssemblerPredicates with the negation of
513 // processor features. For example, ARM v6 "nop" may be either a HINT or
514 // MOV. With v6, we want to match HINT. The assembler has no way to
515 // predicate MOV under "NoV6", but HINT will always match first because it
516 // requires V6 while MOV does not.
517 if (RequiredFeatures.size() != RHS.RequiredFeatures.size())
518 return RequiredFeatures.size() > RHS.RequiredFeatures.size();
523 /// couldMatchAmbiguouslyWith - Check whether this matchable could
524 /// ambiguously match the same set of operands as \p RHS (without being a
525 /// strictly superior match).
526 bool couldMatchAmbiguouslyWith(const MatchableInfo &RHS) {
527 // The primary comparator is the instruction mnemonic.
528 if (Mnemonic != RHS.Mnemonic)
531 // The number of operands is unambiguous.
532 if (AsmOperands.size() != RHS.AsmOperands.size())
535 // Otherwise, make sure the ordering of the two instructions is unambiguous
536 // by checking that either (a) a token or operand kind discriminates them,
537 // or (b) the ordering among equivalent kinds is consistent.
539 // Tokens and operand kinds are unambiguous (assuming a correct target
541 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i)
542 if (AsmOperands[i].Class->Kind != RHS.AsmOperands[i].Class->Kind ||
543 AsmOperands[i].Class->Kind == ClassInfo::Token)
544 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class ||
545 *RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
548 // Otherwise, this operand could commute if all operands are equivalent, or
549 // there is a pair of operands that compare less than and a pair that
550 // compare greater than.
551 bool HasLT = false, HasGT = false;
552 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
553 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class)
555 if (*RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
559 return !(HasLT ^ HasGT);
565 void tokenizeAsmString(const AsmMatcherInfo &Info);
568 /// SubtargetFeatureInfo - Helper class for storing information on a subtarget
569 /// feature which participates in instruction matching.
570 struct SubtargetFeatureInfo {
571 /// \brief The predicate record for this feature.
574 /// \brief An unique index assigned to represent this feature.
577 SubtargetFeatureInfo(Record *D, unsigned Idx) : TheDef(D), Index(Idx) {}
579 /// \brief The name of the enumerated constant identifying this feature.
580 std::string getEnumName() const {
581 return "Feature_" + TheDef->getName();
585 struct OperandMatchEntry {
586 unsigned OperandMask;
590 static OperandMatchEntry create(MatchableInfo* mi, ClassInfo *ci,
593 X.OperandMask = opMask;
601 class AsmMatcherInfo {
604 RecordKeeper &Records;
606 /// The tablegen AsmParser record.
609 /// Target - The target information.
610 CodeGenTarget &Target;
612 /// The classes which are needed for matching.
613 std::vector<ClassInfo*> Classes;
615 /// The information on the matchables to match.
616 std::vector<MatchableInfo*> Matchables;
618 /// Info for custom matching operands by user defined methods.
619 std::vector<OperandMatchEntry> OperandMatchInfo;
621 /// Map of Register records to their class information.
622 typedef std::map<Record*, ClassInfo*, LessRecordByID> RegisterClassesTy;
623 RegisterClassesTy RegisterClasses;
625 /// Map of Predicate records to their subtarget information.
626 std::map<Record*, SubtargetFeatureInfo*, LessRecordByID> SubtargetFeatures;
628 /// Map of AsmOperandClass records to their class information.
629 std::map<Record*, ClassInfo*> AsmOperandClasses;
632 /// Map of token to class information which has already been constructed.
633 std::map<std::string, ClassInfo*> TokenClasses;
635 /// Map of RegisterClass records to their class information.
636 std::map<Record*, ClassInfo*> RegisterClassClasses;
639 /// getTokenClass - Lookup or create the class for the given token.
640 ClassInfo *getTokenClass(StringRef Token);
642 /// getOperandClass - Lookup or create the class for the given operand.
643 ClassInfo *getOperandClass(const CGIOperandList::OperandInfo &OI,
645 ClassInfo *getOperandClass(Record *Rec, int SubOpIdx);
647 /// buildRegisterClasses - Build the ClassInfo* instances for register
649 void buildRegisterClasses(SmallPtrSet<Record*, 16> &SingletonRegisters);
651 /// buildOperandClasses - Build the ClassInfo* instances for user defined
653 void buildOperandClasses();
655 void buildInstructionOperandReference(MatchableInfo *II, StringRef OpName,
657 void buildAliasOperandReference(MatchableInfo *II, StringRef OpName,
658 MatchableInfo::AsmOperand &Op);
661 AsmMatcherInfo(Record *AsmParser,
662 CodeGenTarget &Target,
663 RecordKeeper &Records);
665 /// buildInfo - Construct the various tables used during matching.
668 /// buildOperandMatchInfo - Build the necessary information to handle user
669 /// defined operand parsing methods.
670 void buildOperandMatchInfo();
672 /// getSubtargetFeature - Lookup or create the subtarget feature info for the
674 SubtargetFeatureInfo *getSubtargetFeature(Record *Def) const {
675 assert(Def->isSubClassOf("Predicate") && "Invalid predicate type!");
676 std::map<Record*, SubtargetFeatureInfo*, LessRecordByID>::const_iterator I =
677 SubtargetFeatures.find(Def);
678 return I == SubtargetFeatures.end() ? 0 : I->second;
681 RecordKeeper &getRecords() const {
686 } // End anonymous namespace
688 void MatchableInfo::dump() {
689 errs() << TheDef->getName() << " -- " << "flattened:\"" << AsmString <<"\"\n";
691 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
692 AsmOperand &Op = AsmOperands[i];
693 errs() << " op[" << i << "] = " << Op.Class->ClassName << " - ";
694 errs() << '\"' << Op.Token << "\"\n";
698 static std::pair<StringRef, StringRef>
699 parseTwoOperandConstraint(StringRef S, ArrayRef<SMLoc> Loc) {
700 // Split via the '='.
701 std::pair<StringRef, StringRef> Ops = S.split('=');
702 if (Ops.second == "")
703 PrintFatalError(Loc, "missing '=' in two-operand alias constraint");
704 // Trim whitespace and the leading '$' on the operand names.
705 size_t start = Ops.first.find_first_of('$');
706 if (start == std::string::npos)
707 PrintFatalError(Loc, "expected '$' prefix on asm operand name");
708 Ops.first = Ops.first.slice(start + 1, std::string::npos);
709 size_t end = Ops.first.find_last_of(" \t");
710 Ops.first = Ops.first.slice(0, end);
711 // Now the second operand.
712 start = Ops.second.find_first_of('$');
713 if (start == std::string::npos)
714 PrintFatalError(Loc, "expected '$' prefix on asm operand name");
715 Ops.second = Ops.second.slice(start + 1, std::string::npos);
716 end = Ops.second.find_last_of(" \t");
717 Ops.first = Ops.first.slice(0, end);
721 void MatchableInfo::formTwoOperandAlias(StringRef Constraint) {
722 // Figure out which operands are aliased and mark them as tied.
723 std::pair<StringRef, StringRef> Ops =
724 parseTwoOperandConstraint(Constraint, TheDef->getLoc());
726 // Find the AsmOperands that refer to the operands we're aliasing.
727 int SrcAsmOperand = findAsmOperandNamed(Ops.first);
728 int DstAsmOperand = findAsmOperandNamed(Ops.second);
729 if (SrcAsmOperand == -1)
730 PrintFatalError(TheDef->getLoc(),
731 "unknown source two-operand alias operand '" +
732 Ops.first.str() + "'.");
733 if (DstAsmOperand == -1)
734 PrintFatalError(TheDef->getLoc(),
735 "unknown destination two-operand alias operand '" +
736 Ops.second.str() + "'.");
738 // Find the ResOperand that refers to the operand we're aliasing away
739 // and update it to refer to the combined operand instead.
740 for (unsigned i = 0, e = ResOperands.size(); i != e; ++i) {
741 ResOperand &Op = ResOperands[i];
742 if (Op.Kind == ResOperand::RenderAsmOperand &&
743 Op.AsmOperandNum == (unsigned)SrcAsmOperand) {
744 Op.AsmOperandNum = DstAsmOperand;
748 // Remove the AsmOperand for the alias operand.
749 AsmOperands.erase(AsmOperands.begin() + SrcAsmOperand);
750 // Adjust the ResOperand references to any AsmOperands that followed
751 // the one we just deleted.
752 for (unsigned i = 0, e = ResOperands.size(); i != e; ++i) {
753 ResOperand &Op = ResOperands[i];
756 // Nothing to do for operands that don't reference AsmOperands.
758 case ResOperand::RenderAsmOperand:
759 if (Op.AsmOperandNum > (unsigned)SrcAsmOperand)
762 case ResOperand::TiedOperand:
763 if (Op.TiedOperandNum > (unsigned)SrcAsmOperand)
770 void MatchableInfo::initialize(const AsmMatcherInfo &Info,
771 SmallPtrSet<Record*, 16> &SingletonRegisters,
772 int AsmVariantNo, std::string &RegisterPrefix) {
773 AsmVariantID = AsmVariantNo;
775 CodeGenInstruction::FlattenAsmStringVariants(AsmString, AsmVariantNo);
777 tokenizeAsmString(Info);
779 // Compute the require features.
780 std::vector<Record*> Predicates =TheDef->getValueAsListOfDefs("Predicates");
781 for (unsigned i = 0, e = Predicates.size(); i != e; ++i)
782 if (SubtargetFeatureInfo *Feature =
783 Info.getSubtargetFeature(Predicates[i]))
784 RequiredFeatures.push_back(Feature);
786 // Collect singleton registers, if used.
787 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
788 extractSingletonRegisterForAsmOperand(i, Info, RegisterPrefix);
789 if (Record *Reg = AsmOperands[i].SingletonReg)
790 SingletonRegisters.insert(Reg);
793 const RecordVal *DepMask = TheDef->getValue("DeprecatedFeatureMask");
795 DepMask = TheDef->getValue("ComplexDeprecationPredicate");
798 DepMask ? !DepMask->getValue()->getAsUnquotedString().empty() : false;
801 /// tokenizeAsmString - Tokenize a simplified assembly string.
802 void MatchableInfo::tokenizeAsmString(const AsmMatcherInfo &Info) {
803 StringRef String = AsmString;
806 for (unsigned i = 0, e = String.size(); i != e; ++i) {
816 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
819 if (!isspace(String[i]) && String[i] != ',')
820 AsmOperands.push_back(AsmOperand(String.substr(i, 1)));
826 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
830 assert(i != String.size() && "Invalid quoted character");
831 AsmOperands.push_back(AsmOperand(String.substr(i, 1)));
837 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
841 // If this isn't "${", treat like a normal token.
842 if (i + 1 == String.size() || String[i + 1] != '{') {
847 StringRef::iterator End = std::find(String.begin() + i, String.end(),'}');
848 assert(End != String.end() && "Missing brace in operand reference!");
849 size_t EndPos = End - String.begin();
850 AsmOperands.push_back(AsmOperand(String.slice(i, EndPos+1)));
857 if (!Info.AsmParser->getValueAsBit("MnemonicContainsDot")) {
859 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
869 if (InTok && Prev != String.size())
870 AsmOperands.push_back(AsmOperand(String.substr(Prev)));
872 // The first token of the instruction is the mnemonic, which must be a
873 // simple string, not a $foo variable or a singleton register.
874 if (AsmOperands.empty())
875 PrintFatalError(TheDef->getLoc(),
876 "Instruction '" + TheDef->getName() + "' has no tokens");
877 Mnemonic = AsmOperands[0].Token;
878 if (Mnemonic.empty())
879 PrintFatalError(TheDef->getLoc(),
880 "Missing instruction mnemonic");
881 // FIXME : Check and raise an error if it is a register.
882 if (Mnemonic[0] == '$')
883 PrintFatalError(TheDef->getLoc(),
884 "Invalid instruction mnemonic '" + Mnemonic.str() + "'!");
886 // Remove the first operand, it is tracked in the mnemonic field.
887 AsmOperands.erase(AsmOperands.begin());
890 bool MatchableInfo::validate(StringRef CommentDelimiter, bool Hack) const {
891 // Reject matchables with no .s string.
892 if (AsmString.empty())
893 PrintFatalError(TheDef->getLoc(), "instruction with empty asm string");
895 // Reject any matchables with a newline in them, they should be marked
896 // isCodeGenOnly if they are pseudo instructions.
897 if (AsmString.find('\n') != std::string::npos)
898 PrintFatalError(TheDef->getLoc(),
899 "multiline instruction is not valid for the asmparser, "
900 "mark it isCodeGenOnly");
902 // Remove comments from the asm string. We know that the asmstring only
904 if (!CommentDelimiter.empty() &&
905 StringRef(AsmString).find(CommentDelimiter) != StringRef::npos)
906 PrintFatalError(TheDef->getLoc(),
907 "asmstring for instruction has comment character in it, "
908 "mark it isCodeGenOnly");
910 // Reject matchables with operand modifiers, these aren't something we can
911 // handle, the target should be refactored to use operands instead of
914 // Also, check for instructions which reference the operand multiple times;
915 // this implies a constraint we would not honor.
916 std::set<std::string> OperandNames;
917 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
918 StringRef Tok = AsmOperands[i].Token;
919 if (Tok[0] == '$' && Tok.find(':') != StringRef::npos)
920 PrintFatalError(TheDef->getLoc(),
921 "matchable with operand modifier '" + Tok.str() +
922 "' not supported by asm matcher. Mark isCodeGenOnly!");
924 // Verify that any operand is only mentioned once.
925 // We reject aliases and ignore instructions for now.
926 if (Tok[0] == '$' && !OperandNames.insert(Tok).second) {
928 PrintFatalError(TheDef->getLoc(),
929 "ERROR: matchable with tied operand '" + Tok.str() +
930 "' can never be matched!");
931 // FIXME: Should reject these. The ARM backend hits this with $lane in a
932 // bunch of instructions. It is unclear what the right answer is.
934 errs() << "warning: '" << TheDef->getName() << "': "
935 << "ignoring instruction with tied operand '"
936 << Tok.str() << "'\n";
945 /// extractSingletonRegisterForAsmOperand - Extract singleton register,
946 /// if present, from specified token.
948 extractSingletonRegisterForAsmOperand(unsigned OperandNo,
949 const AsmMatcherInfo &Info,
950 std::string &RegisterPrefix) {
951 StringRef Tok = AsmOperands[OperandNo].Token;
952 if (RegisterPrefix.empty()) {
953 std::string LoweredTok = Tok.lower();
954 if (const CodeGenRegister *Reg = Info.Target.getRegisterByName(LoweredTok))
955 AsmOperands[OperandNo].SingletonReg = Reg->TheDef;
959 if (!Tok.startswith(RegisterPrefix))
962 StringRef RegName = Tok.substr(RegisterPrefix.size());
963 if (const CodeGenRegister *Reg = Info.Target.getRegisterByName(RegName))
964 AsmOperands[OperandNo].SingletonReg = Reg->TheDef;
966 // If there is no register prefix (i.e. "%" in "%eax"), then this may
967 // be some random non-register token, just ignore it.
971 static std::string getEnumNameForToken(StringRef Str) {
974 for (StringRef::iterator it = Str.begin(), ie = Str.end(); it != ie; ++it) {
976 case '*': Res += "_STAR_"; break;
977 case '%': Res += "_PCT_"; break;
978 case ':': Res += "_COLON_"; break;
979 case '!': Res += "_EXCLAIM_"; break;
980 case '.': Res += "_DOT_"; break;
981 case '<': Res += "_LT_"; break;
982 case '>': Res += "_GT_"; break;
984 if ((*it >= 'A' && *it <= 'Z') ||
985 (*it >= 'a' && *it <= 'z') ||
986 (*it >= '0' && *it <= '9'))
989 Res += "_" + utostr((unsigned) *it) + "_";
996 ClassInfo *AsmMatcherInfo::getTokenClass(StringRef Token) {
997 ClassInfo *&Entry = TokenClasses[Token];
1000 Entry = new ClassInfo();
1001 Entry->Kind = ClassInfo::Token;
1002 Entry->ClassName = "Token";
1003 Entry->Name = "MCK_" + getEnumNameForToken(Token);
1004 Entry->ValueName = Token;
1005 Entry->PredicateMethod = "<invalid>";
1006 Entry->RenderMethod = "<invalid>";
1007 Entry->ParserMethod = "";
1008 Entry->DiagnosticType = "";
1009 Classes.push_back(Entry);
1016 AsmMatcherInfo::getOperandClass(const CGIOperandList::OperandInfo &OI,
1018 Record *Rec = OI.Rec;
1020 Rec = cast<DefInit>(OI.MIOperandInfo->getArg(SubOpIdx))->getDef();
1021 return getOperandClass(Rec, SubOpIdx);
1025 AsmMatcherInfo::getOperandClass(Record *Rec, int SubOpIdx) {
1026 if (Rec->isSubClassOf("RegisterOperand")) {
1027 // RegisterOperand may have an associated ParserMatchClass. If it does,
1028 // use it, else just fall back to the underlying register class.
1029 const RecordVal *R = Rec->getValue("ParserMatchClass");
1030 if (R == 0 || R->getValue() == 0)
1031 PrintFatalError("Record `" + Rec->getName() +
1032 "' does not have a ParserMatchClass!\n");
1034 if (DefInit *DI= dyn_cast<DefInit>(R->getValue())) {
1035 Record *MatchClass = DI->getDef();
1036 if (ClassInfo *CI = AsmOperandClasses[MatchClass])
1040 // No custom match class. Just use the register class.
1041 Record *ClassRec = Rec->getValueAsDef("RegClass");
1043 PrintFatalError(Rec->getLoc(), "RegisterOperand `" + Rec->getName() +
1044 "' has no associated register class!\n");
1045 if (ClassInfo *CI = RegisterClassClasses[ClassRec])
1047 PrintFatalError(Rec->getLoc(), "register class has no class info!");
1051 if (Rec->isSubClassOf("RegisterClass")) {
1052 if (ClassInfo *CI = RegisterClassClasses[Rec])
1054 PrintFatalError(Rec->getLoc(), "register class has no class info!");
1057 if (!Rec->isSubClassOf("Operand"))
1058 PrintFatalError(Rec->getLoc(), "Operand `" + Rec->getName() +
1059 "' does not derive from class Operand!\n");
1060 Record *MatchClass = Rec->getValueAsDef("ParserMatchClass");
1061 if (ClassInfo *CI = AsmOperandClasses[MatchClass])
1064 PrintFatalError(Rec->getLoc(), "operand has no match class!");
1067 struct LessRegisterSet {
1068 bool operator() (const RegisterSet &LHS, const RegisterSet & RHS) const {
1069 // std::set<T> defines its own compariso "operator<", but it
1070 // performs a lexicographical comparison by T's innate comparison
1071 // for some reason. We don't want non-deterministic pointer
1072 // comparisons so use this instead.
1073 return std::lexicographical_compare(LHS.begin(), LHS.end(),
1074 RHS.begin(), RHS.end(),
1079 void AsmMatcherInfo::
1080 buildRegisterClasses(SmallPtrSet<Record*, 16> &SingletonRegisters) {
1081 const std::vector<CodeGenRegister*> &Registers =
1082 Target.getRegBank().getRegisters();
1083 ArrayRef<CodeGenRegisterClass*> RegClassList =
1084 Target.getRegBank().getRegClasses();
1086 typedef std::set<RegisterSet, LessRegisterSet> RegisterSetSet;
1088 // The register sets used for matching.
1089 RegisterSetSet RegisterSets;
1091 // Gather the defined sets.
1092 for (ArrayRef<CodeGenRegisterClass*>::const_iterator it =
1093 RegClassList.begin(), ie = RegClassList.end(); it != ie; ++it)
1094 RegisterSets.insert(RegisterSet(
1095 (*it)->getOrder().begin(), (*it)->getOrder().end()));
1097 // Add any required singleton sets.
1098 for (SmallPtrSet<Record*, 16>::iterator it = SingletonRegisters.begin(),
1099 ie = SingletonRegisters.end(); it != ie; ++it) {
1101 RegisterSets.insert(RegisterSet(&Rec, &Rec + 1));
1104 // Introduce derived sets where necessary (when a register does not determine
1105 // a unique register set class), and build the mapping of registers to the set
1106 // they should classify to.
1107 std::map<Record*, RegisterSet> RegisterMap;
1108 for (std::vector<CodeGenRegister*>::const_iterator it = Registers.begin(),
1109 ie = Registers.end(); it != ie; ++it) {
1110 const CodeGenRegister &CGR = **it;
1111 // Compute the intersection of all sets containing this register.
1112 RegisterSet ContainingSet;
1114 for (RegisterSetSet::iterator it = RegisterSets.begin(),
1115 ie = RegisterSets.end(); it != ie; ++it) {
1116 if (!it->count(CGR.TheDef))
1119 if (ContainingSet.empty()) {
1120 ContainingSet = *it;
1125 std::swap(Tmp, ContainingSet);
1126 std::insert_iterator<RegisterSet> II(ContainingSet,
1127 ContainingSet.begin());
1128 std::set_intersection(Tmp.begin(), Tmp.end(), it->begin(), it->end(), II,
1132 if (!ContainingSet.empty()) {
1133 RegisterSets.insert(ContainingSet);
1134 RegisterMap.insert(std::make_pair(CGR.TheDef, ContainingSet));
1138 // Construct the register classes.
1139 std::map<RegisterSet, ClassInfo*, LessRegisterSet> RegisterSetClasses;
1141 for (RegisterSetSet::iterator it = RegisterSets.begin(),
1142 ie = RegisterSets.end(); it != ie; ++it, ++Index) {
1143 ClassInfo *CI = new ClassInfo();
1144 CI->Kind = ClassInfo::RegisterClass0 + Index;
1145 CI->ClassName = "Reg" + utostr(Index);
1146 CI->Name = "MCK_Reg" + utostr(Index);
1148 CI->PredicateMethod = ""; // unused
1149 CI->RenderMethod = "addRegOperands";
1150 CI->Registers = *it;
1151 // FIXME: diagnostic type.
1152 CI->DiagnosticType = "";
1153 Classes.push_back(CI);
1154 RegisterSetClasses.insert(std::make_pair(*it, CI));
1157 // Find the superclasses; we could compute only the subgroup lattice edges,
1158 // but there isn't really a point.
1159 for (RegisterSetSet::iterator it = RegisterSets.begin(),
1160 ie = RegisterSets.end(); it != ie; ++it) {
1161 ClassInfo *CI = RegisterSetClasses[*it];
1162 for (RegisterSetSet::iterator it2 = RegisterSets.begin(),
1163 ie2 = RegisterSets.end(); it2 != ie2; ++it2)
1165 std::includes(it2->begin(), it2->end(), it->begin(), it->end(),
1167 CI->SuperClasses.push_back(RegisterSetClasses[*it2]);
1170 // Name the register classes which correspond to a user defined RegisterClass.
1171 for (ArrayRef<CodeGenRegisterClass*>::const_iterator
1172 it = RegClassList.begin(), ie = RegClassList.end(); it != ie; ++it) {
1173 const CodeGenRegisterClass &RC = **it;
1174 // Def will be NULL for non-user defined register classes.
1175 Record *Def = RC.getDef();
1178 ClassInfo *CI = RegisterSetClasses[RegisterSet(RC.getOrder().begin(),
1179 RC.getOrder().end())];
1180 if (CI->ValueName.empty()) {
1181 CI->ClassName = RC.getName();
1182 CI->Name = "MCK_" + RC.getName();
1183 CI->ValueName = RC.getName();
1185 CI->ValueName = CI->ValueName + "," + RC.getName();
1187 RegisterClassClasses.insert(std::make_pair(Def, CI));
1190 // Populate the map for individual registers.
1191 for (std::map<Record*, RegisterSet>::iterator it = RegisterMap.begin(),
1192 ie = RegisterMap.end(); it != ie; ++it)
1193 RegisterClasses[it->first] = RegisterSetClasses[it->second];
1195 // Name the register classes which correspond to singleton registers.
1196 for (SmallPtrSet<Record*, 16>::iterator it = SingletonRegisters.begin(),
1197 ie = SingletonRegisters.end(); it != ie; ++it) {
1199 ClassInfo *CI = RegisterClasses[Rec];
1200 assert(CI && "Missing singleton register class info!");
1202 if (CI->ValueName.empty()) {
1203 CI->ClassName = Rec->getName();
1204 CI->Name = "MCK_" + Rec->getName();
1205 CI->ValueName = Rec->getName();
1207 CI->ValueName = CI->ValueName + "," + Rec->getName();
1211 void AsmMatcherInfo::buildOperandClasses() {
1212 std::vector<Record*> AsmOperands =
1213 Records.getAllDerivedDefinitions("AsmOperandClass");
1215 // Pre-populate AsmOperandClasses map.
1216 for (std::vector<Record*>::iterator it = AsmOperands.begin(),
1217 ie = AsmOperands.end(); it != ie; ++it)
1218 AsmOperandClasses[*it] = new ClassInfo();
1221 for (std::vector<Record*>::iterator it = AsmOperands.begin(),
1222 ie = AsmOperands.end(); it != ie; ++it, ++Index) {
1223 ClassInfo *CI = AsmOperandClasses[*it];
1224 CI->Kind = ClassInfo::UserClass0 + Index;
1226 ListInit *Supers = (*it)->getValueAsListInit("SuperClasses");
1227 for (unsigned i = 0, e = Supers->getSize(); i != e; ++i) {
1228 DefInit *DI = dyn_cast<DefInit>(Supers->getElement(i));
1230 PrintError((*it)->getLoc(), "Invalid super class reference!");
1234 ClassInfo *SC = AsmOperandClasses[DI->getDef()];
1236 PrintError((*it)->getLoc(), "Invalid super class reference!");
1238 CI->SuperClasses.push_back(SC);
1240 CI->ClassName = (*it)->getValueAsString("Name");
1241 CI->Name = "MCK_" + CI->ClassName;
1242 CI->ValueName = (*it)->getName();
1244 // Get or construct the predicate method name.
1245 Init *PMName = (*it)->getValueInit("PredicateMethod");
1246 if (StringInit *SI = dyn_cast<StringInit>(PMName)) {
1247 CI->PredicateMethod = SI->getValue();
1249 assert(isa<UnsetInit>(PMName) && "Unexpected PredicateMethod field!");
1250 CI->PredicateMethod = "is" + CI->ClassName;
1253 // Get or construct the render method name.
1254 Init *RMName = (*it)->getValueInit("RenderMethod");
1255 if (StringInit *SI = dyn_cast<StringInit>(RMName)) {
1256 CI->RenderMethod = SI->getValue();
1258 assert(isa<UnsetInit>(RMName) && "Unexpected RenderMethod field!");
1259 CI->RenderMethod = "add" + CI->ClassName + "Operands";
1262 // Get the parse method name or leave it as empty.
1263 Init *PRMName = (*it)->getValueInit("ParserMethod");
1264 if (StringInit *SI = dyn_cast<StringInit>(PRMName))
1265 CI->ParserMethod = SI->getValue();
1267 // Get the diagnostic type or leave it as empty.
1268 // Get the parse method name or leave it as empty.
1269 Init *DiagnosticType = (*it)->getValueInit("DiagnosticType");
1270 if (StringInit *SI = dyn_cast<StringInit>(DiagnosticType))
1271 CI->DiagnosticType = SI->getValue();
1273 AsmOperandClasses[*it] = CI;
1274 Classes.push_back(CI);
1278 AsmMatcherInfo::AsmMatcherInfo(Record *asmParser,
1279 CodeGenTarget &target,
1280 RecordKeeper &records)
1281 : Records(records), AsmParser(asmParser), Target(target) {
1284 /// buildOperandMatchInfo - Build the necessary information to handle user
1285 /// defined operand parsing methods.
1286 void AsmMatcherInfo::buildOperandMatchInfo() {
1288 /// Map containing a mask with all operands indices that can be found for
1289 /// that class inside a instruction.
1290 typedef std::map<ClassInfo*, unsigned, LessClassInfoPtr> OpClassMaskTy;
1291 OpClassMaskTy OpClassMask;
1293 for (std::vector<MatchableInfo*>::const_iterator it =
1294 Matchables.begin(), ie = Matchables.end();
1296 MatchableInfo &II = **it;
1297 OpClassMask.clear();
1299 // Keep track of all operands of this instructions which belong to the
1301 for (unsigned i = 0, e = II.AsmOperands.size(); i != e; ++i) {
1302 MatchableInfo::AsmOperand &Op = II.AsmOperands[i];
1303 if (Op.Class->ParserMethod.empty())
1305 unsigned &OperandMask = OpClassMask[Op.Class];
1306 OperandMask |= (1 << i);
1309 // Generate operand match info for each mnemonic/operand class pair.
1310 for (OpClassMaskTy::iterator iit = OpClassMask.begin(),
1311 iie = OpClassMask.end(); iit != iie; ++iit) {
1312 unsigned OpMask = iit->second;
1313 ClassInfo *CI = iit->first;
1314 OperandMatchInfo.push_back(OperandMatchEntry::create(&II, CI, OpMask));
1319 void AsmMatcherInfo::buildInfo() {
1320 // Build information about all of the AssemblerPredicates.
1321 std::vector<Record*> AllPredicates =
1322 Records.getAllDerivedDefinitions("Predicate");
1323 for (unsigned i = 0, e = AllPredicates.size(); i != e; ++i) {
1324 Record *Pred = AllPredicates[i];
1325 // Ignore predicates that are not intended for the assembler.
1326 if (!Pred->getValueAsBit("AssemblerMatcherPredicate"))
1329 if (Pred->getName().empty())
1330 PrintFatalError(Pred->getLoc(), "Predicate has no name!");
1332 unsigned FeatureNo = SubtargetFeatures.size();
1333 SubtargetFeatures[Pred] = new SubtargetFeatureInfo(Pred, FeatureNo);
1334 assert(FeatureNo < 32 && "Too many subtarget features!");
1337 // Parse the instructions; we need to do this first so that we can gather the
1338 // singleton register classes.
1339 SmallPtrSet<Record*, 16> SingletonRegisters;
1340 unsigned VariantCount = Target.getAsmParserVariantCount();
1341 for (unsigned VC = 0; VC != VariantCount; ++VC) {
1342 Record *AsmVariant = Target.getAsmParserVariant(VC);
1343 std::string CommentDelimiter =
1344 AsmVariant->getValueAsString("CommentDelimiter");
1345 std::string RegisterPrefix = AsmVariant->getValueAsString("RegisterPrefix");
1346 int AsmVariantNo = AsmVariant->getValueAsInt("Variant");
1348 for (CodeGenTarget::inst_iterator I = Target.inst_begin(),
1349 E = Target.inst_end(); I != E; ++I) {
1350 const CodeGenInstruction &CGI = **I;
1352 // If the tblgen -match-prefix option is specified (for tblgen hackers),
1353 // filter the set of instructions we consider.
1354 if (!StringRef(CGI.TheDef->getName()).startswith(MatchPrefix))
1357 // Ignore "codegen only" instructions.
1358 if (CGI.TheDef->getValueAsBit("isCodeGenOnly"))
1361 OwningPtr<MatchableInfo> II(new MatchableInfo(CGI));
1363 II->initialize(*this, SingletonRegisters, AsmVariantNo, RegisterPrefix);
1365 // Ignore instructions which shouldn't be matched and diagnose invalid
1366 // instruction definitions with an error.
1367 if (!II->validate(CommentDelimiter, true))
1370 // Ignore "Int_*" and "*_Int" instructions, which are internal aliases.
1372 // FIXME: This is a total hack.
1373 if (StringRef(II->TheDef->getName()).startswith("Int_") ||
1374 StringRef(II->TheDef->getName()).endswith("_Int"))
1377 Matchables.push_back(II.take());
1380 // Parse all of the InstAlias definitions and stick them in the list of
1382 std::vector<Record*> AllInstAliases =
1383 Records.getAllDerivedDefinitions("InstAlias");
1384 for (unsigned i = 0, e = AllInstAliases.size(); i != e; ++i) {
1385 CodeGenInstAlias *Alias = new CodeGenInstAlias(AllInstAliases[i], Target);
1387 // If the tblgen -match-prefix option is specified (for tblgen hackers),
1388 // filter the set of instruction aliases we consider, based on the target
1390 if (!StringRef(Alias->ResultInst->TheDef->getName())
1391 .startswith( MatchPrefix))
1394 OwningPtr<MatchableInfo> II(new MatchableInfo(Alias));
1396 II->initialize(*this, SingletonRegisters, AsmVariantNo, RegisterPrefix);
1398 // Validate the alias definitions.
1399 II->validate(CommentDelimiter, false);
1401 Matchables.push_back(II.take());
1405 // Build info for the register classes.
1406 buildRegisterClasses(SingletonRegisters);
1408 // Build info for the user defined assembly operand classes.
1409 buildOperandClasses();
1411 // Build the information about matchables, now that we have fully formed
1413 std::vector<MatchableInfo*> NewMatchables;
1414 for (std::vector<MatchableInfo*>::iterator it = Matchables.begin(),
1415 ie = Matchables.end(); it != ie; ++it) {
1416 MatchableInfo *II = *it;
1418 // Parse the tokens after the mnemonic.
1419 // Note: buildInstructionOperandReference may insert new AsmOperands, so
1420 // don't precompute the loop bound.
1421 for (unsigned i = 0; i != II->AsmOperands.size(); ++i) {
1422 MatchableInfo::AsmOperand &Op = II->AsmOperands[i];
1423 StringRef Token = Op.Token;
1425 // Check for singleton registers.
1426 if (Record *RegRecord = II->AsmOperands[i].SingletonReg) {
1427 Op.Class = RegisterClasses[RegRecord];
1428 assert(Op.Class && Op.Class->Registers.size() == 1 &&
1429 "Unexpected class for singleton register");
1433 // Check for simple tokens.
1434 if (Token[0] != '$') {
1435 Op.Class = getTokenClass(Token);
1439 if (Token.size() > 1 && isdigit(Token[1])) {
1440 Op.Class = getTokenClass(Token);
1444 // Otherwise this is an operand reference.
1445 StringRef OperandName;
1446 if (Token[1] == '{')
1447 OperandName = Token.substr(2, Token.size() - 3);
1449 OperandName = Token.substr(1);
1451 if (II->DefRec.is<const CodeGenInstruction*>())
1452 buildInstructionOperandReference(II, OperandName, i);
1454 buildAliasOperandReference(II, OperandName, Op);
1457 if (II->DefRec.is<const CodeGenInstruction*>()) {
1458 II->buildInstructionResultOperands();
1459 // If the instruction has a two-operand alias, build up the
1460 // matchable here. We'll add them in bulk at the end to avoid
1461 // confusing this loop.
1462 std::string Constraint =
1463 II->TheDef->getValueAsString("TwoOperandAliasConstraint");
1464 if (Constraint != "") {
1465 // Start by making a copy of the original matchable.
1466 OwningPtr<MatchableInfo> AliasII(new MatchableInfo(*II));
1468 // Adjust it to be a two-operand alias.
1469 AliasII->formTwoOperandAlias(Constraint);
1471 // Add the alias to the matchables list.
1472 NewMatchables.push_back(AliasII.take());
1475 II->buildAliasResultOperands();
1477 if (!NewMatchables.empty())
1478 Matchables.insert(Matchables.end(), NewMatchables.begin(),
1479 NewMatchables.end());
1481 // Process token alias definitions and set up the associated superclass
1483 std::vector<Record*> AllTokenAliases =
1484 Records.getAllDerivedDefinitions("TokenAlias");
1485 for (unsigned i = 0, e = AllTokenAliases.size(); i != e; ++i) {
1486 Record *Rec = AllTokenAliases[i];
1487 ClassInfo *FromClass = getTokenClass(Rec->getValueAsString("FromToken"));
1488 ClassInfo *ToClass = getTokenClass(Rec->getValueAsString("ToToken"));
1489 if (FromClass == ToClass)
1490 PrintFatalError(Rec->getLoc(),
1491 "error: Destination value identical to source value.");
1492 FromClass->SuperClasses.push_back(ToClass);
1495 // Reorder classes so that classes precede super classes.
1496 std::sort(Classes.begin(), Classes.end(), less_ptr<ClassInfo>());
1499 /// buildInstructionOperandReference - The specified operand is a reference to a
1500 /// named operand such as $src. Resolve the Class and OperandInfo pointers.
1501 void AsmMatcherInfo::
1502 buildInstructionOperandReference(MatchableInfo *II,
1503 StringRef OperandName,
1504 unsigned AsmOpIdx) {
1505 const CodeGenInstruction &CGI = *II->DefRec.get<const CodeGenInstruction*>();
1506 const CGIOperandList &Operands = CGI.Operands;
1507 MatchableInfo::AsmOperand *Op = &II->AsmOperands[AsmOpIdx];
1509 // Map this token to an operand.
1511 if (!Operands.hasOperandNamed(OperandName, Idx))
1512 PrintFatalError(II->TheDef->getLoc(), "error: unable to find operand: '" +
1513 OperandName.str() + "'");
1515 // If the instruction operand has multiple suboperands, but the parser
1516 // match class for the asm operand is still the default "ImmAsmOperand",
1517 // then handle each suboperand separately.
1518 if (Op->SubOpIdx == -1 && Operands[Idx].MINumOperands > 1) {
1519 Record *Rec = Operands[Idx].Rec;
1520 assert(Rec->isSubClassOf("Operand") && "Unexpected operand!");
1521 Record *MatchClass = Rec->getValueAsDef("ParserMatchClass");
1522 if (MatchClass && MatchClass->getValueAsString("Name") == "Imm") {
1523 // Insert remaining suboperands after AsmOpIdx in II->AsmOperands.
1524 StringRef Token = Op->Token; // save this in case Op gets moved
1525 for (unsigned SI = 1, SE = Operands[Idx].MINumOperands; SI != SE; ++SI) {
1526 MatchableInfo::AsmOperand NewAsmOp(Token);
1527 NewAsmOp.SubOpIdx = SI;
1528 II->AsmOperands.insert(II->AsmOperands.begin()+AsmOpIdx+SI, NewAsmOp);
1530 // Replace Op with first suboperand.
1531 Op = &II->AsmOperands[AsmOpIdx]; // update the pointer in case it moved
1536 // Set up the operand class.
1537 Op->Class = getOperandClass(Operands[Idx], Op->SubOpIdx);
1539 // If the named operand is tied, canonicalize it to the untied operand.
1540 // For example, something like:
1541 // (outs GPR:$dst), (ins GPR:$src)
1542 // with an asmstring of
1544 // we want to canonicalize to:
1546 // so that we know how to provide the $dst operand when filling in the result.
1548 if (Operands[Idx].MINumOperands == 1)
1549 OITied = Operands[Idx].getTiedRegister();
1551 // The tied operand index is an MIOperand index, find the operand that
1553 std::pair<unsigned, unsigned> Idx = Operands.getSubOperandNumber(OITied);
1554 OperandName = Operands[Idx.first].Name;
1555 Op->SubOpIdx = Idx.second;
1558 Op->SrcOpName = OperandName;
1561 /// buildAliasOperandReference - When parsing an operand reference out of the
1562 /// matching string (e.g. "movsx $src, $dst"), determine what the class of the
1563 /// operand reference is by looking it up in the result pattern definition.
1564 void AsmMatcherInfo::buildAliasOperandReference(MatchableInfo *II,
1565 StringRef OperandName,
1566 MatchableInfo::AsmOperand &Op) {
1567 const CodeGenInstAlias &CGA = *II->DefRec.get<const CodeGenInstAlias*>();
1569 // Set up the operand class.
1570 for (unsigned i = 0, e = CGA.ResultOperands.size(); i != e; ++i)
1571 if (CGA.ResultOperands[i].isRecord() &&
1572 CGA.ResultOperands[i].getName() == OperandName) {
1573 // It's safe to go with the first one we find, because CodeGenInstAlias
1574 // validates that all operands with the same name have the same record.
1575 Op.SubOpIdx = CGA.ResultInstOperandIndex[i].second;
1576 // Use the match class from the Alias definition, not the
1577 // destination instruction, as we may have an immediate that's
1578 // being munged by the match class.
1579 Op.Class = getOperandClass(CGA.ResultOperands[i].getRecord(),
1581 Op.SrcOpName = OperandName;
1585 PrintFatalError(II->TheDef->getLoc(), "error: unable to find operand: '" +
1586 OperandName.str() + "'");
1589 void MatchableInfo::buildInstructionResultOperands() {
1590 const CodeGenInstruction *ResultInst = getResultInst();
1592 // Loop over all operands of the result instruction, determining how to
1594 for (unsigned i = 0, e = ResultInst->Operands.size(); i != e; ++i) {
1595 const CGIOperandList::OperandInfo &OpInfo = ResultInst->Operands[i];
1597 // If this is a tied operand, just copy from the previously handled operand.
1599 if (OpInfo.MINumOperands == 1)
1600 TiedOp = OpInfo.getTiedRegister();
1602 ResOperands.push_back(ResOperand::getTiedOp(TiedOp));
1606 // Find out what operand from the asmparser this MCInst operand comes from.
1607 int SrcOperand = findAsmOperandNamed(OpInfo.Name);
1608 if (OpInfo.Name.empty() || SrcOperand == -1) {
1609 // This may happen for operands that are tied to a suboperand of a
1610 // complex operand. Simply use a dummy value here; nobody should
1611 // use this operand slot.
1612 // FIXME: The long term goal is for the MCOperand list to not contain
1613 // tied operands at all.
1614 ResOperands.push_back(ResOperand::getImmOp(0));
1618 // Check if the one AsmOperand populates the entire operand.
1619 unsigned NumOperands = OpInfo.MINumOperands;
1620 if (AsmOperands[SrcOperand].SubOpIdx == -1) {
1621 ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand, NumOperands));
1625 // Add a separate ResOperand for each suboperand.
1626 for (unsigned AI = 0; AI < NumOperands; ++AI) {
1627 assert(AsmOperands[SrcOperand+AI].SubOpIdx == (int)AI &&
1628 AsmOperands[SrcOperand+AI].SrcOpName == OpInfo.Name &&
1629 "unexpected AsmOperands for suboperands");
1630 ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand + AI, 1));
1635 void MatchableInfo::buildAliasResultOperands() {
1636 const CodeGenInstAlias &CGA = *DefRec.get<const CodeGenInstAlias*>();
1637 const CodeGenInstruction *ResultInst = getResultInst();
1639 // Loop over all operands of the result instruction, determining how to
1641 unsigned AliasOpNo = 0;
1642 unsigned LastOpNo = CGA.ResultInstOperandIndex.size();
1643 for (unsigned i = 0, e = ResultInst->Operands.size(); i != e; ++i) {
1644 const CGIOperandList::OperandInfo *OpInfo = &ResultInst->Operands[i];
1646 // If this is a tied operand, just copy from the previously handled operand.
1648 if (OpInfo->MINumOperands == 1)
1649 TiedOp = OpInfo->getTiedRegister();
1651 ResOperands.push_back(ResOperand::getTiedOp(TiedOp));
1655 // Handle all the suboperands for this operand.
1656 const std::string &OpName = OpInfo->Name;
1657 for ( ; AliasOpNo < LastOpNo &&
1658 CGA.ResultInstOperandIndex[AliasOpNo].first == i; ++AliasOpNo) {
1659 int SubIdx = CGA.ResultInstOperandIndex[AliasOpNo].second;
1661 // Find out what operand from the asmparser that this MCInst operand
1663 switch (CGA.ResultOperands[AliasOpNo].Kind) {
1664 case CodeGenInstAlias::ResultOperand::K_Record: {
1665 StringRef Name = CGA.ResultOperands[AliasOpNo].getName();
1666 int SrcOperand = findAsmOperand(Name, SubIdx);
1667 if (SrcOperand == -1)
1668 PrintFatalError(TheDef->getLoc(), "Instruction '" +
1669 TheDef->getName() + "' has operand '" + OpName +
1670 "' that doesn't appear in asm string!");
1671 unsigned NumOperands = (SubIdx == -1 ? OpInfo->MINumOperands : 1);
1672 ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand,
1676 case CodeGenInstAlias::ResultOperand::K_Imm: {
1677 int64_t ImmVal = CGA.ResultOperands[AliasOpNo].getImm();
1678 ResOperands.push_back(ResOperand::getImmOp(ImmVal));
1681 case CodeGenInstAlias::ResultOperand::K_Reg: {
1682 Record *Reg = CGA.ResultOperands[AliasOpNo].getRegister();
1683 ResOperands.push_back(ResOperand::getRegOp(Reg));
1691 static unsigned getConverterOperandID(const std::string &Name,
1692 SetVector<std::string> &Table,
1694 IsNew = Table.insert(Name);
1696 unsigned ID = IsNew ? Table.size() - 1 :
1697 std::find(Table.begin(), Table.end(), Name) - Table.begin();
1699 assert(ID < Table.size());
1705 static void emitConvertFuncs(CodeGenTarget &Target, StringRef ClassName,
1706 std::vector<MatchableInfo*> &Infos,
1708 SetVector<std::string> OperandConversionKinds;
1709 SetVector<std::string> InstructionConversionKinds;
1710 std::vector<std::vector<uint8_t> > ConversionTable;
1711 size_t MaxRowLength = 2; // minimum is custom converter plus terminator.
1713 // TargetOperandClass - This is the target's operand class, like X86Operand.
1714 std::string TargetOperandClass = Target.getName() + "Operand";
1716 // Write the convert function to a separate stream, so we can drop it after
1717 // the enum. We'll build up the conversion handlers for the individual
1718 // operand types opportunistically as we encounter them.
1719 std::string ConvertFnBody;
1720 raw_string_ostream CvtOS(ConvertFnBody);
1721 // Start the unified conversion function.
1722 CvtOS << "void " << Target.getName() << ClassName << "::\n"
1723 << "convertToMCInst(unsigned Kind, MCInst &Inst, "
1724 << "unsigned Opcode,\n"
1725 << " const SmallVectorImpl<MCParsedAsmOperand*"
1726 << "> &Operands) {\n"
1727 << " assert(Kind < CVT_NUM_SIGNATURES && \"Invalid signature!\");\n"
1728 << " const uint8_t *Converter = ConversionTable[Kind];\n"
1729 << " Inst.setOpcode(Opcode);\n"
1730 << " for (const uint8_t *p = Converter; *p; p+= 2) {\n"
1731 << " switch (*p) {\n"
1732 << " default: llvm_unreachable(\"invalid conversion entry!\");\n"
1733 << " case CVT_Reg:\n"
1734 << " static_cast<" << TargetOperandClass
1735 << "*>(Operands[*(p + 1)])->addRegOperands(Inst, 1);\n"
1737 << " case CVT_Tied:\n"
1738 << " Inst.addOperand(Inst.getOperand(*(p + 1)));\n"
1741 std::string OperandFnBody;
1742 raw_string_ostream OpOS(OperandFnBody);
1743 // Start the operand number lookup function.
1744 OpOS << "void " << Target.getName() << ClassName << "::\n"
1745 << "convertToMapAndConstraints(unsigned Kind,\n";
1747 OpOS << "const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {\n"
1748 << " assert(Kind < CVT_NUM_SIGNATURES && \"Invalid signature!\");\n"
1749 << " unsigned NumMCOperands = 0;\n"
1750 << " const uint8_t *Converter = ConversionTable[Kind];\n"
1751 << " for (const uint8_t *p = Converter; *p; p+= 2) {\n"
1752 << " switch (*p) {\n"
1753 << " default: llvm_unreachable(\"invalid conversion entry!\");\n"
1754 << " case CVT_Reg:\n"
1755 << " Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n"
1756 << " Operands[*(p + 1)]->setConstraint(\"r\");\n"
1757 << " ++NumMCOperands;\n"
1759 << " case CVT_Tied:\n"
1760 << " ++NumMCOperands;\n"
1763 // Pre-populate the operand conversion kinds with the standard always
1764 // available entries.
1765 OperandConversionKinds.insert("CVT_Done");
1766 OperandConversionKinds.insert("CVT_Reg");
1767 OperandConversionKinds.insert("CVT_Tied");
1768 enum { CVT_Done, CVT_Reg, CVT_Tied };
1770 for (std::vector<MatchableInfo*>::const_iterator it = Infos.begin(),
1771 ie = Infos.end(); it != ie; ++it) {
1772 MatchableInfo &II = **it;
1774 // Check if we have a custom match function.
1775 std::string AsmMatchConverter =
1776 II.getResultInst()->TheDef->getValueAsString("AsmMatchConverter");
1777 if (!AsmMatchConverter.empty()) {
1778 std::string Signature = "ConvertCustom_" + AsmMatchConverter;
1779 II.ConversionFnKind = Signature;
1781 // Check if we have already generated this signature.
1782 if (!InstructionConversionKinds.insert(Signature))
1785 // Remember this converter for the kind enum.
1786 unsigned KindID = OperandConversionKinds.size();
1787 OperandConversionKinds.insert("CVT_" +
1788 getEnumNameForToken(AsmMatchConverter));
1790 // Add the converter row for this instruction.
1791 ConversionTable.push_back(std::vector<uint8_t>());
1792 ConversionTable.back().push_back(KindID);
1793 ConversionTable.back().push_back(CVT_Done);
1795 // Add the handler to the conversion driver function.
1796 CvtOS << " case CVT_"
1797 << getEnumNameForToken(AsmMatchConverter) << ":\n"
1798 << " " << AsmMatchConverter << "(Inst, Operands);\n"
1801 // FIXME: Handle the operand number lookup for custom match functions.
1805 // Build the conversion function signature.
1806 std::string Signature = "Convert";
1808 std::vector<uint8_t> ConversionRow;
1810 // Compute the convert enum and the case body.
1811 MaxRowLength = std::max(MaxRowLength, II.ResOperands.size()*2 + 1 );
1813 for (unsigned i = 0, e = II.ResOperands.size(); i != e; ++i) {
1814 const MatchableInfo::ResOperand &OpInfo = II.ResOperands[i];
1816 // Generate code to populate each result operand.
1817 switch (OpInfo.Kind) {
1818 case MatchableInfo::ResOperand::RenderAsmOperand: {
1819 // This comes from something we parsed.
1820 MatchableInfo::AsmOperand &Op = II.AsmOperands[OpInfo.AsmOperandNum];
1822 // Registers are always converted the same, don't duplicate the
1823 // conversion function based on them.
1826 Class = Op.Class->isRegisterClass() ? "Reg" : Op.Class->ClassName;
1828 Signature += utostr(OpInfo.MINumOperands);
1829 Signature += "_" + itostr(OpInfo.AsmOperandNum);
1831 // Add the conversion kind, if necessary, and get the associated ID
1832 // the index of its entry in the vector).
1833 std::string Name = "CVT_" + (Op.Class->isRegisterClass() ? "Reg" :
1834 Op.Class->RenderMethod);
1835 Name = getEnumNameForToken(Name);
1837 bool IsNewConverter = false;
1838 unsigned ID = getConverterOperandID(Name, OperandConversionKinds,
1841 // Add the operand entry to the instruction kind conversion row.
1842 ConversionRow.push_back(ID);
1843 ConversionRow.push_back(OpInfo.AsmOperandNum + 1);
1845 if (!IsNewConverter)
1848 // This is a new operand kind. Add a handler for it to the
1849 // converter driver.
1850 CvtOS << " case " << Name << ":\n"
1851 << " static_cast<" << TargetOperandClass
1852 << "*>(Operands[*(p + 1)])->"
1853 << Op.Class->RenderMethod << "(Inst, " << OpInfo.MINumOperands
1857 // Add a handler for the operand number lookup.
1858 OpOS << " case " << Name << ":\n"
1859 << " Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n";
1861 if (Op.Class->isRegisterClass())
1862 OpOS << " Operands[*(p + 1)]->setConstraint(\"r\");\n";
1864 OpOS << " Operands[*(p + 1)]->setConstraint(\"m\");\n";
1865 OpOS << " NumMCOperands += " << OpInfo.MINumOperands << ";\n"
1869 case MatchableInfo::ResOperand::TiedOperand: {
1870 // If this operand is tied to a previous one, just copy the MCInst
1871 // operand from the earlier one.We can only tie single MCOperand values.
1872 assert(OpInfo.MINumOperands == 1 && "Not a singular MCOperand");
1873 unsigned TiedOp = OpInfo.TiedOperandNum;
1874 assert(i > TiedOp && "Tied operand precedes its target!");
1875 Signature += "__Tie" + utostr(TiedOp);
1876 ConversionRow.push_back(CVT_Tied);
1877 ConversionRow.push_back(TiedOp);
1880 case MatchableInfo::ResOperand::ImmOperand: {
1881 int64_t Val = OpInfo.ImmVal;
1882 std::string Ty = "imm_" + itostr(Val);
1883 Signature += "__" + Ty;
1885 std::string Name = "CVT_" + Ty;
1886 bool IsNewConverter = false;
1887 unsigned ID = getConverterOperandID(Name, OperandConversionKinds,
1889 // Add the operand entry to the instruction kind conversion row.
1890 ConversionRow.push_back(ID);
1891 ConversionRow.push_back(0);
1893 if (!IsNewConverter)
1896 CvtOS << " case " << Name << ":\n"
1897 << " Inst.addOperand(MCOperand::CreateImm(" << Val << "));\n"
1900 OpOS << " case " << Name << ":\n"
1901 << " Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n"
1902 << " Operands[*(p + 1)]->setConstraint(\"\");\n"
1903 << " ++NumMCOperands;\n"
1907 case MatchableInfo::ResOperand::RegOperand: {
1908 std::string Reg, Name;
1909 if (OpInfo.Register == 0) {
1913 Reg = getQualifiedName(OpInfo.Register);
1914 Name = "reg" + OpInfo.Register->getName();
1916 Signature += "__" + Name;
1917 Name = "CVT_" + Name;
1918 bool IsNewConverter = false;
1919 unsigned ID = getConverterOperandID(Name, OperandConversionKinds,
1921 // Add the operand entry to the instruction kind conversion row.
1922 ConversionRow.push_back(ID);
1923 ConversionRow.push_back(0);
1925 if (!IsNewConverter)
1927 CvtOS << " case " << Name << ":\n"
1928 << " Inst.addOperand(MCOperand::CreateReg(" << Reg << "));\n"
1931 OpOS << " case " << Name << ":\n"
1932 << " Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n"
1933 << " Operands[*(p + 1)]->setConstraint(\"m\");\n"
1934 << " ++NumMCOperands;\n"
1940 // If there were no operands, add to the signature to that effect
1941 if (Signature == "Convert")
1942 Signature += "_NoOperands";
1944 II.ConversionFnKind = Signature;
1946 // Save the signature. If we already have it, don't add a new row
1948 if (!InstructionConversionKinds.insert(Signature))
1951 // Add the row to the table.
1952 ConversionTable.push_back(ConversionRow);
1955 // Finish up the converter driver function.
1956 CvtOS << " }\n }\n}\n\n";
1958 // Finish up the operand number lookup function.
1959 OpOS << " }\n }\n}\n\n";
1961 OS << "namespace {\n";
1963 // Output the operand conversion kind enum.
1964 OS << "enum OperatorConversionKind {\n";
1965 for (unsigned i = 0, e = OperandConversionKinds.size(); i != e; ++i)
1966 OS << " " << OperandConversionKinds[i] << ",\n";
1967 OS << " CVT_NUM_CONVERTERS\n";
1970 // Output the instruction conversion kind enum.
1971 OS << "enum InstructionConversionKind {\n";
1972 for (SetVector<std::string>::const_iterator
1973 i = InstructionConversionKinds.begin(),
1974 e = InstructionConversionKinds.end(); i != e; ++i)
1975 OS << " " << *i << ",\n";
1976 OS << " CVT_NUM_SIGNATURES\n";
1980 OS << "} // end anonymous namespace\n\n";
1982 // Output the conversion table.
1983 OS << "static const uint8_t ConversionTable[CVT_NUM_SIGNATURES]["
1984 << MaxRowLength << "] = {\n";
1986 for (unsigned Row = 0, ERow = ConversionTable.size(); Row != ERow; ++Row) {
1987 assert(ConversionTable[Row].size() % 2 == 0 && "bad conversion row!");
1988 OS << " // " << InstructionConversionKinds[Row] << "\n";
1990 for (unsigned i = 0, e = ConversionTable[Row].size(); i != e; i += 2)
1991 OS << OperandConversionKinds[ConversionTable[Row][i]] << ", "
1992 << (unsigned)(ConversionTable[Row][i + 1]) << ", ";
1993 OS << "CVT_Done },\n";
1998 // Spit out the conversion driver function.
2001 // Spit out the operand number lookup function.
2005 /// emitMatchClassEnumeration - Emit the enumeration for match class kinds.
2006 static void emitMatchClassEnumeration(CodeGenTarget &Target,
2007 std::vector<ClassInfo*> &Infos,
2009 OS << "namespace {\n\n";
2011 OS << "/// MatchClassKind - The kinds of classes which participate in\n"
2012 << "/// instruction matching.\n";
2013 OS << "enum MatchClassKind {\n";
2014 OS << " InvalidMatchClass = 0,\n";
2015 for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
2016 ie = Infos.end(); it != ie; ++it) {
2017 ClassInfo &CI = **it;
2018 OS << " " << CI.Name << ", // ";
2019 if (CI.Kind == ClassInfo::Token) {
2020 OS << "'" << CI.ValueName << "'\n";
2021 } else if (CI.isRegisterClass()) {
2022 if (!CI.ValueName.empty())
2023 OS << "register class '" << CI.ValueName << "'\n";
2025 OS << "derived register class\n";
2027 OS << "user defined class '" << CI.ValueName << "'\n";
2030 OS << " NumMatchClassKinds\n";
2036 /// emitValidateOperandClass - Emit the function to validate an operand class.
2037 static void emitValidateOperandClass(AsmMatcherInfo &Info,
2039 OS << "static unsigned validateOperandClass(MCParsedAsmOperand *GOp, "
2040 << "MatchClassKind Kind) {\n";
2041 OS << " " << Info.Target.getName() << "Operand &Operand = *("
2042 << Info.Target.getName() << "Operand*)GOp;\n";
2044 // The InvalidMatchClass is not to match any operand.
2045 OS << " if (Kind == InvalidMatchClass)\n";
2046 OS << " return MCTargetAsmParser::Match_InvalidOperand;\n\n";
2048 // Check for Token operands first.
2049 // FIXME: Use a more specific diagnostic type.
2050 OS << " if (Operand.isToken())\n";
2051 OS << " return isSubclass(matchTokenString(Operand.getToken()), Kind) ?\n"
2052 << " MCTargetAsmParser::Match_Success :\n"
2053 << " MCTargetAsmParser::Match_InvalidOperand;\n\n";
2055 // Check the user classes. We don't care what order since we're only
2056 // actually matching against one of them.
2057 for (std::vector<ClassInfo*>::iterator it = Info.Classes.begin(),
2058 ie = Info.Classes.end(); it != ie; ++it) {
2059 ClassInfo &CI = **it;
2061 if (!CI.isUserClass())
2064 OS << " // '" << CI.ClassName << "' class\n";
2065 OS << " if (Kind == " << CI.Name << ") {\n";
2066 OS << " if (Operand." << CI.PredicateMethod << "())\n";
2067 OS << " return MCTargetAsmParser::Match_Success;\n";
2068 if (!CI.DiagnosticType.empty())
2069 OS << " return " << Info.Target.getName() << "AsmParser::Match_"
2070 << CI.DiagnosticType << ";\n";
2074 // Check for register operands, including sub-classes.
2075 OS << " if (Operand.isReg()) {\n";
2076 OS << " MatchClassKind OpKind;\n";
2077 OS << " switch (Operand.getReg()) {\n";
2078 OS << " default: OpKind = InvalidMatchClass; break;\n";
2079 for (AsmMatcherInfo::RegisterClassesTy::iterator
2080 it = Info.RegisterClasses.begin(), ie = Info.RegisterClasses.end();
2082 OS << " case " << Info.Target.getName() << "::"
2083 << it->first->getName() << ": OpKind = " << it->second->Name
2086 OS << " return isSubclass(OpKind, Kind) ? "
2087 << "MCTargetAsmParser::Match_Success :\n "
2088 << " MCTargetAsmParser::Match_InvalidOperand;\n }\n\n";
2090 // Generic fallthrough match failure case for operands that don't have
2091 // specialized diagnostic types.
2092 OS << " return MCTargetAsmParser::Match_InvalidOperand;\n";
2096 /// emitIsSubclass - Emit the subclass predicate function.
2097 static void emitIsSubclass(CodeGenTarget &Target,
2098 std::vector<ClassInfo*> &Infos,
2100 OS << "/// isSubclass - Compute whether \\p A is a subclass of \\p B.\n";
2101 OS << "static bool isSubclass(MatchClassKind A, MatchClassKind B) {\n";
2102 OS << " if (A == B)\n";
2103 OS << " return true;\n\n";
2106 raw_string_ostream SS(OStr);
2108 SS << " switch (A) {\n";
2109 SS << " default:\n";
2110 SS << " return false;\n";
2111 for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
2112 ie = Infos.end(); it != ie; ++it) {
2113 ClassInfo &A = **it;
2115 std::vector<StringRef> SuperClasses;
2116 for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
2117 ie = Infos.end(); it != ie; ++it) {
2118 ClassInfo &B = **it;
2120 if (&A != &B && A.isSubsetOf(B))
2121 SuperClasses.push_back(B.Name);
2124 if (SuperClasses.empty())
2128 SS << "\n case " << A.Name << ":\n";
2130 if (SuperClasses.size() == 1) {
2131 SS << " return B == " << SuperClasses.back().str() << ";\n";
2135 if (!SuperClasses.empty()) {
2136 SS << " switch (B) {\n";
2137 SS << " default: return false;\n";
2138 for (unsigned i = 0, e = SuperClasses.size(); i != e; ++i)
2139 SS << " case " << SuperClasses[i].str() << ": return true;\n";
2142 // No case statement to emit
2143 SS << " return false;\n";
2148 // If there were case statements emitted into the string stream, write them
2149 // to the output stream, otherwise write the default.
2153 OS << " return false;\n";
2158 /// emitMatchTokenString - Emit the function to match a token string to the
2159 /// appropriate match class value.
2160 static void emitMatchTokenString(CodeGenTarget &Target,
2161 std::vector<ClassInfo*> &Infos,
2163 // Construct the match list.
2164 std::vector<StringMatcher::StringPair> Matches;
2165 for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
2166 ie = Infos.end(); it != ie; ++it) {
2167 ClassInfo &CI = **it;
2169 if (CI.Kind == ClassInfo::Token)
2170 Matches.push_back(StringMatcher::StringPair(CI.ValueName,
2171 "return " + CI.Name + ";"));
2174 OS << "static MatchClassKind matchTokenString(StringRef Name) {\n";
2176 StringMatcher("Name", Matches, OS).Emit();
2178 OS << " return InvalidMatchClass;\n";
2182 /// emitMatchRegisterName - Emit the function to match a string to the target
2183 /// specific register enum.
2184 static void emitMatchRegisterName(CodeGenTarget &Target, Record *AsmParser,
2186 // Construct the match list.
2187 std::vector<StringMatcher::StringPair> Matches;
2188 const std::vector<CodeGenRegister*> &Regs =
2189 Target.getRegBank().getRegisters();
2190 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
2191 const CodeGenRegister *Reg = Regs[i];
2192 if (Reg->TheDef->getValueAsString("AsmName").empty())
2195 Matches.push_back(StringMatcher::StringPair(
2196 Reg->TheDef->getValueAsString("AsmName"),
2197 "return " + utostr(Reg->EnumValue) + ";"));
2200 OS << "static unsigned MatchRegisterName(StringRef Name) {\n";
2202 StringMatcher("Name", Matches, OS).Emit();
2204 OS << " return 0;\n";
2208 /// emitSubtargetFeatureFlagEnumeration - Emit the subtarget feature flag
2210 static void emitSubtargetFeatureFlagEnumeration(AsmMatcherInfo &Info,
2212 OS << "// Flags for subtarget features that participate in "
2213 << "instruction matching.\n";
2214 OS << "enum SubtargetFeatureFlag {\n";
2215 for (std::map<Record*, SubtargetFeatureInfo*, LessRecordByID>::const_iterator
2216 it = Info.SubtargetFeatures.begin(),
2217 ie = Info.SubtargetFeatures.end(); it != ie; ++it) {
2218 SubtargetFeatureInfo &SFI = *it->second;
2219 OS << " " << SFI.getEnumName() << " = (1 << " << SFI.Index << "),\n";
2221 OS << " Feature_None = 0\n";
2225 /// emitOperandDiagnosticTypes - Emit the operand matching diagnostic types.
2226 static void emitOperandDiagnosticTypes(AsmMatcherInfo &Info, raw_ostream &OS) {
2227 // Get the set of diagnostic types from all of the operand classes.
2228 std::set<StringRef> Types;
2229 for (std::map<Record*, ClassInfo*>::const_iterator
2230 I = Info.AsmOperandClasses.begin(),
2231 E = Info.AsmOperandClasses.end(); I != E; ++I) {
2232 if (!I->second->DiagnosticType.empty())
2233 Types.insert(I->second->DiagnosticType);
2236 if (Types.empty()) return;
2238 // Now emit the enum entries.
2239 for (std::set<StringRef>::const_iterator I = Types.begin(), E = Types.end();
2241 OS << " Match_" << *I << ",\n";
2242 OS << " END_OPERAND_DIAGNOSTIC_TYPES\n";
2245 /// emitGetSubtargetFeatureName - Emit the helper function to get the
2246 /// user-level name for a subtarget feature.
2247 static void emitGetSubtargetFeatureName(AsmMatcherInfo &Info, raw_ostream &OS) {
2248 OS << "// User-level names for subtarget features that participate in\n"
2249 << "// instruction matching.\n"
2250 << "static const char *getSubtargetFeatureName(unsigned Val) {\n";
2251 if (!Info.SubtargetFeatures.empty()) {
2252 OS << " switch(Val) {\n";
2253 typedef std::map<Record*, SubtargetFeatureInfo*, LessRecordByID> RecFeatMap;
2254 for (RecFeatMap::const_iterator it = Info.SubtargetFeatures.begin(),
2255 ie = Info.SubtargetFeatures.end(); it != ie; ++it) {
2256 SubtargetFeatureInfo &SFI = *it->second;
2257 // FIXME: Totally just a placeholder name to get the algorithm working.
2258 OS << " case " << SFI.getEnumName() << ": return \""
2259 << SFI.TheDef->getValueAsString("PredicateName") << "\";\n";
2261 OS << " default: return \"(unknown)\";\n";
2264 // Nothing to emit, so skip the switch
2265 OS << " return \"(unknown)\";\n";
2270 /// emitComputeAvailableFeatures - Emit the function to compute the list of
2271 /// available features given a subtarget.
2272 static void emitComputeAvailableFeatures(AsmMatcherInfo &Info,
2274 std::string ClassName =
2275 Info.AsmParser->getValueAsString("AsmParserClassName");
2277 OS << "unsigned " << Info.Target.getName() << ClassName << "::\n"
2278 << "ComputeAvailableFeatures(uint64_t FB) const {\n";
2279 OS << " unsigned Features = 0;\n";
2280 for (std::map<Record*, SubtargetFeatureInfo*, LessRecordByID>::const_iterator
2281 it = Info.SubtargetFeatures.begin(),
2282 ie = Info.SubtargetFeatures.end(); it != ie; ++it) {
2283 SubtargetFeatureInfo &SFI = *it->second;
2286 std::string CondStorage =
2287 SFI.TheDef->getValueAsString("AssemblerCondString");
2288 StringRef Conds = CondStorage;
2289 std::pair<StringRef,StringRef> Comma = Conds.split(',');
2296 StringRef Cond = Comma.first;
2297 if (Cond[0] == '!') {
2299 Cond = Cond.substr(1);
2302 OS << "((FB & " << Info.Target.getName() << "::" << Cond << ")";
2309 if (Comma.second.empty())
2313 Comma = Comma.second.split(',');
2317 OS << " Features |= " << SFI.getEnumName() << ";\n";
2319 OS << " return Features;\n";
2323 static std::string GetAliasRequiredFeatures(Record *R,
2324 const AsmMatcherInfo &Info) {
2325 std::vector<Record*> ReqFeatures = R->getValueAsListOfDefs("Predicates");
2327 unsigned NumFeatures = 0;
2328 for (unsigned i = 0, e = ReqFeatures.size(); i != e; ++i) {
2329 SubtargetFeatureInfo *F = Info.getSubtargetFeature(ReqFeatures[i]);
2332 PrintFatalError(R->getLoc(), "Predicate '" + ReqFeatures[i]->getName() +
2333 "' is not marked as an AssemblerPredicate!");
2338 Result += F->getEnumName();
2342 if (NumFeatures > 1)
2343 Result = '(' + Result + ')';
2347 static void emitMnemonicAliasVariant(raw_ostream &OS,const AsmMatcherInfo &Info,
2348 std::vector<Record*> &Aliases,
2349 unsigned Indent = 0,
2350 StringRef AsmParserVariantName = StringRef()){
2351 // Keep track of all the aliases from a mnemonic. Use an std::map so that the
2352 // iteration order of the map is stable.
2353 std::map<std::string, std::vector<Record*> > AliasesFromMnemonic;
2355 for (unsigned i = 0, e = Aliases.size(); i != e; ++i) {
2356 Record *R = Aliases[i];
2357 // FIXME: Allow AssemblerVariantName to be a comma separated list.
2358 std::string AsmVariantName = R->getValueAsString("AsmVariantName");
2359 if (AsmVariantName != AsmParserVariantName)
2361 AliasesFromMnemonic[R->getValueAsString("FromMnemonic")].push_back(R);
2363 if (AliasesFromMnemonic.empty())
2366 // Process each alias a "from" mnemonic at a time, building the code executed
2367 // by the string remapper.
2368 std::vector<StringMatcher::StringPair> Cases;
2369 for (std::map<std::string, std::vector<Record*> >::iterator
2370 I = AliasesFromMnemonic.begin(), E = AliasesFromMnemonic.end();
2372 const std::vector<Record*> &ToVec = I->second;
2374 // Loop through each alias and emit code that handles each case. If there
2375 // are two instructions without predicates, emit an error. If there is one,
2377 std::string MatchCode;
2378 int AliasWithNoPredicate = -1;
2380 for (unsigned i = 0, e = ToVec.size(); i != e; ++i) {
2381 Record *R = ToVec[i];
2382 std::string FeatureMask = GetAliasRequiredFeatures(R, Info);
2384 // If this unconditionally matches, remember it for later and diagnose
2386 if (FeatureMask.empty()) {
2387 if (AliasWithNoPredicate != -1) {
2388 // We can't have two aliases from the same mnemonic with no predicate.
2389 PrintError(ToVec[AliasWithNoPredicate]->getLoc(),
2390 "two MnemonicAliases with the same 'from' mnemonic!");
2391 PrintFatalError(R->getLoc(), "this is the other MnemonicAlias.");
2394 AliasWithNoPredicate = i;
2397 if (R->getValueAsString("ToMnemonic") == I->first)
2398 PrintFatalError(R->getLoc(), "MnemonicAlias to the same string");
2400 if (!MatchCode.empty())
2401 MatchCode += "else ";
2402 MatchCode += "if ((Features & " + FeatureMask + ") == "+FeatureMask+")\n";
2403 MatchCode += " Mnemonic = \"" +R->getValueAsString("ToMnemonic")+"\";\n";
2406 if (AliasWithNoPredicate != -1) {
2407 Record *R = ToVec[AliasWithNoPredicate];
2408 if (!MatchCode.empty())
2409 MatchCode += "else\n ";
2410 MatchCode += "Mnemonic = \"" + R->getValueAsString("ToMnemonic")+"\";\n";
2413 MatchCode += "return;";
2415 Cases.push_back(std::make_pair(I->first, MatchCode));
2417 StringMatcher("Mnemonic", Cases, OS).Emit(Indent);
2420 /// emitMnemonicAliases - If the target has any MnemonicAlias<> definitions,
2421 /// emit a function for them and return true, otherwise return false.
2422 static bool emitMnemonicAliases(raw_ostream &OS, const AsmMatcherInfo &Info,
2423 CodeGenTarget &Target) {
2424 // Ignore aliases when match-prefix is set.
2425 if (!MatchPrefix.empty())
2428 std::vector<Record*> Aliases =
2429 Info.getRecords().getAllDerivedDefinitions("MnemonicAlias");
2430 if (Aliases.empty()) return false;
2432 OS << "static void applyMnemonicAliases(StringRef &Mnemonic, "
2433 "unsigned Features, unsigned VariantID) {\n";
2434 OS << " switch (VariantID) {\n";
2435 unsigned VariantCount = Target.getAsmParserVariantCount();
2436 for (unsigned VC = 0; VC != VariantCount; ++VC) {
2437 Record *AsmVariant = Target.getAsmParserVariant(VC);
2438 int AsmParserVariantNo = AsmVariant->getValueAsInt("Variant");
2439 std::string AsmParserVariantName = AsmVariant->getValueAsString("Name");
2440 OS << " case " << AsmParserVariantNo << ":\n";
2441 emitMnemonicAliasVariant(OS, Info, Aliases, /*Indent=*/2,
2442 AsmParserVariantName);
2447 // Emit aliases that apply to all variants.
2448 emitMnemonicAliasVariant(OS, Info, Aliases);
2455 static const char *getMinimalTypeForRange(uint64_t Range) {
2456 assert(Range < 0xFFFFFFFFULL && "Enum too large");
2464 static void emitCustomOperandParsing(raw_ostream &OS, CodeGenTarget &Target,
2465 const AsmMatcherInfo &Info, StringRef ClassName,
2466 StringToOffsetTable &StringTable,
2467 unsigned MaxMnemonicIndex) {
2468 unsigned MaxMask = 0;
2469 for (std::vector<OperandMatchEntry>::const_iterator it =
2470 Info.OperandMatchInfo.begin(), ie = Info.OperandMatchInfo.end();
2472 MaxMask |= it->OperandMask;
2475 // Emit the static custom operand parsing table;
2476 OS << "namespace {\n";
2477 OS << " struct OperandMatchEntry {\n";
2478 OS << " " << getMinimalTypeForRange(1ULL << Info.SubtargetFeatures.size())
2479 << " RequiredFeatures;\n";
2480 OS << " " << getMinimalTypeForRange(MaxMnemonicIndex)
2482 OS << " " << getMinimalTypeForRange(Info.Classes.size())
2484 OS << " " << getMinimalTypeForRange(MaxMask)
2485 << " OperandMask;\n\n";
2486 OS << " StringRef getMnemonic() const {\n";
2487 OS << " return StringRef(MnemonicTable + Mnemonic + 1,\n";
2488 OS << " MnemonicTable[Mnemonic]);\n";
2492 OS << " // Predicate for searching for an opcode.\n";
2493 OS << " struct LessOpcodeOperand {\n";
2494 OS << " bool operator()(const OperandMatchEntry &LHS, StringRef RHS) {\n";
2495 OS << " return LHS.getMnemonic() < RHS;\n";
2497 OS << " bool operator()(StringRef LHS, const OperandMatchEntry &RHS) {\n";
2498 OS << " return LHS < RHS.getMnemonic();\n";
2500 OS << " bool operator()(const OperandMatchEntry &LHS,";
2501 OS << " const OperandMatchEntry &RHS) {\n";
2502 OS << " return LHS.getMnemonic() < RHS.getMnemonic();\n";
2506 OS << "} // end anonymous namespace.\n\n";
2508 OS << "static const OperandMatchEntry OperandMatchTable["
2509 << Info.OperandMatchInfo.size() << "] = {\n";
2511 OS << " /* Operand List Mask, Mnemonic, Operand Class, Features */\n";
2512 for (std::vector<OperandMatchEntry>::const_iterator it =
2513 Info.OperandMatchInfo.begin(), ie = Info.OperandMatchInfo.end();
2515 const OperandMatchEntry &OMI = *it;
2516 const MatchableInfo &II = *OMI.MI;
2520 // Write the required features mask.
2521 if (!II.RequiredFeatures.empty()) {
2522 for (unsigned i = 0, e = II.RequiredFeatures.size(); i != e; ++i) {
2524 OS << II.RequiredFeatures[i]->getEnumName();
2529 // Store a pascal-style length byte in the mnemonic.
2530 std::string LenMnemonic = char(II.Mnemonic.size()) + II.Mnemonic.str();
2531 OS << ", " << StringTable.GetOrAddStringOffset(LenMnemonic, false)
2532 << " /* " << II.Mnemonic << " */, ";
2536 OS << ", " << OMI.OperandMask;
2538 bool printComma = false;
2539 for (int i = 0, e = 31; i !=e; ++i)
2540 if (OMI.OperandMask & (1 << i)) {
2552 // Emit the operand class switch to call the correct custom parser for
2553 // the found operand class.
2554 OS << Target.getName() << ClassName << "::OperandMatchResultTy "
2555 << Target.getName() << ClassName << "::\n"
2556 << "tryCustomParseOperand(SmallVectorImpl<MCParsedAsmOperand*>"
2557 << " &Operands,\n unsigned MCK) {\n\n"
2558 << " switch(MCK) {\n";
2560 for (std::vector<ClassInfo*>::const_iterator it = Info.Classes.begin(),
2561 ie = Info.Classes.end(); it != ie; ++it) {
2562 ClassInfo *CI = *it;
2563 if (CI->ParserMethod.empty())
2565 OS << " case " << CI->Name << ":\n"
2566 << " return " << CI->ParserMethod << "(Operands);\n";
2569 OS << " default:\n";
2570 OS << " return MatchOperand_NoMatch;\n";
2572 OS << " return MatchOperand_NoMatch;\n";
2575 // Emit the static custom operand parser. This code is very similar with
2576 // the other matcher. Also use MatchResultTy here just in case we go for
2577 // a better error handling.
2578 OS << Target.getName() << ClassName << "::OperandMatchResultTy "
2579 << Target.getName() << ClassName << "::\n"
2580 << "MatchOperandParserImpl(SmallVectorImpl<MCParsedAsmOperand*>"
2581 << " &Operands,\n StringRef Mnemonic) {\n";
2583 // Emit code to get the available features.
2584 OS << " // Get the current feature set.\n";
2585 OS << " unsigned AvailableFeatures = getAvailableFeatures();\n\n";
2587 OS << " // Get the next operand index.\n";
2588 OS << " unsigned NextOpNum = Operands.size()-1;\n";
2590 // Emit code to search the table.
2591 OS << " // Search the table.\n";
2592 OS << " std::pair<const OperandMatchEntry*, const OperandMatchEntry*>";
2593 OS << " MnemonicRange =\n";
2594 OS << " std::equal_range(OperandMatchTable, OperandMatchTable+"
2595 << Info.OperandMatchInfo.size() << ", Mnemonic,\n"
2596 << " LessOpcodeOperand());\n\n";
2598 OS << " if (MnemonicRange.first == MnemonicRange.second)\n";
2599 OS << " return MatchOperand_NoMatch;\n\n";
2601 OS << " for (const OperandMatchEntry *it = MnemonicRange.first,\n"
2602 << " *ie = MnemonicRange.second; it != ie; ++it) {\n";
2604 OS << " // equal_range guarantees that instruction mnemonic matches.\n";
2605 OS << " assert(Mnemonic == it->getMnemonic());\n\n";
2607 // Emit check that the required features are available.
2608 OS << " // check if the available features match\n";
2609 OS << " if ((AvailableFeatures & it->RequiredFeatures) "
2610 << "!= it->RequiredFeatures) {\n";
2611 OS << " continue;\n";
2614 // Emit check to ensure the operand number matches.
2615 OS << " // check if the operand in question has a custom parser.\n";
2616 OS << " if (!(it->OperandMask & (1 << NextOpNum)))\n";
2617 OS << " continue;\n\n";
2619 // Emit call to the custom parser method
2620 OS << " // call custom parse method to handle the operand\n";
2621 OS << " OperandMatchResultTy Result = ";
2622 OS << "tryCustomParseOperand(Operands, it->Class);\n";
2623 OS << " if (Result != MatchOperand_NoMatch)\n";
2624 OS << " return Result;\n";
2627 OS << " // Okay, we had no match.\n";
2628 OS << " return MatchOperand_NoMatch;\n";
2632 void AsmMatcherEmitter::run(raw_ostream &OS) {
2633 CodeGenTarget Target(Records);
2634 Record *AsmParser = Target.getAsmParser();
2635 std::string ClassName = AsmParser->getValueAsString("AsmParserClassName");
2637 // Compute the information on the instructions to match.
2638 AsmMatcherInfo Info(AsmParser, Target, Records);
2641 // Sort the instruction table using the partial order on classes. We use
2642 // stable_sort to ensure that ambiguous instructions are still
2643 // deterministically ordered.
2644 std::stable_sort(Info.Matchables.begin(), Info.Matchables.end(),
2645 less_ptr<MatchableInfo>());
2647 DEBUG_WITH_TYPE("instruction_info", {
2648 for (std::vector<MatchableInfo*>::iterator
2649 it = Info.Matchables.begin(), ie = Info.Matchables.end();
2654 // Check for ambiguous matchables.
2655 DEBUG_WITH_TYPE("ambiguous_instrs", {
2656 unsigned NumAmbiguous = 0;
2657 for (unsigned i = 0, e = Info.Matchables.size(); i != e; ++i) {
2658 for (unsigned j = i + 1; j != e; ++j) {
2659 MatchableInfo &A = *Info.Matchables[i];
2660 MatchableInfo &B = *Info.Matchables[j];
2662 if (A.couldMatchAmbiguouslyWith(B)) {
2663 errs() << "warning: ambiguous matchables:\n";
2665 errs() << "\nis incomparable with:\n";
2673 errs() << "warning: " << NumAmbiguous
2674 << " ambiguous matchables!\n";
2677 // Compute the information on the custom operand parsing.
2678 Info.buildOperandMatchInfo();
2680 // Write the output.
2682 // Information for the class declaration.
2683 OS << "\n#ifdef GET_ASSEMBLER_HEADER\n";
2684 OS << "#undef GET_ASSEMBLER_HEADER\n";
2685 OS << " // This should be included into the middle of the declaration of\n";
2686 OS << " // your subclasses implementation of MCTargetAsmParser.\n";
2687 OS << " unsigned ComputeAvailableFeatures(uint64_t FeatureBits) const;\n";
2688 OS << " void convertToMCInst(unsigned Kind, MCInst &Inst, "
2689 << "unsigned Opcode,\n"
2690 << " const SmallVectorImpl<MCParsedAsmOperand*> "
2692 OS << " void convertToMapAndConstraints(unsigned Kind,\n ";
2693 OS << " const SmallVectorImpl<MCParsedAsmOperand*> &Operands);\n";
2694 OS << " bool mnemonicIsValid(StringRef Mnemonic, unsigned VariantID);\n";
2695 OS << " unsigned MatchInstructionImpl(\n";
2697 OS << "const SmallVectorImpl<MCParsedAsmOperand*> &Operands,\n"
2698 << " MCInst &Inst,\n"
2699 << " unsigned &ErrorInfo,"
2700 << " bool matchingInlineAsm,\n"
2701 << " unsigned VariantID = 0);\n";
2703 if (Info.OperandMatchInfo.size()) {
2704 OS << "\n enum OperandMatchResultTy {\n";
2705 OS << " MatchOperand_Success, // operand matched successfully\n";
2706 OS << " MatchOperand_NoMatch, // operand did not match\n";
2707 OS << " MatchOperand_ParseFail // operand matched but had errors\n";
2709 OS << " OperandMatchResultTy MatchOperandParserImpl(\n";
2710 OS << " SmallVectorImpl<MCParsedAsmOperand*> &Operands,\n";
2711 OS << " StringRef Mnemonic);\n";
2713 OS << " OperandMatchResultTy tryCustomParseOperand(\n";
2714 OS << " SmallVectorImpl<MCParsedAsmOperand*> &Operands,\n";
2715 OS << " unsigned MCK);\n\n";
2718 OS << "#endif // GET_ASSEMBLER_HEADER_INFO\n\n";
2720 // Emit the operand match diagnostic enum names.
2721 OS << "\n#ifdef GET_OPERAND_DIAGNOSTIC_TYPES\n";
2722 OS << "#undef GET_OPERAND_DIAGNOSTIC_TYPES\n\n";
2723 emitOperandDiagnosticTypes(Info, OS);
2724 OS << "#endif // GET_OPERAND_DIAGNOSTIC_TYPES\n\n";
2727 OS << "\n#ifdef GET_REGISTER_MATCHER\n";
2728 OS << "#undef GET_REGISTER_MATCHER\n\n";
2730 // Emit the subtarget feature enumeration.
2731 emitSubtargetFeatureFlagEnumeration(Info, OS);
2733 // Emit the function to match a register name to number.
2734 // This should be omitted for Mips target
2735 if (AsmParser->getValueAsBit("ShouldEmitMatchRegisterName"))
2736 emitMatchRegisterName(Target, AsmParser, OS);
2738 OS << "#endif // GET_REGISTER_MATCHER\n\n";
2740 OS << "\n#ifdef GET_SUBTARGET_FEATURE_NAME\n";
2741 OS << "#undef GET_SUBTARGET_FEATURE_NAME\n\n";
2743 // Generate the helper function to get the names for subtarget features.
2744 emitGetSubtargetFeatureName(Info, OS);
2746 OS << "#endif // GET_SUBTARGET_FEATURE_NAME\n\n";
2748 OS << "\n#ifdef GET_MATCHER_IMPLEMENTATION\n";
2749 OS << "#undef GET_MATCHER_IMPLEMENTATION\n\n";
2751 // Generate the function that remaps for mnemonic aliases.
2752 bool HasMnemonicAliases = emitMnemonicAliases(OS, Info, Target);
2754 // Generate the convertToMCInst function to convert operands into an MCInst.
2755 // Also, generate the convertToMapAndConstraints function for MS-style inline
2756 // assembly. The latter doesn't actually generate a MCInst.
2757 emitConvertFuncs(Target, ClassName, Info.Matchables, OS);
2759 // Emit the enumeration for classes which participate in matching.
2760 emitMatchClassEnumeration(Target, Info.Classes, OS);
2762 // Emit the routine to match token strings to their match class.
2763 emitMatchTokenString(Target, Info.Classes, OS);
2765 // Emit the subclass predicate routine.
2766 emitIsSubclass(Target, Info.Classes, OS);
2768 // Emit the routine to validate an operand against a match class.
2769 emitValidateOperandClass(Info, OS);
2771 // Emit the available features compute function.
2772 emitComputeAvailableFeatures(Info, OS);
2775 StringToOffsetTable StringTable;
2777 size_t MaxNumOperands = 0;
2778 unsigned MaxMnemonicIndex = 0;
2779 bool HasDeprecation = false;
2780 for (std::vector<MatchableInfo*>::const_iterator it =
2781 Info.Matchables.begin(), ie = Info.Matchables.end();
2783 MatchableInfo &II = **it;
2784 MaxNumOperands = std::max(MaxNumOperands, II.AsmOperands.size());
2785 HasDeprecation |= II.HasDeprecation;
2787 // Store a pascal-style length byte in the mnemonic.
2788 std::string LenMnemonic = char(II.Mnemonic.size()) + II.Mnemonic.str();
2789 MaxMnemonicIndex = std::max(MaxMnemonicIndex,
2790 StringTable.GetOrAddStringOffset(LenMnemonic, false));
2793 OS << "static const char *const MnemonicTable =\n";
2794 StringTable.EmitString(OS);
2797 // Emit the static match table; unused classes get initalized to 0 which is
2798 // guaranteed to be InvalidMatchClass.
2800 // FIXME: We can reduce the size of this table very easily. First, we change
2801 // it so that store the kinds in separate bit-fields for each index, which
2802 // only needs to be the max width used for classes at that index (we also need
2803 // to reject based on this during classification). If we then make sure to
2804 // order the match kinds appropriately (putting mnemonics last), then we
2805 // should only end up using a few bits for each class, especially the ones
2806 // following the mnemonic.
2807 OS << "namespace {\n";
2808 OS << " struct MatchEntry {\n";
2809 OS << " " << getMinimalTypeForRange(MaxMnemonicIndex)
2811 OS << " uint16_t Opcode;\n";
2812 OS << " " << getMinimalTypeForRange(Info.Matchables.size())
2814 OS << " " << getMinimalTypeForRange(1ULL << Info.SubtargetFeatures.size())
2815 << " RequiredFeatures;\n";
2816 OS << " " << getMinimalTypeForRange(Info.Classes.size())
2817 << " Classes[" << MaxNumOperands << "];\n";
2818 OS << " StringRef getMnemonic() const {\n";
2819 OS << " return StringRef(MnemonicTable + Mnemonic + 1,\n";
2820 OS << " MnemonicTable[Mnemonic]);\n";
2824 OS << " // Predicate for searching for an opcode.\n";
2825 OS << " struct LessOpcode {\n";
2826 OS << " bool operator()(const MatchEntry &LHS, StringRef RHS) {\n";
2827 OS << " return LHS.getMnemonic() < RHS;\n";
2829 OS << " bool operator()(StringRef LHS, const MatchEntry &RHS) {\n";
2830 OS << " return LHS < RHS.getMnemonic();\n";
2832 OS << " bool operator()(const MatchEntry &LHS, const MatchEntry &RHS) {\n";
2833 OS << " return LHS.getMnemonic() < RHS.getMnemonic();\n";
2837 OS << "} // end anonymous namespace.\n\n";
2839 unsigned VariantCount = Target.getAsmParserVariantCount();
2840 for (unsigned VC = 0; VC != VariantCount; ++VC) {
2841 Record *AsmVariant = Target.getAsmParserVariant(VC);
2842 std::string CommentDelimiter =
2843 AsmVariant->getValueAsString("CommentDelimiter");
2844 std::string RegisterPrefix = AsmVariant->getValueAsString("RegisterPrefix");
2845 int AsmVariantNo = AsmVariant->getValueAsInt("Variant");
2847 OS << "static const MatchEntry MatchTable" << VC << "[] = {\n";
2849 for (std::vector<MatchableInfo*>::const_iterator it =
2850 Info.Matchables.begin(), ie = Info.Matchables.end();
2852 MatchableInfo &II = **it;
2853 if (II.AsmVariantID != AsmVariantNo)
2856 // Store a pascal-style length byte in the mnemonic.
2857 std::string LenMnemonic = char(II.Mnemonic.size()) + II.Mnemonic.str();
2858 OS << " { " << StringTable.GetOrAddStringOffset(LenMnemonic, false)
2859 << " /* " << II.Mnemonic << " */, "
2860 << Target.getName() << "::"
2861 << II.getResultInst()->TheDef->getName() << ", "
2862 << II.ConversionFnKind << ", ";
2864 // Write the required features mask.
2865 if (!II.RequiredFeatures.empty()) {
2866 for (unsigned i = 0, e = II.RequiredFeatures.size(); i != e; ++i) {
2868 OS << II.RequiredFeatures[i]->getEnumName();
2874 for (unsigned i = 0, e = II.AsmOperands.size(); i != e; ++i) {
2875 MatchableInfo::AsmOperand &Op = II.AsmOperands[i];
2878 OS << Op.Class->Name;
2886 // A method to determine if a mnemonic is in the list.
2887 OS << "bool " << Target.getName() << ClassName << "::\n"
2888 << "mnemonicIsValid(StringRef Mnemonic, unsigned VariantID) {\n";
2889 OS << " // Find the appropriate table for this asm variant.\n";
2890 OS << " const MatchEntry *Start, *End;\n";
2891 OS << " switch (VariantID) {\n";
2892 OS << " default: // unreachable\n";
2893 for (unsigned VC = 0; VC != VariantCount; ++VC) {
2894 Record *AsmVariant = Target.getAsmParserVariant(VC);
2895 std::string CommentDelimiter =
2896 AsmVariant->getValueAsString("CommentDelimiter");
2897 std::string RegisterPrefix = AsmVariant->getValueAsString("RegisterPrefix");
2898 int AsmVariantNo = AsmVariant->getValueAsInt("Variant");
2899 OS << " case " << AsmVariantNo << ": Start = MatchTable" << VC
2900 << "; End = array_endof(MatchTable" << VC << "); break;\n";
2903 OS << " // Search the table.\n";
2904 OS << " std::pair<const MatchEntry*, const MatchEntry*> MnemonicRange =\n";
2905 OS << " std::equal_range(Start, End, Mnemonic, LessOpcode());\n";
2906 OS << " return MnemonicRange.first != MnemonicRange.second;\n";
2909 // Finally, build the match function.
2911 << Target.getName() << ClassName << "::\n"
2912 << "MatchInstructionImpl(const SmallVectorImpl<MCParsedAsmOperand*>"
2914 OS << " MCInst &Inst,\n"
2915 << "unsigned &ErrorInfo, bool matchingInlineAsm, unsigned VariantID) {\n";
2917 OS << " // Eliminate obvious mismatches.\n";
2918 OS << " if (Operands.size() > " << (MaxNumOperands+1) << ") {\n";
2919 OS << " ErrorInfo = " << (MaxNumOperands+1) << ";\n";
2920 OS << " return Match_InvalidOperand;\n";
2923 // Emit code to get the available features.
2924 OS << " // Get the current feature set.\n";
2925 OS << " unsigned AvailableFeatures = getAvailableFeatures();\n\n";
2927 OS << " // Get the instruction mnemonic, which is the first token.\n";
2928 OS << " StringRef Mnemonic = ((" << Target.getName()
2929 << "Operand*)Operands[0])->getToken();\n\n";
2931 if (HasMnemonicAliases) {
2932 OS << " // Process all MnemonicAliases to remap the mnemonic.\n";
2933 OS << " applyMnemonicAliases(Mnemonic, AvailableFeatures, VariantID);\n\n";
2936 // Emit code to compute the class list for this operand vector.
2937 OS << " // Some state to try to produce better error messages.\n";
2938 OS << " bool HadMatchOtherThanFeatures = false;\n";
2939 OS << " bool HadMatchOtherThanPredicate = false;\n";
2940 OS << " unsigned RetCode = Match_InvalidOperand;\n";
2941 OS << " unsigned MissingFeatures = ~0U;\n";
2942 OS << " // Set ErrorInfo to the operand that mismatches if it is\n";
2943 OS << " // wrong for all instances of the instruction.\n";
2944 OS << " ErrorInfo = ~0U;\n";
2946 // Emit code to search the table.
2947 OS << " // Find the appropriate table for this asm variant.\n";
2948 OS << " const MatchEntry *Start, *End;\n";
2949 OS << " switch (VariantID) {\n";
2950 OS << " default: // unreachable\n";
2951 for (unsigned VC = 0; VC != VariantCount; ++VC) {
2952 Record *AsmVariant = Target.getAsmParserVariant(VC);
2953 std::string CommentDelimiter =
2954 AsmVariant->getValueAsString("CommentDelimiter");
2955 std::string RegisterPrefix = AsmVariant->getValueAsString("RegisterPrefix");
2956 int AsmVariantNo = AsmVariant->getValueAsInt("Variant");
2957 OS << " case " << AsmVariantNo << ": Start = MatchTable" << VC
2958 << "; End = array_endof(MatchTable" << VC << "); break;\n";
2961 OS << " // Search the table.\n";
2962 OS << " std::pair<const MatchEntry*, const MatchEntry*> MnemonicRange =\n";
2963 OS << " std::equal_range(Start, End, Mnemonic, LessOpcode());\n\n";
2965 OS << " // Return a more specific error code if no mnemonics match.\n";
2966 OS << " if (MnemonicRange.first == MnemonicRange.second)\n";
2967 OS << " return Match_MnemonicFail;\n\n";
2969 OS << " for (const MatchEntry *it = MnemonicRange.first, "
2970 << "*ie = MnemonicRange.second;\n";
2971 OS << " it != ie; ++it) {\n";
2973 OS << " // equal_range guarantees that instruction mnemonic matches.\n";
2974 OS << " assert(Mnemonic == it->getMnemonic());\n";
2976 // Emit check that the subclasses match.
2977 OS << " bool OperandsValid = true;\n";
2978 OS << " for (unsigned i = 0; i != " << MaxNumOperands << "; ++i) {\n";
2979 OS << " if (i + 1 >= Operands.size()) {\n";
2980 OS << " OperandsValid = (it->Classes[i] == " <<"InvalidMatchClass);\n";
2981 OS << " if (!OperandsValid) ErrorInfo = i + 1;\n";
2984 OS << " unsigned Diag = validateOperandClass(Operands[i+1],\n";
2986 OS << "(MatchClassKind)it->Classes[i]);\n";
2987 OS << " if (Diag == Match_Success)\n";
2988 OS << " continue;\n";
2989 OS << " // If the generic handler indicates an invalid operand\n";
2990 OS << " // failure, check for a special case.\n";
2991 OS << " if (Diag == Match_InvalidOperand) {\n";
2992 OS << " Diag = validateTargetOperandClass(Operands[i+1],\n";
2994 OS << "(MatchClassKind)it->Classes[i]);\n";
2995 OS << " if (Diag == Match_Success)\n";
2996 OS << " continue;\n";
2998 OS << " // If this operand is broken for all of the instances of this\n";
2999 OS << " // mnemonic, keep track of it so we can report loc info.\n";
3000 OS << " // If we already had a match that only failed due to a\n";
3001 OS << " // target predicate, that diagnostic is preferred.\n";
3002 OS << " if (!HadMatchOtherThanPredicate &&\n";
3003 OS << " (it == MnemonicRange.first || ErrorInfo <= i+1)) {\n";
3004 OS << " ErrorInfo = i+1;\n";
3005 OS << " // InvalidOperand is the default. Prefer specificity.\n";
3006 OS << " if (Diag != Match_InvalidOperand)\n";
3007 OS << " RetCode = Diag;\n";
3009 OS << " // Otherwise, just reject this instance of the mnemonic.\n";
3010 OS << " OperandsValid = false;\n";
3014 OS << " if (!OperandsValid) continue;\n";
3016 // Emit check that the required features are available.
3017 OS << " if ((AvailableFeatures & it->RequiredFeatures) "
3018 << "!= it->RequiredFeatures) {\n";
3019 OS << " HadMatchOtherThanFeatures = true;\n";
3020 OS << " unsigned NewMissingFeatures = it->RequiredFeatures & "
3021 "~AvailableFeatures;\n";
3022 OS << " if (CountPopulation_32(NewMissingFeatures) <=\n"
3023 " CountPopulation_32(MissingFeatures))\n";
3024 OS << " MissingFeatures = NewMissingFeatures;\n";
3025 OS << " continue;\n";
3028 OS << " if (matchingInlineAsm) {\n";
3029 OS << " Inst.setOpcode(it->Opcode);\n";
3030 OS << " convertToMapAndConstraints(it->ConvertFn, Operands);\n";
3031 OS << " return Match_Success;\n";
3033 OS << " // We have selected a definite instruction, convert the parsed\n"
3034 << " // operands into the appropriate MCInst.\n";
3035 OS << " convertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands);\n";
3038 // Verify the instruction with the target-specific match predicate function.
3039 OS << " // We have a potential match. Check the target predicate to\n"
3040 << " // handle any context sensitive constraints.\n"
3041 << " unsigned MatchResult;\n"
3042 << " if ((MatchResult = checkTargetMatchPredicate(Inst)) !="
3043 << " Match_Success) {\n"
3044 << " Inst.clear();\n"
3045 << " RetCode = MatchResult;\n"
3046 << " HadMatchOtherThanPredicate = true;\n"
3050 // Call the post-processing function, if used.
3051 std::string InsnCleanupFn =
3052 AsmParser->getValueAsString("AsmParserInstCleanup");
3053 if (!InsnCleanupFn.empty())
3054 OS << " " << InsnCleanupFn << "(Inst);\n";
3056 if (HasDeprecation) {
3057 OS << " std::string Info;\n";
3058 OS << " if (MII.get(Inst.getOpcode()).getDeprecatedInfo(Inst, STI, Info)) {\n";
3059 OS << " SMLoc Loc = ((" << Target.getName() << "Operand*)Operands[0])->getStartLoc();\n";
3060 OS << " Parser.Warning(Loc, Info, None);\n";
3064 OS << " return Match_Success;\n";
3067 OS << " // Okay, we had no match. Try to return a useful error code.\n";
3068 OS << " if (HadMatchOtherThanPredicate || !HadMatchOtherThanFeatures)\n";
3069 OS << " return RetCode;\n\n";
3070 OS << " // Missing feature matches return which features were missing\n";
3071 OS << " ErrorInfo = MissingFeatures;\n";
3072 OS << " return Match_MissingFeature;\n";
3075 if (Info.OperandMatchInfo.size())
3076 emitCustomOperandParsing(OS, Target, Info, ClassName, StringTable,
3079 OS << "#endif // GET_MATCHER_IMPLEMENTATION\n\n";
3084 void EmitAsmMatcher(RecordKeeper &RK, raw_ostream &OS) {
3085 emitSourceFileHeader("Assembly Matcher Source Fragment", OS);
3086 AsmMatcherEmitter(RK).run(OS);
3089 } // End llvm namespace