1 //===- AsmMatcherEmitter.cpp - Generate an assembly matcher ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend emits a target specifier matcher for converting parsed
11 // assembly operands in the MCInst structures. It also emits a matcher for
12 // custom operand parsing.
14 // Converting assembly operands into MCInst structures
15 // ---------------------------------------------------
17 // The input to the target specific matcher is a list of literal tokens and
18 // operands. The target specific parser should generally eliminate any syntax
19 // which is not relevant for matching; for example, comma tokens should have
20 // already been consumed and eliminated by the parser. Most instructions will
21 // end up with a single literal token (the instruction name) and some number of
24 // Some example inputs, for X86:
25 // 'addl' (immediate ...) (register ...)
26 // 'add' (immediate ...) (memory ...)
29 // The assembly matcher is responsible for converting this input into a precise
30 // machine instruction (i.e., an instruction with a well defined encoding). This
31 // mapping has several properties which complicate matching:
33 // - It may be ambiguous; many architectures can legally encode particular
34 // variants of an instruction in different ways (for example, using a smaller
35 // encoding for small immediates). Such ambiguities should never be
36 // arbitrarily resolved by the assembler, the assembler is always responsible
37 // for choosing the "best" available instruction.
39 // - It may depend on the subtarget or the assembler context. Instructions
40 // which are invalid for the current mode, but otherwise unambiguous (e.g.,
41 // an SSE instruction in a file being assembled for i486) should be accepted
42 // and rejected by the assembler front end. However, if the proper encoding
43 // for an instruction is dependent on the assembler context then the matcher
44 // is responsible for selecting the correct machine instruction for the
47 // The core matching algorithm attempts to exploit the regularity in most
48 // instruction sets to quickly determine the set of possibly matching
49 // instructions, and the simplify the generated code. Additionally, this helps
50 // to ensure that the ambiguities are intentionally resolved by the user.
52 // The matching is divided into two distinct phases:
54 // 1. Classification: Each operand is mapped to the unique set which (a)
55 // contains it, and (b) is the largest such subset for which a single
56 // instruction could match all members.
58 // For register classes, we can generate these subgroups automatically. For
59 // arbitrary operands, we expect the user to define the classes and their
60 // relations to one another (for example, 8-bit signed immediates as a
61 // subset of 32-bit immediates).
63 // By partitioning the operands in this way, we guarantee that for any
64 // tuple of classes, any single instruction must match either all or none
65 // of the sets of operands which could classify to that tuple.
67 // In addition, the subset relation amongst classes induces a partial order
68 // on such tuples, which we use to resolve ambiguities.
70 // 2. The input can now be treated as a tuple of classes (static tokens are
71 // simple singleton sets). Each such tuple should generally map to a single
72 // instruction (we currently ignore cases where this isn't true, whee!!!),
73 // which we can emit a simple matcher for.
75 // Custom Operand Parsing
76 // ----------------------
78 // Some targets need a custom way to parse operands, some specific instructions
79 // can contain arguments that can represent processor flags and other kinds of
80 // identifiers that need to be mapped to specific values in the final encoded
81 // instructions. The target specific custom operand parsing works in the
84 // 1. A operand match table is built, each entry contains a mnemonic, an
85 // operand class, a mask for all operand positions for that same
86 // class/mnemonic and target features to be checked while trying to match.
88 // 2. The operand matcher will try every possible entry with the same
89 // mnemonic and will check if the target feature for this mnemonic also
90 // matches. After that, if the operand to be matched has its index
91 // present in the mask, a successful match occurs. Otherwise, fallback
92 // to the regular operand parsing.
94 // 3. For a match success, each operand class that has a 'ParserMethod'
95 // becomes part of a switch from where the custom method is called.
97 //===----------------------------------------------------------------------===//
99 #include "CodeGenTarget.h"
100 #include "llvm/ADT/PointerUnion.h"
101 #include "llvm/ADT/STLExtras.h"
102 #include "llvm/ADT/SmallPtrSet.h"
103 #include "llvm/ADT/SmallVector.h"
104 #include "llvm/ADT/StringExtras.h"
105 #include "llvm/Support/CommandLine.h"
106 #include "llvm/Support/Debug.h"
107 #include "llvm/Support/ErrorHandling.h"
108 #include "llvm/TableGen/Error.h"
109 #include "llvm/TableGen/Record.h"
110 #include "llvm/TableGen/StringMatcher.h"
111 #include "llvm/TableGen/StringToOffsetTable.h"
112 #include "llvm/TableGen/TableGenBackend.h"
118 #include <forward_list>
119 using namespace llvm;
121 #define DEBUG_TYPE "asm-matcher-emitter"
123 static cl::opt<std::string>
124 MatchPrefix("match-prefix", cl::init(""),
125 cl::desc("Only match instructions with the given prefix"));
128 class AsmMatcherInfo;
129 struct SubtargetFeatureInfo;
131 // Register sets are used as keys in some second-order sets TableGen creates
132 // when generating its data structures. This means that the order of two
133 // RegisterSets can be seen in the outputted AsmMatcher tables occasionally, and
134 // can even affect compiler output (at least seen in diagnostics produced when
135 // all matches fail). So we use a type that sorts them consistently.
136 typedef std::set<Record*, LessRecordByID> RegisterSet;
138 class AsmMatcherEmitter {
139 RecordKeeper &Records;
141 AsmMatcherEmitter(RecordKeeper &R) : Records(R) {}
143 void run(raw_ostream &o);
146 /// ClassInfo - Helper class for storing the information about a particular
147 /// class of operands which can be matched.
150 /// Invalid kind, for use as a sentinel value.
153 /// The class for a particular token.
156 /// The (first) register class, subsequent register classes are
157 /// RegisterClass0+1, and so on.
160 /// The (first) user defined class, subsequent user defined classes are
161 /// UserClass0+1, and so on.
165 /// Kind - The class kind, which is either a predefined kind, or (UserClass0 +
166 /// N) for the Nth user defined class.
169 /// SuperClasses - The super classes of this class. Note that for simplicities
170 /// sake user operands only record their immediate super class, while register
171 /// operands include all superclasses.
172 std::vector<ClassInfo*> SuperClasses;
174 /// Name - The full class name, suitable for use in an enum.
177 /// ClassName - The unadorned generic name for this class (e.g., Token).
178 std::string ClassName;
180 /// ValueName - The name of the value this class represents; for a token this
181 /// is the literal token string, for an operand it is the TableGen class (or
182 /// empty if this is a derived class).
183 std::string ValueName;
185 /// PredicateMethod - The name of the operand method to test whether the
186 /// operand matches this class; this is not valid for Token or register kinds.
187 std::string PredicateMethod;
189 /// RenderMethod - The name of the operand method to add this operand to an
190 /// MCInst; this is not valid for Token or register kinds.
191 std::string RenderMethod;
193 /// ParserMethod - The name of the operand method to do a target specific
194 /// parsing on the operand.
195 std::string ParserMethod;
197 /// For register classes: the records for all the registers in this class.
198 RegisterSet Registers;
200 /// For custom match classes: the diagnostic kind for when the predicate fails.
201 std::string DiagnosticType;
203 /// isRegisterClass() - Check if this is a register class.
204 bool isRegisterClass() const {
205 return Kind >= RegisterClass0 && Kind < UserClass0;
208 /// isUserClass() - Check if this is a user defined class.
209 bool isUserClass() const {
210 return Kind >= UserClass0;
213 /// isRelatedTo - Check whether this class is "related" to \p RHS. Classes
214 /// are related if they are in the same class hierarchy.
215 bool isRelatedTo(const ClassInfo &RHS) const {
216 // Tokens are only related to tokens.
217 if (Kind == Token || RHS.Kind == Token)
218 return Kind == Token && RHS.Kind == Token;
220 // Registers classes are only related to registers classes, and only if
221 // their intersection is non-empty.
222 if (isRegisterClass() || RHS.isRegisterClass()) {
223 if (!isRegisterClass() || !RHS.isRegisterClass())
227 std::insert_iterator<RegisterSet> II(Tmp, Tmp.begin());
228 std::set_intersection(Registers.begin(), Registers.end(),
229 RHS.Registers.begin(), RHS.Registers.end(),
230 II, LessRecordByID());
235 // Otherwise we have two users operands; they are related if they are in the
236 // same class hierarchy.
238 // FIXME: This is an oversimplification, they should only be related if they
239 // intersect, however we don't have that information.
240 assert(isUserClass() && RHS.isUserClass() && "Unexpected class!");
241 const ClassInfo *Root = this;
242 while (!Root->SuperClasses.empty())
243 Root = Root->SuperClasses.front();
245 const ClassInfo *RHSRoot = &RHS;
246 while (!RHSRoot->SuperClasses.empty())
247 RHSRoot = RHSRoot->SuperClasses.front();
249 return Root == RHSRoot;
252 /// isSubsetOf - Test whether this class is a subset of \p RHS.
253 bool isSubsetOf(const ClassInfo &RHS) const {
254 // This is a subset of RHS if it is the same class...
258 // ... or if any of its super classes are a subset of RHS.
259 for (const ClassInfo *CI : SuperClasses)
260 if (CI->isSubsetOf(RHS))
266 /// operator< - Compare two classes.
267 // FIXME: This ordering seems to be broken. For example:
268 // u64 < i64, i64 < s8, s8 < u64, forming a cycle
269 // u64 is a subset of i64
270 // i64 and s8 are not subsets of each other, so are ordered by name
271 // s8 and u64 are not subsets of each other, so are ordered by name
272 bool operator<(const ClassInfo &RHS) const {
276 // Unrelated classes can be ordered by kind.
277 if (!isRelatedTo(RHS))
278 return Kind < RHS.Kind;
282 llvm_unreachable("Invalid kind!");
285 // This class precedes the RHS if it is a proper subset of the RHS.
288 if (RHS.isSubsetOf(*this))
291 // Otherwise, order by name to ensure we have a total ordering.
292 return ValueName < RHS.ValueName;
297 /// MatchableInfo - Helper class for storing the necessary information for an
298 /// instruction or alias which is capable of being matched.
299 struct MatchableInfo {
301 /// Token - This is the token that the operand came from.
304 /// The unique class instance this operand should match.
307 /// The operand name this is, if anything.
310 /// The suboperand index within SrcOpName, or -1 for the entire operand.
313 /// Whether the token is "isolated", i.e., it is preceded and followed
315 bool IsIsolatedToken;
317 /// Register record if this token is singleton register.
318 Record *SingletonReg;
320 explicit AsmOperand(bool IsIsolatedToken, StringRef T)
321 : Token(T), Class(nullptr), SubOpIdx(-1),
322 IsIsolatedToken(IsIsolatedToken), SingletonReg(nullptr) {}
325 /// ResOperand - This represents a single operand in the result instruction
326 /// generated by the match. In cases (like addressing modes) where a single
327 /// assembler operand expands to multiple MCOperands, this represents the
328 /// single assembler operand, not the MCOperand.
331 /// RenderAsmOperand - This represents an operand result that is
332 /// generated by calling the render method on the assembly operand. The
333 /// corresponding AsmOperand is specified by AsmOperandNum.
336 /// TiedOperand - This represents a result operand that is a duplicate of
337 /// a previous result operand.
340 /// ImmOperand - This represents an immediate value that is dumped into
344 /// RegOperand - This represents a fixed register that is dumped in.
349 /// This is the operand # in the AsmOperands list that this should be
351 unsigned AsmOperandNum;
353 /// TiedOperandNum - This is the (earlier) result operand that should be
355 unsigned TiedOperandNum;
357 /// ImmVal - This is the immediate value added to the instruction.
360 /// Register - This is the register record.
364 /// MINumOperands - The number of MCInst operands populated by this
366 unsigned MINumOperands;
368 static ResOperand getRenderedOp(unsigned AsmOpNum, unsigned NumOperands) {
370 X.Kind = RenderAsmOperand;
371 X.AsmOperandNum = AsmOpNum;
372 X.MINumOperands = NumOperands;
376 static ResOperand getTiedOp(unsigned TiedOperandNum) {
378 X.Kind = TiedOperand;
379 X.TiedOperandNum = TiedOperandNum;
384 static ResOperand getImmOp(int64_t Val) {
392 static ResOperand getRegOp(Record *Reg) {
401 /// AsmVariantID - Target's assembly syntax variant no.
404 /// AsmString - The assembly string for this instruction (with variants
405 /// removed), e.g. "movsx $src, $dst".
406 std::string AsmString;
408 /// TheDef - This is the definition of the instruction or InstAlias that this
409 /// matchable came from.
410 Record *const TheDef;
412 /// DefRec - This is the definition that it came from.
413 PointerUnion<const CodeGenInstruction*, const CodeGenInstAlias*> DefRec;
415 const CodeGenInstruction *getResultInst() const {
416 if (DefRec.is<const CodeGenInstruction*>())
417 return DefRec.get<const CodeGenInstruction*>();
418 return DefRec.get<const CodeGenInstAlias*>()->ResultInst;
421 /// ResOperands - This is the operand list that should be built for the result
423 SmallVector<ResOperand, 8> ResOperands;
425 /// Mnemonic - This is the first token of the matched instruction, its
429 /// AsmOperands - The textual operands that this instruction matches,
430 /// annotated with a class and where in the OperandList they were defined.
431 /// This directly corresponds to the tokenized AsmString after the mnemonic is
433 SmallVector<AsmOperand, 8> AsmOperands;
435 /// Predicates - The required subtarget features to match this instruction.
436 SmallVector<const SubtargetFeatureInfo *, 4> RequiredFeatures;
438 /// ConversionFnKind - The enum value which is passed to the generated
439 /// convertToMCInst to convert parsed operands into an MCInst for this
441 std::string ConversionFnKind;
443 /// If this instruction is deprecated in some form.
446 /// If this is an alias, this is use to determine whether or not to using
447 /// the conversion function defined by the instruction's AsmMatchConverter
448 /// or to use the function generated by the alias.
449 bool UseInstAsmMatchConverter;
451 MatchableInfo(const CodeGenInstruction &CGI)
452 : AsmVariantID(0), AsmString(CGI.AsmString), TheDef(CGI.TheDef), DefRec(&CGI),
453 UseInstAsmMatchConverter(true) {
456 MatchableInfo(std::unique_ptr<const CodeGenInstAlias> Alias)
457 : AsmVariantID(0), AsmString(Alias->AsmString), TheDef(Alias->TheDef),
458 DefRec(Alias.release()),
459 UseInstAsmMatchConverter(
460 TheDef->getValueAsBit("UseInstAsmMatchConverter")) {
463 // Could remove this and the dtor if PointerUnion supported unique_ptr
464 // elements with a dynamic failure/assertion (like the one below) in the case
465 // where it was copied while being in an owning state.
466 MatchableInfo(const MatchableInfo &RHS)
467 : AsmVariantID(RHS.AsmVariantID), AsmString(RHS.AsmString),
468 TheDef(RHS.TheDef), DefRec(RHS.DefRec), ResOperands(RHS.ResOperands),
469 Mnemonic(RHS.Mnemonic), AsmOperands(RHS.AsmOperands),
470 RequiredFeatures(RHS.RequiredFeatures),
471 ConversionFnKind(RHS.ConversionFnKind),
472 HasDeprecation(RHS.HasDeprecation),
473 UseInstAsmMatchConverter(RHS.UseInstAsmMatchConverter) {
474 assert(!DefRec.is<const CodeGenInstAlias *>());
478 delete DefRec.dyn_cast<const CodeGenInstAlias*>();
481 // Two-operand aliases clone from the main matchable, but mark the second
482 // operand as a tied operand of the first for purposes of the assembler.
483 void formTwoOperandAlias(StringRef Constraint);
485 void initialize(const AsmMatcherInfo &Info,
486 SmallPtrSetImpl<Record*> &SingletonRegisters,
487 int AsmVariantNo, StringRef RegisterPrefix);
489 /// validate - Return true if this matchable is a valid thing to match against
490 /// and perform a bunch of validity checking.
491 bool validate(StringRef CommentDelimiter, bool Hack) const;
493 /// findAsmOperand - Find the AsmOperand with the specified name and
494 /// suboperand index.
495 int findAsmOperand(StringRef N, int SubOpIdx) const {
496 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i)
497 if (N == AsmOperands[i].SrcOpName &&
498 SubOpIdx == AsmOperands[i].SubOpIdx)
503 /// findAsmOperandNamed - Find the first AsmOperand with the specified name.
504 /// This does not check the suboperand index.
505 int findAsmOperandNamed(StringRef N) const {
506 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i)
507 if (N == AsmOperands[i].SrcOpName)
512 void buildInstructionResultOperands();
513 void buildAliasResultOperands();
515 /// operator< - Compare two matchables.
516 bool operator<(const MatchableInfo &RHS) const {
517 // The primary comparator is the instruction mnemonic.
518 if (Mnemonic != RHS.Mnemonic)
519 return Mnemonic < RHS.Mnemonic;
521 if (AsmOperands.size() != RHS.AsmOperands.size())
522 return AsmOperands.size() < RHS.AsmOperands.size();
524 // Compare lexicographically by operand. The matcher validates that other
525 // orderings wouldn't be ambiguous using \see couldMatchAmbiguouslyWith().
526 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
527 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class)
529 if (*RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
533 // Give matches that require more features higher precedence. This is useful
534 // because we cannot define AssemblerPredicates with the negation of
535 // processor features. For example, ARM v6 "nop" may be either a HINT or
536 // MOV. With v6, we want to match HINT. The assembler has no way to
537 // predicate MOV under "NoV6", but HINT will always match first because it
538 // requires V6 while MOV does not.
539 if (RequiredFeatures.size() != RHS.RequiredFeatures.size())
540 return RequiredFeatures.size() > RHS.RequiredFeatures.size();
545 /// couldMatchAmbiguouslyWith - Check whether this matchable could
546 /// ambiguously match the same set of operands as \p RHS (without being a
547 /// strictly superior match).
548 bool couldMatchAmbiguouslyWith(const MatchableInfo &RHS) const {
549 // The primary comparator is the instruction mnemonic.
550 if (Mnemonic != RHS.Mnemonic)
553 // The number of operands is unambiguous.
554 if (AsmOperands.size() != RHS.AsmOperands.size())
557 // Otherwise, make sure the ordering of the two instructions is unambiguous
558 // by checking that either (a) a token or operand kind discriminates them,
559 // or (b) the ordering among equivalent kinds is consistent.
561 // Tokens and operand kinds are unambiguous (assuming a correct target
563 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i)
564 if (AsmOperands[i].Class->Kind != RHS.AsmOperands[i].Class->Kind ||
565 AsmOperands[i].Class->Kind == ClassInfo::Token)
566 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class ||
567 *RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
570 // Otherwise, this operand could commute if all operands are equivalent, or
571 // there is a pair of operands that compare less than and a pair that
572 // compare greater than.
573 bool HasLT = false, HasGT = false;
574 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
575 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class)
577 if (*RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
581 return !(HasLT ^ HasGT);
587 void tokenizeAsmString(const AsmMatcherInfo &Info);
588 void addAsmOperand(size_t Start, size_t End);
591 /// SubtargetFeatureInfo - Helper class for storing information on a subtarget
592 /// feature which participates in instruction matching.
593 struct SubtargetFeatureInfo {
594 /// \brief The predicate record for this feature.
597 /// \brief An unique index assigned to represent this feature.
600 SubtargetFeatureInfo(Record *D, uint64_t Idx) : TheDef(D), Index(Idx) {}
602 /// \brief The name of the enumerated constant identifying this feature.
603 std::string getEnumName() const {
604 return "Feature_" + TheDef->getName();
608 errs() << getEnumName() << " " << Index << "\n";
613 struct OperandMatchEntry {
614 unsigned OperandMask;
615 const MatchableInfo* MI;
618 static OperandMatchEntry create(const MatchableInfo *mi, ClassInfo *ci,
621 X.OperandMask = opMask;
629 class AsmMatcherInfo {
632 RecordKeeper &Records;
634 /// The tablegen AsmParser record.
637 /// Target - The target information.
638 CodeGenTarget &Target;
640 /// The classes which are needed for matching.
641 std::forward_list<ClassInfo> Classes;
643 /// The information on the matchables to match.
644 std::vector<std::unique_ptr<MatchableInfo>> Matchables;
646 /// Info for custom matching operands by user defined methods.
647 std::vector<OperandMatchEntry> OperandMatchInfo;
649 /// Map of Register records to their class information.
650 typedef std::map<Record*, ClassInfo*, LessRecordByID> RegisterClassesTy;
651 RegisterClassesTy RegisterClasses;
653 /// Map of Predicate records to their subtarget information.
654 std::map<Record *, SubtargetFeatureInfo, LessRecordByID> SubtargetFeatures;
656 /// Map of AsmOperandClass records to their class information.
657 std::map<Record*, ClassInfo*> AsmOperandClasses;
660 /// Map of token to class information which has already been constructed.
661 std::map<std::string, ClassInfo*> TokenClasses;
663 /// Map of RegisterClass records to their class information.
664 std::map<Record*, ClassInfo*> RegisterClassClasses;
667 /// getTokenClass - Lookup or create the class for the given token.
668 ClassInfo *getTokenClass(StringRef Token);
670 /// getOperandClass - Lookup or create the class for the given operand.
671 ClassInfo *getOperandClass(const CGIOperandList::OperandInfo &OI,
673 ClassInfo *getOperandClass(Record *Rec, int SubOpIdx);
675 /// buildRegisterClasses - Build the ClassInfo* instances for register
677 void buildRegisterClasses(SmallPtrSetImpl<Record*> &SingletonRegisters);
679 /// buildOperandClasses - Build the ClassInfo* instances for user defined
681 void buildOperandClasses();
683 void buildInstructionOperandReference(MatchableInfo *II, StringRef OpName,
685 void buildAliasOperandReference(MatchableInfo *II, StringRef OpName,
686 MatchableInfo::AsmOperand &Op);
689 AsmMatcherInfo(Record *AsmParser,
690 CodeGenTarget &Target,
691 RecordKeeper &Records);
693 /// buildInfo - Construct the various tables used during matching.
696 /// buildOperandMatchInfo - Build the necessary information to handle user
697 /// defined operand parsing methods.
698 void buildOperandMatchInfo();
700 /// getSubtargetFeature - Lookup or create the subtarget feature info for the
702 const SubtargetFeatureInfo *getSubtargetFeature(Record *Def) const {
703 assert(Def->isSubClassOf("Predicate") && "Invalid predicate type!");
704 const auto &I = SubtargetFeatures.find(Def);
705 return I == SubtargetFeatures.end() ? nullptr : &I->second;
708 RecordKeeper &getRecords() const {
713 } // End anonymous namespace
715 void MatchableInfo::dump() const {
716 errs() << TheDef->getName() << " -- " << "flattened:\"" << AsmString <<"\"\n";
718 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
719 const AsmOperand &Op = AsmOperands[i];
720 errs() << " op[" << i << "] = " << Op.Class->ClassName << " - ";
721 errs() << '\"' << Op.Token << "\"\n";
725 static std::pair<StringRef, StringRef>
726 parseTwoOperandConstraint(StringRef S, ArrayRef<SMLoc> Loc) {
727 // Split via the '='.
728 std::pair<StringRef, StringRef> Ops = S.split('=');
729 if (Ops.second == "")
730 PrintFatalError(Loc, "missing '=' in two-operand alias constraint");
731 // Trim whitespace and the leading '$' on the operand names.
732 size_t start = Ops.first.find_first_of('$');
733 if (start == std::string::npos)
734 PrintFatalError(Loc, "expected '$' prefix on asm operand name");
735 Ops.first = Ops.first.slice(start + 1, std::string::npos);
736 size_t end = Ops.first.find_last_of(" \t");
737 Ops.first = Ops.first.slice(0, end);
738 // Now the second operand.
739 start = Ops.second.find_first_of('$');
740 if (start == std::string::npos)
741 PrintFatalError(Loc, "expected '$' prefix on asm operand name");
742 Ops.second = Ops.second.slice(start + 1, std::string::npos);
743 end = Ops.second.find_last_of(" \t");
744 Ops.first = Ops.first.slice(0, end);
748 void MatchableInfo::formTwoOperandAlias(StringRef Constraint) {
749 // Figure out which operands are aliased and mark them as tied.
750 std::pair<StringRef, StringRef> Ops =
751 parseTwoOperandConstraint(Constraint, TheDef->getLoc());
753 // Find the AsmOperands that refer to the operands we're aliasing.
754 int SrcAsmOperand = findAsmOperandNamed(Ops.first);
755 int DstAsmOperand = findAsmOperandNamed(Ops.second);
756 if (SrcAsmOperand == -1)
757 PrintFatalError(TheDef->getLoc(),
758 "unknown source two-operand alias operand '" + Ops.first +
760 if (DstAsmOperand == -1)
761 PrintFatalError(TheDef->getLoc(),
762 "unknown destination two-operand alias operand '" +
765 // Find the ResOperand that refers to the operand we're aliasing away
766 // and update it to refer to the combined operand instead.
767 for (unsigned i = 0, e = ResOperands.size(); i != e; ++i) {
768 ResOperand &Op = ResOperands[i];
769 if (Op.Kind == ResOperand::RenderAsmOperand &&
770 Op.AsmOperandNum == (unsigned)SrcAsmOperand) {
771 Op.AsmOperandNum = DstAsmOperand;
775 // Remove the AsmOperand for the alias operand.
776 AsmOperands.erase(AsmOperands.begin() + SrcAsmOperand);
777 // Adjust the ResOperand references to any AsmOperands that followed
778 // the one we just deleted.
779 for (unsigned i = 0, e = ResOperands.size(); i != e; ++i) {
780 ResOperand &Op = ResOperands[i];
783 // Nothing to do for operands that don't reference AsmOperands.
785 case ResOperand::RenderAsmOperand:
786 if (Op.AsmOperandNum > (unsigned)SrcAsmOperand)
789 case ResOperand::TiedOperand:
790 if (Op.TiedOperandNum > (unsigned)SrcAsmOperand)
797 /// extractSingletonRegisterForAsmOperand - Extract singleton register,
798 /// if present, from specified token.
800 extractSingletonRegisterForAsmOperand(MatchableInfo::AsmOperand &Op,
801 const AsmMatcherInfo &Info,
802 StringRef RegisterPrefix) {
803 StringRef Tok = Op.Token;
805 // If this token is not an isolated token, i.e., it isn't separated from
806 // other tokens (e.g. with whitespace), don't interpret it as a register name.
807 if (!Op.IsIsolatedToken)
810 if (RegisterPrefix.empty()) {
811 std::string LoweredTok = Tok.lower();
812 if (const CodeGenRegister *Reg = Info.Target.getRegisterByName(LoweredTok))
813 Op.SingletonReg = Reg->TheDef;
817 if (!Tok.startswith(RegisterPrefix))
820 StringRef RegName = Tok.substr(RegisterPrefix.size());
821 if (const CodeGenRegister *Reg = Info.Target.getRegisterByName(RegName))
822 Op.SingletonReg = Reg->TheDef;
824 // If there is no register prefix (i.e. "%" in "%eax"), then this may
825 // be some random non-register token, just ignore it.
829 void MatchableInfo::initialize(const AsmMatcherInfo &Info,
830 SmallPtrSetImpl<Record*> &SingletonRegisters,
831 int AsmVariantNo, StringRef RegisterPrefix) {
832 AsmVariantID = AsmVariantNo;
834 CodeGenInstruction::FlattenAsmStringVariants(AsmString, AsmVariantNo);
836 tokenizeAsmString(Info);
838 // Compute the require features.
839 for (Record *Predicate : TheDef->getValueAsListOfDefs("Predicates"))
840 if (const SubtargetFeatureInfo *Feature =
841 Info.getSubtargetFeature(Predicate))
842 RequiredFeatures.push_back(Feature);
844 // Collect singleton registers, if used.
845 for (MatchableInfo::AsmOperand &Op : AsmOperands) {
846 extractSingletonRegisterForAsmOperand(Op, Info, RegisterPrefix);
847 if (Record *Reg = Op.SingletonReg)
848 SingletonRegisters.insert(Reg);
851 const RecordVal *DepMask = TheDef->getValue("DeprecatedFeatureMask");
853 DepMask = TheDef->getValue("ComplexDeprecationPredicate");
856 DepMask ? !DepMask->getValue()->getAsUnquotedString().empty() : false;
859 /// Append an AsmOperand for the given substring of AsmString.
860 void MatchableInfo::addAsmOperand(size_t Start, size_t End) {
861 StringRef String = AsmString;
862 StringRef Separators = "[]*! \t,";
863 // Look for separators before and after to figure out is this token is
864 // isolated. Accept '$$' as that's how we escape '$'.
865 bool IsIsolatedToken =
866 (!Start || Separators.find(String[Start - 1]) != StringRef::npos ||
867 String.substr(Start - 1, 2) == "$$") &&
868 (End >= String.size() || Separators.find(String[End]) != StringRef::npos);
869 AsmOperands.push_back(AsmOperand(IsIsolatedToken, String.slice(Start, End)));
872 /// tokenizeAsmString - Tokenize a simplified assembly string.
873 void MatchableInfo::tokenizeAsmString(const AsmMatcherInfo &Info) {
874 StringRef String = AsmString;
877 for (size_t i = 0, e = String.size(); i != e; ++i) {
887 addAsmOperand(Prev, i);
890 if (!isspace(String[i]) && String[i] != ',')
891 addAsmOperand(i, i + 1);
897 addAsmOperand(Prev, i);
901 assert(i != String.size() && "Invalid quoted character");
902 addAsmOperand(i, i + 1);
908 addAsmOperand(Prev, i);
912 // If this isn't "${", start new identifier looking like "$xxx"
913 if (i + 1 == String.size() || String[i + 1] != '{') {
918 // If this is "${" find the next "}" and make an identifier like "${xxx}"
919 size_t EndPos = String.find('}', i);
920 assert(EndPos != StringRef::npos &&
921 "Missing brace in operand reference!");
922 addAsmOperand(i, EndPos+1);
929 if (!Info.AsmParser->getValueAsBit("MnemonicContainsDot")) {
931 addAsmOperand(Prev, i);
941 if (InTok && Prev != String.size())
942 addAsmOperand(Prev, StringRef::npos);
944 // The first token of the instruction is the mnemonic, which must be a
945 // simple string, not a $foo variable or a singleton register.
946 if (AsmOperands.empty())
947 PrintFatalError(TheDef->getLoc(),
948 "Instruction '" + TheDef->getName() + "' has no tokens");
949 Mnemonic = AsmOperands[0].Token;
950 if (Mnemonic.empty())
951 PrintFatalError(TheDef->getLoc(),
952 "Missing instruction mnemonic");
953 // FIXME : Check and raise an error if it is a register.
954 if (Mnemonic[0] == '$')
955 PrintFatalError(TheDef->getLoc(),
956 "Invalid instruction mnemonic '" + Mnemonic + "'!");
958 // Remove the first operand, it is tracked in the mnemonic field.
959 AsmOperands.erase(AsmOperands.begin());
962 bool MatchableInfo::validate(StringRef CommentDelimiter, bool Hack) const {
963 // Reject matchables with no .s string.
964 if (AsmString.empty())
965 PrintFatalError(TheDef->getLoc(), "instruction with empty asm string");
967 // Reject any matchables with a newline in them, they should be marked
968 // isCodeGenOnly if they are pseudo instructions.
969 if (AsmString.find('\n') != std::string::npos)
970 PrintFatalError(TheDef->getLoc(),
971 "multiline instruction is not valid for the asmparser, "
972 "mark it isCodeGenOnly");
974 // Remove comments from the asm string. We know that the asmstring only
976 if (!CommentDelimiter.empty() &&
977 StringRef(AsmString).find(CommentDelimiter) != StringRef::npos)
978 PrintFatalError(TheDef->getLoc(),
979 "asmstring for instruction has comment character in it, "
980 "mark it isCodeGenOnly");
982 // Reject matchables with operand modifiers, these aren't something we can
983 // handle, the target should be refactored to use operands instead of
986 // Also, check for instructions which reference the operand multiple times;
987 // this implies a constraint we would not honor.
988 std::set<std::string> OperandNames;
989 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
990 StringRef Tok = AsmOperands[i].Token;
991 if (Tok[0] == '$' && Tok.find(':') != StringRef::npos)
992 PrintFatalError(TheDef->getLoc(),
993 "matchable with operand modifier '" + Tok +
994 "' not supported by asm matcher. Mark isCodeGenOnly!");
996 // Verify that any operand is only mentioned once.
997 // We reject aliases and ignore instructions for now.
998 if (Tok[0] == '$' && !OperandNames.insert(Tok).second) {
1000 PrintFatalError(TheDef->getLoc(),
1001 "ERROR: matchable with tied operand '" + Tok +
1002 "' can never be matched!");
1003 // FIXME: Should reject these. The ARM backend hits this with $lane in a
1004 // bunch of instructions. It is unclear what the right answer is.
1006 errs() << "warning: '" << TheDef->getName() << "': "
1007 << "ignoring instruction with tied operand '"
1017 static std::string getEnumNameForToken(StringRef Str) {
1020 for (StringRef::iterator it = Str.begin(), ie = Str.end(); it != ie; ++it) {
1022 case '*': Res += "_STAR_"; break;
1023 case '%': Res += "_PCT_"; break;
1024 case ':': Res += "_COLON_"; break;
1025 case '!': Res += "_EXCLAIM_"; break;
1026 case '.': Res += "_DOT_"; break;
1027 case '<': Res += "_LT_"; break;
1028 case '>': Res += "_GT_"; break;
1029 case '-': Res += "_MINUS_"; break;
1031 if ((*it >= 'A' && *it <= 'Z') ||
1032 (*it >= 'a' && *it <= 'z') ||
1033 (*it >= '0' && *it <= '9'))
1036 Res += "_" + utostr((unsigned) *it) + "_";
1043 ClassInfo *AsmMatcherInfo::getTokenClass(StringRef Token) {
1044 ClassInfo *&Entry = TokenClasses[Token];
1047 Classes.emplace_front();
1048 Entry = &Classes.front();
1049 Entry->Kind = ClassInfo::Token;
1050 Entry->ClassName = "Token";
1051 Entry->Name = "MCK_" + getEnumNameForToken(Token);
1052 Entry->ValueName = Token;
1053 Entry->PredicateMethod = "<invalid>";
1054 Entry->RenderMethod = "<invalid>";
1055 Entry->ParserMethod = "";
1056 Entry->DiagnosticType = "";
1063 AsmMatcherInfo::getOperandClass(const CGIOperandList::OperandInfo &OI,
1065 Record *Rec = OI.Rec;
1067 Rec = cast<DefInit>(OI.MIOperandInfo->getArg(SubOpIdx))->getDef();
1068 return getOperandClass(Rec, SubOpIdx);
1072 AsmMatcherInfo::getOperandClass(Record *Rec, int SubOpIdx) {
1073 if (Rec->isSubClassOf("RegisterOperand")) {
1074 // RegisterOperand may have an associated ParserMatchClass. If it does,
1075 // use it, else just fall back to the underlying register class.
1076 const RecordVal *R = Rec->getValue("ParserMatchClass");
1077 if (!R || !R->getValue())
1078 PrintFatalError("Record `" + Rec->getName() +
1079 "' does not have a ParserMatchClass!\n");
1081 if (DefInit *DI= dyn_cast<DefInit>(R->getValue())) {
1082 Record *MatchClass = DI->getDef();
1083 if (ClassInfo *CI = AsmOperandClasses[MatchClass])
1087 // No custom match class. Just use the register class.
1088 Record *ClassRec = Rec->getValueAsDef("RegClass");
1090 PrintFatalError(Rec->getLoc(), "RegisterOperand `" + Rec->getName() +
1091 "' has no associated register class!\n");
1092 if (ClassInfo *CI = RegisterClassClasses[ClassRec])
1094 PrintFatalError(Rec->getLoc(), "register class has no class info!");
1098 if (Rec->isSubClassOf("RegisterClass")) {
1099 if (ClassInfo *CI = RegisterClassClasses[Rec])
1101 PrintFatalError(Rec->getLoc(), "register class has no class info!");
1104 if (!Rec->isSubClassOf("Operand"))
1105 PrintFatalError(Rec->getLoc(), "Operand `" + Rec->getName() +
1106 "' does not derive from class Operand!\n");
1107 Record *MatchClass = Rec->getValueAsDef("ParserMatchClass");
1108 if (ClassInfo *CI = AsmOperandClasses[MatchClass])
1111 PrintFatalError(Rec->getLoc(), "operand has no match class!");
1114 struct LessRegisterSet {
1115 bool operator() (const RegisterSet &LHS, const RegisterSet & RHS) const {
1116 // std::set<T> defines its own compariso "operator<", but it
1117 // performs a lexicographical comparison by T's innate comparison
1118 // for some reason. We don't want non-deterministic pointer
1119 // comparisons so use this instead.
1120 return std::lexicographical_compare(LHS.begin(), LHS.end(),
1121 RHS.begin(), RHS.end(),
1126 void AsmMatcherInfo::
1127 buildRegisterClasses(SmallPtrSetImpl<Record*> &SingletonRegisters) {
1128 const auto &Registers = Target.getRegBank().getRegisters();
1129 auto &RegClassList = Target.getRegBank().getRegClasses();
1131 typedef std::set<RegisterSet, LessRegisterSet> RegisterSetSet;
1133 // The register sets used for matching.
1134 RegisterSetSet RegisterSets;
1136 // Gather the defined sets.
1137 for (const CodeGenRegisterClass &RC : RegClassList)
1138 RegisterSets.insert(
1139 RegisterSet(RC.getOrder().begin(), RC.getOrder().end()));
1141 // Add any required singleton sets.
1142 for (Record *Rec : SingletonRegisters) {
1143 RegisterSets.insert(RegisterSet(&Rec, &Rec + 1));
1146 // Introduce derived sets where necessary (when a register does not determine
1147 // a unique register set class), and build the mapping of registers to the set
1148 // they should classify to.
1149 std::map<Record*, RegisterSet> RegisterMap;
1150 for (const CodeGenRegister &CGR : Registers) {
1151 // Compute the intersection of all sets containing this register.
1152 RegisterSet ContainingSet;
1154 for (const RegisterSet &RS : RegisterSets) {
1155 if (!RS.count(CGR.TheDef))
1158 if (ContainingSet.empty()) {
1164 std::swap(Tmp, ContainingSet);
1165 std::insert_iterator<RegisterSet> II(ContainingSet,
1166 ContainingSet.begin());
1167 std::set_intersection(Tmp.begin(), Tmp.end(), RS.begin(), RS.end(), II,
1171 if (!ContainingSet.empty()) {
1172 RegisterSets.insert(ContainingSet);
1173 RegisterMap.insert(std::make_pair(CGR.TheDef, ContainingSet));
1177 // Construct the register classes.
1178 std::map<RegisterSet, ClassInfo*, LessRegisterSet> RegisterSetClasses;
1180 for (const RegisterSet &RS : RegisterSets) {
1181 Classes.emplace_front();
1182 ClassInfo *CI = &Classes.front();
1183 CI->Kind = ClassInfo::RegisterClass0 + Index;
1184 CI->ClassName = "Reg" + utostr(Index);
1185 CI->Name = "MCK_Reg" + utostr(Index);
1187 CI->PredicateMethod = ""; // unused
1188 CI->RenderMethod = "addRegOperands";
1190 // FIXME: diagnostic type.
1191 CI->DiagnosticType = "";
1192 RegisterSetClasses.insert(std::make_pair(RS, CI));
1196 // Find the superclasses; we could compute only the subgroup lattice edges,
1197 // but there isn't really a point.
1198 for (const RegisterSet &RS : RegisterSets) {
1199 ClassInfo *CI = RegisterSetClasses[RS];
1200 for (const RegisterSet &RS2 : RegisterSets)
1202 std::includes(RS2.begin(), RS2.end(), RS.begin(), RS.end(),
1204 CI->SuperClasses.push_back(RegisterSetClasses[RS2]);
1207 // Name the register classes which correspond to a user defined RegisterClass.
1208 for (const CodeGenRegisterClass &RC : RegClassList) {
1209 // Def will be NULL for non-user defined register classes.
1210 Record *Def = RC.getDef();
1213 ClassInfo *CI = RegisterSetClasses[RegisterSet(RC.getOrder().begin(),
1214 RC.getOrder().end())];
1215 if (CI->ValueName.empty()) {
1216 CI->ClassName = RC.getName();
1217 CI->Name = "MCK_" + RC.getName();
1218 CI->ValueName = RC.getName();
1220 CI->ValueName = CI->ValueName + "," + RC.getName();
1222 RegisterClassClasses.insert(std::make_pair(Def, CI));
1225 // Populate the map for individual registers.
1226 for (std::map<Record*, RegisterSet>::iterator it = RegisterMap.begin(),
1227 ie = RegisterMap.end(); it != ie; ++it)
1228 RegisterClasses[it->first] = RegisterSetClasses[it->second];
1230 // Name the register classes which correspond to singleton registers.
1231 for (Record *Rec : SingletonRegisters) {
1232 ClassInfo *CI = RegisterClasses[Rec];
1233 assert(CI && "Missing singleton register class info!");
1235 if (CI->ValueName.empty()) {
1236 CI->ClassName = Rec->getName();
1237 CI->Name = "MCK_" + Rec->getName();
1238 CI->ValueName = Rec->getName();
1240 CI->ValueName = CI->ValueName + "," + Rec->getName();
1244 void AsmMatcherInfo::buildOperandClasses() {
1245 std::vector<Record*> AsmOperands =
1246 Records.getAllDerivedDefinitions("AsmOperandClass");
1248 // Pre-populate AsmOperandClasses map.
1249 for (Record *Rec : AsmOperands) {
1250 Classes.emplace_front();
1251 AsmOperandClasses[Rec] = &Classes.front();
1255 for (Record *Rec : AsmOperands) {
1256 ClassInfo *CI = AsmOperandClasses[Rec];
1257 CI->Kind = ClassInfo::UserClass0 + Index;
1259 ListInit *Supers = Rec->getValueAsListInit("SuperClasses");
1260 for (Init *I : Supers->getValues()) {
1261 DefInit *DI = dyn_cast<DefInit>(I);
1263 PrintError(Rec->getLoc(), "Invalid super class reference!");
1267 ClassInfo *SC = AsmOperandClasses[DI->getDef()];
1269 PrintError(Rec->getLoc(), "Invalid super class reference!");
1271 CI->SuperClasses.push_back(SC);
1273 CI->ClassName = Rec->getValueAsString("Name");
1274 CI->Name = "MCK_" + CI->ClassName;
1275 CI->ValueName = Rec->getName();
1277 // Get or construct the predicate method name.
1278 Init *PMName = Rec->getValueInit("PredicateMethod");
1279 if (StringInit *SI = dyn_cast<StringInit>(PMName)) {
1280 CI->PredicateMethod = SI->getValue();
1282 assert(isa<UnsetInit>(PMName) && "Unexpected PredicateMethod field!");
1283 CI->PredicateMethod = "is" + CI->ClassName;
1286 // Get or construct the render method name.
1287 Init *RMName = Rec->getValueInit("RenderMethod");
1288 if (StringInit *SI = dyn_cast<StringInit>(RMName)) {
1289 CI->RenderMethod = SI->getValue();
1291 assert(isa<UnsetInit>(RMName) && "Unexpected RenderMethod field!");
1292 CI->RenderMethod = "add" + CI->ClassName + "Operands";
1295 // Get the parse method name or leave it as empty.
1296 Init *PRMName = Rec->getValueInit("ParserMethod");
1297 if (StringInit *SI = dyn_cast<StringInit>(PRMName))
1298 CI->ParserMethod = SI->getValue();
1300 // Get the diagnostic type or leave it as empty.
1301 // Get the parse method name or leave it as empty.
1302 Init *DiagnosticType = Rec->getValueInit("DiagnosticType");
1303 if (StringInit *SI = dyn_cast<StringInit>(DiagnosticType))
1304 CI->DiagnosticType = SI->getValue();
1310 AsmMatcherInfo::AsmMatcherInfo(Record *asmParser,
1311 CodeGenTarget &target,
1312 RecordKeeper &records)
1313 : Records(records), AsmParser(asmParser), Target(target) {
1316 /// buildOperandMatchInfo - Build the necessary information to handle user
1317 /// defined operand parsing methods.
1318 void AsmMatcherInfo::buildOperandMatchInfo() {
1320 /// Map containing a mask with all operands indices that can be found for
1321 /// that class inside a instruction.
1322 typedef std::map<ClassInfo *, unsigned, less_ptr<ClassInfo>> OpClassMaskTy;
1323 OpClassMaskTy OpClassMask;
1325 for (const auto &MI : Matchables) {
1326 OpClassMask.clear();
1328 // Keep track of all operands of this instructions which belong to the
1330 for (unsigned i = 0, e = MI->AsmOperands.size(); i != e; ++i) {
1331 const MatchableInfo::AsmOperand &Op = MI->AsmOperands[i];
1332 if (Op.Class->ParserMethod.empty())
1334 unsigned &OperandMask = OpClassMask[Op.Class];
1335 OperandMask |= (1 << i);
1338 // Generate operand match info for each mnemonic/operand class pair.
1339 for (const auto &OCM : OpClassMask) {
1340 unsigned OpMask = OCM.second;
1341 ClassInfo *CI = OCM.first;
1342 OperandMatchInfo.push_back(OperandMatchEntry::create(MI.get(), CI,
1348 void AsmMatcherInfo::buildInfo() {
1349 // Build information about all of the AssemblerPredicates.
1350 std::vector<Record*> AllPredicates =
1351 Records.getAllDerivedDefinitions("Predicate");
1352 for (unsigned i = 0, e = AllPredicates.size(); i != e; ++i) {
1353 Record *Pred = AllPredicates[i];
1354 // Ignore predicates that are not intended for the assembler.
1355 if (!Pred->getValueAsBit("AssemblerMatcherPredicate"))
1358 if (Pred->getName().empty())
1359 PrintFatalError(Pred->getLoc(), "Predicate has no name!");
1361 SubtargetFeatures.insert(std::make_pair(
1362 Pred, SubtargetFeatureInfo(Pred, SubtargetFeatures.size())));
1363 DEBUG(SubtargetFeatures.find(Pred)->second.dump());
1364 assert(SubtargetFeatures.size() <= 64 && "Too many subtarget features!");
1367 // Parse the instructions; we need to do this first so that we can gather the
1368 // singleton register classes.
1369 SmallPtrSet<Record*, 16> SingletonRegisters;
1370 unsigned VariantCount = Target.getAsmParserVariantCount();
1371 for (unsigned VC = 0; VC != VariantCount; ++VC) {
1372 Record *AsmVariant = Target.getAsmParserVariant(VC);
1373 std::string CommentDelimiter =
1374 AsmVariant->getValueAsString("CommentDelimiter");
1375 std::string RegisterPrefix = AsmVariant->getValueAsString("RegisterPrefix");
1376 int AsmVariantNo = AsmVariant->getValueAsInt("Variant");
1378 for (const CodeGenInstruction *CGI : Target.instructions()) {
1380 // If the tblgen -match-prefix option is specified (for tblgen hackers),
1381 // filter the set of instructions we consider.
1382 if (!StringRef(CGI->TheDef->getName()).startswith(MatchPrefix))
1385 // Ignore "codegen only" instructions.
1386 if (CGI->TheDef->getValueAsBit("isCodeGenOnly"))
1389 auto II = llvm::make_unique<MatchableInfo>(*CGI);
1391 II->initialize(*this, SingletonRegisters, AsmVariantNo, RegisterPrefix);
1393 // Ignore instructions which shouldn't be matched and diagnose invalid
1394 // instruction definitions with an error.
1395 if (!II->validate(CommentDelimiter, true))
1398 Matchables.push_back(std::move(II));
1401 // Parse all of the InstAlias definitions and stick them in the list of
1403 std::vector<Record*> AllInstAliases =
1404 Records.getAllDerivedDefinitions("InstAlias");
1405 for (unsigned i = 0, e = AllInstAliases.size(); i != e; ++i) {
1406 auto Alias = llvm::make_unique<CodeGenInstAlias>(AllInstAliases[i],
1407 AsmVariantNo, Target);
1409 // If the tblgen -match-prefix option is specified (for tblgen hackers),
1410 // filter the set of instruction aliases we consider, based on the target
1412 if (!StringRef(Alias->ResultInst->TheDef->getName())
1413 .startswith( MatchPrefix))
1416 auto II = llvm::make_unique<MatchableInfo>(std::move(Alias));
1418 II->initialize(*this, SingletonRegisters, AsmVariantNo, RegisterPrefix);
1420 // Validate the alias definitions.
1421 II->validate(CommentDelimiter, false);
1423 Matchables.push_back(std::move(II));
1427 // Build info for the register classes.
1428 buildRegisterClasses(SingletonRegisters);
1430 // Build info for the user defined assembly operand classes.
1431 buildOperandClasses();
1433 // Build the information about matchables, now that we have fully formed
1435 std::vector<std::unique_ptr<MatchableInfo>> NewMatchables;
1436 for (auto &II : Matchables) {
1437 // Parse the tokens after the mnemonic.
1438 // Note: buildInstructionOperandReference may insert new AsmOperands, so
1439 // don't precompute the loop bound.
1440 for (unsigned i = 0; i != II->AsmOperands.size(); ++i) {
1441 MatchableInfo::AsmOperand &Op = II->AsmOperands[i];
1442 StringRef Token = Op.Token;
1444 // Check for singleton registers.
1445 if (Record *RegRecord = II->AsmOperands[i].SingletonReg) {
1446 Op.Class = RegisterClasses[RegRecord];
1447 assert(Op.Class && Op.Class->Registers.size() == 1 &&
1448 "Unexpected class for singleton register");
1452 // Check for simple tokens.
1453 if (Token[0] != '$') {
1454 Op.Class = getTokenClass(Token);
1458 if (Token.size() > 1 && isdigit(Token[1])) {
1459 Op.Class = getTokenClass(Token);
1463 // Otherwise this is an operand reference.
1464 StringRef OperandName;
1465 if (Token[1] == '{')
1466 OperandName = Token.substr(2, Token.size() - 3);
1468 OperandName = Token.substr(1);
1470 if (II->DefRec.is<const CodeGenInstruction*>())
1471 buildInstructionOperandReference(II.get(), OperandName, i);
1473 buildAliasOperandReference(II.get(), OperandName, Op);
1476 if (II->DefRec.is<const CodeGenInstruction*>()) {
1477 II->buildInstructionResultOperands();
1478 // If the instruction has a two-operand alias, build up the
1479 // matchable here. We'll add them in bulk at the end to avoid
1480 // confusing this loop.
1481 std::string Constraint =
1482 II->TheDef->getValueAsString("TwoOperandAliasConstraint");
1483 if (Constraint != "") {
1484 // Start by making a copy of the original matchable.
1485 auto AliasII = llvm::make_unique<MatchableInfo>(*II);
1487 // Adjust it to be a two-operand alias.
1488 AliasII->formTwoOperandAlias(Constraint);
1490 // Add the alias to the matchables list.
1491 NewMatchables.push_back(std::move(AliasII));
1494 II->buildAliasResultOperands();
1496 if (!NewMatchables.empty())
1497 Matchables.insert(Matchables.end(),
1498 std::make_move_iterator(NewMatchables.begin()),
1499 std::make_move_iterator(NewMatchables.end()));
1501 // Process token alias definitions and set up the associated superclass
1503 std::vector<Record*> AllTokenAliases =
1504 Records.getAllDerivedDefinitions("TokenAlias");
1505 for (unsigned i = 0, e = AllTokenAliases.size(); i != e; ++i) {
1506 Record *Rec = AllTokenAliases[i];
1507 ClassInfo *FromClass = getTokenClass(Rec->getValueAsString("FromToken"));
1508 ClassInfo *ToClass = getTokenClass(Rec->getValueAsString("ToToken"));
1509 if (FromClass == ToClass)
1510 PrintFatalError(Rec->getLoc(),
1511 "error: Destination value identical to source value.");
1512 FromClass->SuperClasses.push_back(ToClass);
1515 // Reorder classes so that classes precede super classes.
1519 /// buildInstructionOperandReference - The specified operand is a reference to a
1520 /// named operand such as $src. Resolve the Class and OperandInfo pointers.
1521 void AsmMatcherInfo::
1522 buildInstructionOperandReference(MatchableInfo *II,
1523 StringRef OperandName,
1524 unsigned AsmOpIdx) {
1525 const CodeGenInstruction &CGI = *II->DefRec.get<const CodeGenInstruction*>();
1526 const CGIOperandList &Operands = CGI.Operands;
1527 MatchableInfo::AsmOperand *Op = &II->AsmOperands[AsmOpIdx];
1529 // Map this token to an operand.
1531 if (!Operands.hasOperandNamed(OperandName, Idx))
1532 PrintFatalError(II->TheDef->getLoc(),
1533 "error: unable to find operand: '" + OperandName + "'");
1535 // If the instruction operand has multiple suboperands, but the parser
1536 // match class for the asm operand is still the default "ImmAsmOperand",
1537 // then handle each suboperand separately.
1538 if (Op->SubOpIdx == -1 && Operands[Idx].MINumOperands > 1) {
1539 Record *Rec = Operands[Idx].Rec;
1540 assert(Rec->isSubClassOf("Operand") && "Unexpected operand!");
1541 Record *MatchClass = Rec->getValueAsDef("ParserMatchClass");
1542 if (MatchClass && MatchClass->getValueAsString("Name") == "Imm") {
1543 // Insert remaining suboperands after AsmOpIdx in II->AsmOperands.
1544 StringRef Token = Op->Token; // save this in case Op gets moved
1545 for (unsigned SI = 1, SE = Operands[Idx].MINumOperands; SI != SE; ++SI) {
1546 MatchableInfo::AsmOperand NewAsmOp(/*IsIsolatedToken=*/true, Token);
1547 NewAsmOp.SubOpIdx = SI;
1548 II->AsmOperands.insert(II->AsmOperands.begin()+AsmOpIdx+SI, NewAsmOp);
1550 // Replace Op with first suboperand.
1551 Op = &II->AsmOperands[AsmOpIdx]; // update the pointer in case it moved
1556 // Set up the operand class.
1557 Op->Class = getOperandClass(Operands[Idx], Op->SubOpIdx);
1559 // If the named operand is tied, canonicalize it to the untied operand.
1560 // For example, something like:
1561 // (outs GPR:$dst), (ins GPR:$src)
1562 // with an asmstring of
1564 // we want to canonicalize to:
1566 // so that we know how to provide the $dst operand when filling in the result.
1568 if (Operands[Idx].MINumOperands == 1)
1569 OITied = Operands[Idx].getTiedRegister();
1571 // The tied operand index is an MIOperand index, find the operand that
1573 std::pair<unsigned, unsigned> Idx = Operands.getSubOperandNumber(OITied);
1574 OperandName = Operands[Idx.first].Name;
1575 Op->SubOpIdx = Idx.second;
1578 Op->SrcOpName = OperandName;
1581 /// buildAliasOperandReference - When parsing an operand reference out of the
1582 /// matching string (e.g. "movsx $src, $dst"), determine what the class of the
1583 /// operand reference is by looking it up in the result pattern definition.
1584 void AsmMatcherInfo::buildAliasOperandReference(MatchableInfo *II,
1585 StringRef OperandName,
1586 MatchableInfo::AsmOperand &Op) {
1587 const CodeGenInstAlias &CGA = *II->DefRec.get<const CodeGenInstAlias*>();
1589 // Set up the operand class.
1590 for (unsigned i = 0, e = CGA.ResultOperands.size(); i != e; ++i)
1591 if (CGA.ResultOperands[i].isRecord() &&
1592 CGA.ResultOperands[i].getName() == OperandName) {
1593 // It's safe to go with the first one we find, because CodeGenInstAlias
1594 // validates that all operands with the same name have the same record.
1595 Op.SubOpIdx = CGA.ResultInstOperandIndex[i].second;
1596 // Use the match class from the Alias definition, not the
1597 // destination instruction, as we may have an immediate that's
1598 // being munged by the match class.
1599 Op.Class = getOperandClass(CGA.ResultOperands[i].getRecord(),
1601 Op.SrcOpName = OperandName;
1605 PrintFatalError(II->TheDef->getLoc(),
1606 "error: unable to find operand: '" + OperandName + "'");
1609 void MatchableInfo::buildInstructionResultOperands() {
1610 const CodeGenInstruction *ResultInst = getResultInst();
1612 // Loop over all operands of the result instruction, determining how to
1614 for (unsigned i = 0, e = ResultInst->Operands.size(); i != e; ++i) {
1615 const CGIOperandList::OperandInfo &OpInfo = ResultInst->Operands[i];
1617 // If this is a tied operand, just copy from the previously handled operand.
1619 if (OpInfo.MINumOperands == 1)
1620 TiedOp = OpInfo.getTiedRegister();
1622 ResOperands.push_back(ResOperand::getTiedOp(TiedOp));
1626 // Find out what operand from the asmparser this MCInst operand comes from.
1627 int SrcOperand = findAsmOperandNamed(OpInfo.Name);
1628 if (OpInfo.Name.empty() || SrcOperand == -1) {
1629 // This may happen for operands that are tied to a suboperand of a
1630 // complex operand. Simply use a dummy value here; nobody should
1631 // use this operand slot.
1632 // FIXME: The long term goal is for the MCOperand list to not contain
1633 // tied operands at all.
1634 ResOperands.push_back(ResOperand::getImmOp(0));
1638 // Check if the one AsmOperand populates the entire operand.
1639 unsigned NumOperands = OpInfo.MINumOperands;
1640 if (AsmOperands[SrcOperand].SubOpIdx == -1) {
1641 ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand, NumOperands));
1645 // Add a separate ResOperand for each suboperand.
1646 for (unsigned AI = 0; AI < NumOperands; ++AI) {
1647 assert(AsmOperands[SrcOperand+AI].SubOpIdx == (int)AI &&
1648 AsmOperands[SrcOperand+AI].SrcOpName == OpInfo.Name &&
1649 "unexpected AsmOperands for suboperands");
1650 ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand + AI, 1));
1655 void MatchableInfo::buildAliasResultOperands() {
1656 const CodeGenInstAlias &CGA = *DefRec.get<const CodeGenInstAlias*>();
1657 const CodeGenInstruction *ResultInst = getResultInst();
1659 // Loop over all operands of the result instruction, determining how to
1661 unsigned AliasOpNo = 0;
1662 unsigned LastOpNo = CGA.ResultInstOperandIndex.size();
1663 for (unsigned i = 0, e = ResultInst->Operands.size(); i != e; ++i) {
1664 const CGIOperandList::OperandInfo *OpInfo = &ResultInst->Operands[i];
1666 // If this is a tied operand, just copy from the previously handled operand.
1668 if (OpInfo->MINumOperands == 1)
1669 TiedOp = OpInfo->getTiedRegister();
1671 ResOperands.push_back(ResOperand::getTiedOp(TiedOp));
1675 // Handle all the suboperands for this operand.
1676 const std::string &OpName = OpInfo->Name;
1677 for ( ; AliasOpNo < LastOpNo &&
1678 CGA.ResultInstOperandIndex[AliasOpNo].first == i; ++AliasOpNo) {
1679 int SubIdx = CGA.ResultInstOperandIndex[AliasOpNo].second;
1681 // Find out what operand from the asmparser that this MCInst operand
1683 switch (CGA.ResultOperands[AliasOpNo].Kind) {
1684 case CodeGenInstAlias::ResultOperand::K_Record: {
1685 StringRef Name = CGA.ResultOperands[AliasOpNo].getName();
1686 int SrcOperand = findAsmOperand(Name, SubIdx);
1687 if (SrcOperand == -1)
1688 PrintFatalError(TheDef->getLoc(), "Instruction '" +
1689 TheDef->getName() + "' has operand '" + OpName +
1690 "' that doesn't appear in asm string!");
1691 unsigned NumOperands = (SubIdx == -1 ? OpInfo->MINumOperands : 1);
1692 ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand,
1696 case CodeGenInstAlias::ResultOperand::K_Imm: {
1697 int64_t ImmVal = CGA.ResultOperands[AliasOpNo].getImm();
1698 ResOperands.push_back(ResOperand::getImmOp(ImmVal));
1701 case CodeGenInstAlias::ResultOperand::K_Reg: {
1702 Record *Reg = CGA.ResultOperands[AliasOpNo].getRegister();
1703 ResOperands.push_back(ResOperand::getRegOp(Reg));
1711 static unsigned getConverterOperandID(const std::string &Name,
1712 SetVector<std::string> &Table,
1714 IsNew = Table.insert(Name);
1716 unsigned ID = IsNew ? Table.size() - 1 :
1717 std::find(Table.begin(), Table.end(), Name) - Table.begin();
1719 assert(ID < Table.size());
1725 static void emitConvertFuncs(CodeGenTarget &Target, StringRef ClassName,
1726 std::vector<std::unique_ptr<MatchableInfo>> &Infos,
1728 SetVector<std::string> OperandConversionKinds;
1729 SetVector<std::string> InstructionConversionKinds;
1730 std::vector<std::vector<uint8_t> > ConversionTable;
1731 size_t MaxRowLength = 2; // minimum is custom converter plus terminator.
1733 // TargetOperandClass - This is the target's operand class, like X86Operand.
1734 std::string TargetOperandClass = Target.getName() + "Operand";
1736 // Write the convert function to a separate stream, so we can drop it after
1737 // the enum. We'll build up the conversion handlers for the individual
1738 // operand types opportunistically as we encounter them.
1739 std::string ConvertFnBody;
1740 raw_string_ostream CvtOS(ConvertFnBody);
1741 // Start the unified conversion function.
1742 CvtOS << "void " << Target.getName() << ClassName << "::\n"
1743 << "convertToMCInst(unsigned Kind, MCInst &Inst, "
1744 << "unsigned Opcode,\n"
1745 << " const OperandVector"
1746 << " &Operands) {\n"
1747 << " assert(Kind < CVT_NUM_SIGNATURES && \"Invalid signature!\");\n"
1748 << " const uint8_t *Converter = ConversionTable[Kind];\n"
1749 << " Inst.setOpcode(Opcode);\n"
1750 << " for (const uint8_t *p = Converter; *p; p+= 2) {\n"
1751 << " switch (*p) {\n"
1752 << " default: llvm_unreachable(\"invalid conversion entry!\");\n"
1753 << " case CVT_Reg:\n"
1754 << " static_cast<" << TargetOperandClass
1755 << "&>(*Operands[*(p + 1)]).addRegOperands(Inst, 1);\n"
1757 << " case CVT_Tied:\n"
1758 << " Inst.addOperand(Inst.getOperand(*(p + 1)));\n"
1761 std::string OperandFnBody;
1762 raw_string_ostream OpOS(OperandFnBody);
1763 // Start the operand number lookup function.
1764 OpOS << "void " << Target.getName() << ClassName << "::\n"
1765 << "convertToMapAndConstraints(unsigned Kind,\n";
1767 OpOS << "const OperandVector &Operands) {\n"
1768 << " assert(Kind < CVT_NUM_SIGNATURES && \"Invalid signature!\");\n"
1769 << " unsigned NumMCOperands = 0;\n"
1770 << " const uint8_t *Converter = ConversionTable[Kind];\n"
1771 << " for (const uint8_t *p = Converter; *p; p+= 2) {\n"
1772 << " switch (*p) {\n"
1773 << " default: llvm_unreachable(\"invalid conversion entry!\");\n"
1774 << " case CVT_Reg:\n"
1775 << " Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n"
1776 << " Operands[*(p + 1)]->setConstraint(\"r\");\n"
1777 << " ++NumMCOperands;\n"
1779 << " case CVT_Tied:\n"
1780 << " ++NumMCOperands;\n"
1783 // Pre-populate the operand conversion kinds with the standard always
1784 // available entries.
1785 OperandConversionKinds.insert("CVT_Done");
1786 OperandConversionKinds.insert("CVT_Reg");
1787 OperandConversionKinds.insert("CVT_Tied");
1788 enum { CVT_Done, CVT_Reg, CVT_Tied };
1790 for (auto &II : Infos) {
1791 // Check if we have a custom match function.
1792 std::string AsmMatchConverter =
1793 II->getResultInst()->TheDef->getValueAsString("AsmMatchConverter");
1794 if (!AsmMatchConverter.empty() && II->UseInstAsmMatchConverter) {
1795 std::string Signature = "ConvertCustom_" + AsmMatchConverter;
1796 II->ConversionFnKind = Signature;
1798 // Check if we have already generated this signature.
1799 if (!InstructionConversionKinds.insert(Signature))
1802 // Remember this converter for the kind enum.
1803 unsigned KindID = OperandConversionKinds.size();
1804 OperandConversionKinds.insert("CVT_" +
1805 getEnumNameForToken(AsmMatchConverter));
1807 // Add the converter row for this instruction.
1808 ConversionTable.emplace_back();
1809 ConversionTable.back().push_back(KindID);
1810 ConversionTable.back().push_back(CVT_Done);
1812 // Add the handler to the conversion driver function.
1813 CvtOS << " case CVT_"
1814 << getEnumNameForToken(AsmMatchConverter) << ":\n"
1815 << " " << AsmMatchConverter << "(Inst, Operands);\n"
1818 // FIXME: Handle the operand number lookup for custom match functions.
1822 // Build the conversion function signature.
1823 std::string Signature = "Convert";
1825 std::vector<uint8_t> ConversionRow;
1827 // Compute the convert enum and the case body.
1828 MaxRowLength = std::max(MaxRowLength, II->ResOperands.size()*2 + 1 );
1830 for (unsigned i = 0, e = II->ResOperands.size(); i != e; ++i) {
1831 const MatchableInfo::ResOperand &OpInfo = II->ResOperands[i];
1833 // Generate code to populate each result operand.
1834 switch (OpInfo.Kind) {
1835 case MatchableInfo::ResOperand::RenderAsmOperand: {
1836 // This comes from something we parsed.
1837 const MatchableInfo::AsmOperand &Op =
1838 II->AsmOperands[OpInfo.AsmOperandNum];
1840 // Registers are always converted the same, don't duplicate the
1841 // conversion function based on them.
1844 Class = Op.Class->isRegisterClass() ? "Reg" : Op.Class->ClassName;
1846 Signature += utostr(OpInfo.MINumOperands);
1847 Signature += "_" + itostr(OpInfo.AsmOperandNum);
1849 // Add the conversion kind, if necessary, and get the associated ID
1850 // the index of its entry in the vector).
1851 std::string Name = "CVT_" + (Op.Class->isRegisterClass() ? "Reg" :
1852 Op.Class->RenderMethod);
1853 Name = getEnumNameForToken(Name);
1855 bool IsNewConverter = false;
1856 unsigned ID = getConverterOperandID(Name, OperandConversionKinds,
1859 // Add the operand entry to the instruction kind conversion row.
1860 ConversionRow.push_back(ID);
1861 ConversionRow.push_back(OpInfo.AsmOperandNum + 1);
1863 if (!IsNewConverter)
1866 // This is a new operand kind. Add a handler for it to the
1867 // converter driver.
1868 CvtOS << " case " << Name << ":\n"
1869 << " static_cast<" << TargetOperandClass
1870 << "&>(*Operands[*(p + 1)])." << Op.Class->RenderMethod
1871 << "(Inst, " << OpInfo.MINumOperands << ");\n"
1874 // Add a handler for the operand number lookup.
1875 OpOS << " case " << Name << ":\n"
1876 << " Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n";
1878 if (Op.Class->isRegisterClass())
1879 OpOS << " Operands[*(p + 1)]->setConstraint(\"r\");\n";
1881 OpOS << " Operands[*(p + 1)]->setConstraint(\"m\");\n";
1882 OpOS << " NumMCOperands += " << OpInfo.MINumOperands << ";\n"
1886 case MatchableInfo::ResOperand::TiedOperand: {
1887 // If this operand is tied to a previous one, just copy the MCInst
1888 // operand from the earlier one.We can only tie single MCOperand values.
1889 assert(OpInfo.MINumOperands == 1 && "Not a singular MCOperand");
1890 unsigned TiedOp = OpInfo.TiedOperandNum;
1891 assert(i > TiedOp && "Tied operand precedes its target!");
1892 Signature += "__Tie" + utostr(TiedOp);
1893 ConversionRow.push_back(CVT_Tied);
1894 ConversionRow.push_back(TiedOp);
1897 case MatchableInfo::ResOperand::ImmOperand: {
1898 int64_t Val = OpInfo.ImmVal;
1899 std::string Ty = "imm_" + itostr(Val);
1900 Ty = getEnumNameForToken(Ty);
1901 Signature += "__" + Ty;
1903 std::string Name = "CVT_" + Ty;
1904 bool IsNewConverter = false;
1905 unsigned ID = getConverterOperandID(Name, OperandConversionKinds,
1907 // Add the operand entry to the instruction kind conversion row.
1908 ConversionRow.push_back(ID);
1909 ConversionRow.push_back(0);
1911 if (!IsNewConverter)
1914 CvtOS << " case " << Name << ":\n"
1915 << " Inst.addOperand(MCOperand::createImm(" << Val << "));\n"
1918 OpOS << " case " << Name << ":\n"
1919 << " Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n"
1920 << " Operands[*(p + 1)]->setConstraint(\"\");\n"
1921 << " ++NumMCOperands;\n"
1925 case MatchableInfo::ResOperand::RegOperand: {
1926 std::string Reg, Name;
1927 if (!OpInfo.Register) {
1931 Reg = getQualifiedName(OpInfo.Register);
1932 Name = "reg" + OpInfo.Register->getName();
1934 Signature += "__" + Name;
1935 Name = "CVT_" + Name;
1936 bool IsNewConverter = false;
1937 unsigned ID = getConverterOperandID(Name, OperandConversionKinds,
1939 // Add the operand entry to the instruction kind conversion row.
1940 ConversionRow.push_back(ID);
1941 ConversionRow.push_back(0);
1943 if (!IsNewConverter)
1945 CvtOS << " case " << Name << ":\n"
1946 << " Inst.addOperand(MCOperand::createReg(" << Reg << "));\n"
1949 OpOS << " case " << Name << ":\n"
1950 << " Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n"
1951 << " Operands[*(p + 1)]->setConstraint(\"m\");\n"
1952 << " ++NumMCOperands;\n"
1958 // If there were no operands, add to the signature to that effect
1959 if (Signature == "Convert")
1960 Signature += "_NoOperands";
1962 II->ConversionFnKind = Signature;
1964 // Save the signature. If we already have it, don't add a new row
1966 if (!InstructionConversionKinds.insert(Signature))
1969 // Add the row to the table.
1970 ConversionTable.push_back(std::move(ConversionRow));
1973 // Finish up the converter driver function.
1974 CvtOS << " }\n }\n}\n\n";
1976 // Finish up the operand number lookup function.
1977 OpOS << " }\n }\n}\n\n";
1979 OS << "namespace {\n";
1981 // Output the operand conversion kind enum.
1982 OS << "enum OperatorConversionKind {\n";
1983 for (unsigned i = 0, e = OperandConversionKinds.size(); i != e; ++i)
1984 OS << " " << OperandConversionKinds[i] << ",\n";
1985 OS << " CVT_NUM_CONVERTERS\n";
1988 // Output the instruction conversion kind enum.
1989 OS << "enum InstructionConversionKind {\n";
1990 for (const std::string &Signature : InstructionConversionKinds)
1991 OS << " " << Signature << ",\n";
1992 OS << " CVT_NUM_SIGNATURES\n";
1996 OS << "} // end anonymous namespace\n\n";
1998 // Output the conversion table.
1999 OS << "static const uint8_t ConversionTable[CVT_NUM_SIGNATURES]["
2000 << MaxRowLength << "] = {\n";
2002 for (unsigned Row = 0, ERow = ConversionTable.size(); Row != ERow; ++Row) {
2003 assert(ConversionTable[Row].size() % 2 == 0 && "bad conversion row!");
2004 OS << " // " << InstructionConversionKinds[Row] << "\n";
2006 for (unsigned i = 0, e = ConversionTable[Row].size(); i != e; i += 2)
2007 OS << OperandConversionKinds[ConversionTable[Row][i]] << ", "
2008 << (unsigned)(ConversionTable[Row][i + 1]) << ", ";
2009 OS << "CVT_Done },\n";
2014 // Spit out the conversion driver function.
2017 // Spit out the operand number lookup function.
2021 /// emitMatchClassEnumeration - Emit the enumeration for match class kinds.
2022 static void emitMatchClassEnumeration(CodeGenTarget &Target,
2023 std::forward_list<ClassInfo> &Infos,
2025 OS << "namespace {\n\n";
2027 OS << "/// MatchClassKind - The kinds of classes which participate in\n"
2028 << "/// instruction matching.\n";
2029 OS << "enum MatchClassKind {\n";
2030 OS << " InvalidMatchClass = 0,\n";
2031 for (const auto &CI : Infos) {
2032 OS << " " << CI.Name << ", // ";
2033 if (CI.Kind == ClassInfo::Token) {
2034 OS << "'" << CI.ValueName << "'\n";
2035 } else if (CI.isRegisterClass()) {
2036 if (!CI.ValueName.empty())
2037 OS << "register class '" << CI.ValueName << "'\n";
2039 OS << "derived register class\n";
2041 OS << "user defined class '" << CI.ValueName << "'\n";
2044 OS << " NumMatchClassKinds\n";
2050 /// emitValidateOperandClass - Emit the function to validate an operand class.
2051 static void emitValidateOperandClass(AsmMatcherInfo &Info,
2053 OS << "static unsigned validateOperandClass(MCParsedAsmOperand &GOp, "
2054 << "MatchClassKind Kind) {\n";
2055 OS << " " << Info.Target.getName() << "Operand &Operand = ("
2056 << Info.Target.getName() << "Operand&)GOp;\n";
2058 // The InvalidMatchClass is not to match any operand.
2059 OS << " if (Kind == InvalidMatchClass)\n";
2060 OS << " return MCTargetAsmParser::Match_InvalidOperand;\n\n";
2062 // Check for Token operands first.
2063 // FIXME: Use a more specific diagnostic type.
2064 OS << " if (Operand.isToken())\n";
2065 OS << " return isSubclass(matchTokenString(Operand.getToken()), Kind) ?\n"
2066 << " MCTargetAsmParser::Match_Success :\n"
2067 << " MCTargetAsmParser::Match_InvalidOperand;\n\n";
2069 // Check the user classes. We don't care what order since we're only
2070 // actually matching against one of them.
2071 for (const auto &CI : Info.Classes) {
2072 if (!CI.isUserClass())
2075 OS << " // '" << CI.ClassName << "' class\n";
2076 OS << " if (Kind == " << CI.Name << ") {\n";
2077 OS << " if (Operand." << CI.PredicateMethod << "())\n";
2078 OS << " return MCTargetAsmParser::Match_Success;\n";
2079 if (!CI.DiagnosticType.empty())
2080 OS << " return " << Info.Target.getName() << "AsmParser::Match_"
2081 << CI.DiagnosticType << ";\n";
2085 // Check for register operands, including sub-classes.
2086 OS << " if (Operand.isReg()) {\n";
2087 OS << " MatchClassKind OpKind;\n";
2088 OS << " switch (Operand.getReg()) {\n";
2089 OS << " default: OpKind = InvalidMatchClass; break;\n";
2090 for (const auto &RC : Info.RegisterClasses)
2091 OS << " case " << Info.Target.getName() << "::"
2092 << RC.first->getName() << ": OpKind = " << RC.second->Name
2095 OS << " return isSubclass(OpKind, Kind) ? "
2096 << "MCTargetAsmParser::Match_Success :\n "
2097 << " MCTargetAsmParser::Match_InvalidOperand;\n }\n\n";
2099 // Generic fallthrough match failure case for operands that don't have
2100 // specialized diagnostic types.
2101 OS << " return MCTargetAsmParser::Match_InvalidOperand;\n";
2105 /// emitIsSubclass - Emit the subclass predicate function.
2106 static void emitIsSubclass(CodeGenTarget &Target,
2107 std::forward_list<ClassInfo> &Infos,
2109 OS << "/// isSubclass - Compute whether \\p A is a subclass of \\p B.\n";
2110 OS << "static bool isSubclass(MatchClassKind A, MatchClassKind B) {\n";
2111 OS << " if (A == B)\n";
2112 OS << " return true;\n\n";
2115 raw_string_ostream SS(OStr);
2117 SS << " switch (A) {\n";
2118 SS << " default:\n";
2119 SS << " return false;\n";
2120 for (const auto &A : Infos) {
2121 std::vector<StringRef> SuperClasses;
2122 for (const auto &B : Infos) {
2123 if (&A != &B && A.isSubsetOf(B))
2124 SuperClasses.push_back(B.Name);
2127 if (SuperClasses.empty())
2131 SS << "\n case " << A.Name << ":\n";
2133 if (SuperClasses.size() == 1) {
2134 SS << " return B == " << SuperClasses.back().str() << ";\n";
2138 if (!SuperClasses.empty()) {
2139 SS << " switch (B) {\n";
2140 SS << " default: return false;\n";
2141 for (unsigned i = 0, e = SuperClasses.size(); i != e; ++i)
2142 SS << " case " << SuperClasses[i].str() << ": return true;\n";
2145 // No case statement to emit
2146 SS << " return false;\n";
2151 // If there were case statements emitted into the string stream, write them
2152 // to the output stream, otherwise write the default.
2156 OS << " return false;\n";
2161 /// emitMatchTokenString - Emit the function to match a token string to the
2162 /// appropriate match class value.
2163 static void emitMatchTokenString(CodeGenTarget &Target,
2164 std::forward_list<ClassInfo> &Infos,
2166 // Construct the match list.
2167 std::vector<StringMatcher::StringPair> Matches;
2168 for (const auto &CI : Infos) {
2169 if (CI.Kind == ClassInfo::Token)
2170 Matches.emplace_back(CI.ValueName, "return " + CI.Name + ";");
2173 OS << "static MatchClassKind matchTokenString(StringRef Name) {\n";
2175 StringMatcher("Name", Matches, OS).Emit();
2177 OS << " return InvalidMatchClass;\n";
2181 /// emitMatchRegisterName - Emit the function to match a string to the target
2182 /// specific register enum.
2183 static void emitMatchRegisterName(CodeGenTarget &Target, Record *AsmParser,
2185 // Construct the match list.
2186 std::vector<StringMatcher::StringPair> Matches;
2187 const auto &Regs = Target.getRegBank().getRegisters();
2188 for (const CodeGenRegister &Reg : Regs) {
2189 if (Reg.TheDef->getValueAsString("AsmName").empty())
2192 Matches.emplace_back(Reg.TheDef->getValueAsString("AsmName"),
2193 "return " + utostr(Reg.EnumValue) + ";");
2196 OS << "static unsigned MatchRegisterName(StringRef Name) {\n";
2198 StringMatcher("Name", Matches, OS).Emit();
2200 OS << " return 0;\n";
2204 static const char *getMinimalTypeForRange(uint64_t Range) {
2205 assert(Range <= 0xFFFFFFFFFFFFFFFFULL && "Enum too large");
2206 if (Range > 0xFFFFFFFFULL)
2215 static const char *getMinimalRequiredFeaturesType(const AsmMatcherInfo &Info) {
2216 uint64_t MaxIndex = Info.SubtargetFeatures.size();
2219 return getMinimalTypeForRange(1ULL << MaxIndex);
2222 /// emitSubtargetFeatureFlagEnumeration - Emit the subtarget feature flag
2224 static void emitSubtargetFeatureFlagEnumeration(AsmMatcherInfo &Info,
2226 OS << "// Flags for subtarget features that participate in "
2227 << "instruction matching.\n";
2228 OS << "enum SubtargetFeatureFlag : " << getMinimalRequiredFeaturesType(Info)
2230 for (const auto &SF : Info.SubtargetFeatures) {
2231 const SubtargetFeatureInfo &SFI = SF.second;
2232 OS << " " << SFI.getEnumName() << " = (1ULL << " << SFI.Index << "),\n";
2234 OS << " Feature_None = 0\n";
2238 /// emitOperandDiagnosticTypes - Emit the operand matching diagnostic types.
2239 static void emitOperandDiagnosticTypes(AsmMatcherInfo &Info, raw_ostream &OS) {
2240 // Get the set of diagnostic types from all of the operand classes.
2241 std::set<StringRef> Types;
2242 for (std::map<Record*, ClassInfo*>::const_iterator
2243 I = Info.AsmOperandClasses.begin(),
2244 E = Info.AsmOperandClasses.end(); I != E; ++I) {
2245 if (!I->second->DiagnosticType.empty())
2246 Types.insert(I->second->DiagnosticType);
2249 if (Types.empty()) return;
2251 // Now emit the enum entries.
2252 for (std::set<StringRef>::const_iterator I = Types.begin(), E = Types.end();
2254 OS << " Match_" << *I << ",\n";
2255 OS << " END_OPERAND_DIAGNOSTIC_TYPES\n";
2258 /// emitGetSubtargetFeatureName - Emit the helper function to get the
2259 /// user-level name for a subtarget feature.
2260 static void emitGetSubtargetFeatureName(AsmMatcherInfo &Info, raw_ostream &OS) {
2261 OS << "// User-level names for subtarget features that participate in\n"
2262 << "// instruction matching.\n"
2263 << "static const char *getSubtargetFeatureName(uint64_t Val) {\n";
2264 if (!Info.SubtargetFeatures.empty()) {
2265 OS << " switch(Val) {\n";
2266 for (const auto &SF : Info.SubtargetFeatures) {
2267 const SubtargetFeatureInfo &SFI = SF.second;
2268 // FIXME: Totally just a placeholder name to get the algorithm working.
2269 OS << " case " << SFI.getEnumName() << ": return \""
2270 << SFI.TheDef->getValueAsString("PredicateName") << "\";\n";
2272 OS << " default: return \"(unknown)\";\n";
2275 // Nothing to emit, so skip the switch
2276 OS << " return \"(unknown)\";\n";
2281 /// emitComputeAvailableFeatures - Emit the function to compute the list of
2282 /// available features given a subtarget.
2283 static void emitComputeAvailableFeatures(AsmMatcherInfo &Info,
2285 std::string ClassName =
2286 Info.AsmParser->getValueAsString("AsmParserClassName");
2288 OS << "uint64_t " << Info.Target.getName() << ClassName << "::\n"
2289 << "ComputeAvailableFeatures(const FeatureBitset& FB) const {\n";
2290 OS << " uint64_t Features = 0;\n";
2291 for (const auto &SF : Info.SubtargetFeatures) {
2292 const SubtargetFeatureInfo &SFI = SF.second;
2295 std::string CondStorage =
2296 SFI.TheDef->getValueAsString("AssemblerCondString");
2297 StringRef Conds = CondStorage;
2298 std::pair<StringRef,StringRef> Comma = Conds.split(',');
2305 StringRef Cond = Comma.first;
2306 if (Cond[0] == '!') {
2308 Cond = Cond.substr(1);
2314 OS << "FB[" << Info.Target.getName() << "::" << Cond << "])";
2316 if (Comma.second.empty())
2320 Comma = Comma.second.split(',');
2324 OS << " Features |= " << SFI.getEnumName() << ";\n";
2326 OS << " return Features;\n";
2330 static std::string GetAliasRequiredFeatures(Record *R,
2331 const AsmMatcherInfo &Info) {
2332 std::vector<Record*> ReqFeatures = R->getValueAsListOfDefs("Predicates");
2334 unsigned NumFeatures = 0;
2335 for (unsigned i = 0, e = ReqFeatures.size(); i != e; ++i) {
2336 const SubtargetFeatureInfo *F = Info.getSubtargetFeature(ReqFeatures[i]);
2339 PrintFatalError(R->getLoc(), "Predicate '" + ReqFeatures[i]->getName() +
2340 "' is not marked as an AssemblerPredicate!");
2345 Result += F->getEnumName();
2349 if (NumFeatures > 1)
2350 Result = '(' + Result + ')';
2354 static void emitMnemonicAliasVariant(raw_ostream &OS,const AsmMatcherInfo &Info,
2355 std::vector<Record*> &Aliases,
2356 unsigned Indent = 0,
2357 StringRef AsmParserVariantName = StringRef()){
2358 // Keep track of all the aliases from a mnemonic. Use an std::map so that the
2359 // iteration order of the map is stable.
2360 std::map<std::string, std::vector<Record*> > AliasesFromMnemonic;
2362 for (unsigned i = 0, e = Aliases.size(); i != e; ++i) {
2363 Record *R = Aliases[i];
2364 // FIXME: Allow AssemblerVariantName to be a comma separated list.
2365 std::string AsmVariantName = R->getValueAsString("AsmVariantName");
2366 if (AsmVariantName != AsmParserVariantName)
2368 AliasesFromMnemonic[R->getValueAsString("FromMnemonic")].push_back(R);
2370 if (AliasesFromMnemonic.empty())
2373 // Process each alias a "from" mnemonic at a time, building the code executed
2374 // by the string remapper.
2375 std::vector<StringMatcher::StringPair> Cases;
2376 for (std::map<std::string, std::vector<Record*> >::iterator
2377 I = AliasesFromMnemonic.begin(), E = AliasesFromMnemonic.end();
2379 const std::vector<Record*> &ToVec = I->second;
2381 // Loop through each alias and emit code that handles each case. If there
2382 // are two instructions without predicates, emit an error. If there is one,
2384 std::string MatchCode;
2385 int AliasWithNoPredicate = -1;
2387 for (unsigned i = 0, e = ToVec.size(); i != e; ++i) {
2388 Record *R = ToVec[i];
2389 std::string FeatureMask = GetAliasRequiredFeatures(R, Info);
2391 // If this unconditionally matches, remember it for later and diagnose
2393 if (FeatureMask.empty()) {
2394 if (AliasWithNoPredicate != -1) {
2395 // We can't have two aliases from the same mnemonic with no predicate.
2396 PrintError(ToVec[AliasWithNoPredicate]->getLoc(),
2397 "two MnemonicAliases with the same 'from' mnemonic!");
2398 PrintFatalError(R->getLoc(), "this is the other MnemonicAlias.");
2401 AliasWithNoPredicate = i;
2404 if (R->getValueAsString("ToMnemonic") == I->first)
2405 PrintFatalError(R->getLoc(), "MnemonicAlias to the same string");
2407 if (!MatchCode.empty())
2408 MatchCode += "else ";
2409 MatchCode += "if ((Features & " + FeatureMask + ") == "+FeatureMask+")\n";
2410 MatchCode += " Mnemonic = \"" +R->getValueAsString("ToMnemonic")+"\";\n";
2413 if (AliasWithNoPredicate != -1) {
2414 Record *R = ToVec[AliasWithNoPredicate];
2415 if (!MatchCode.empty())
2416 MatchCode += "else\n ";
2417 MatchCode += "Mnemonic = \"" + R->getValueAsString("ToMnemonic")+"\";\n";
2420 MatchCode += "return;";
2422 Cases.push_back(std::make_pair(I->first, MatchCode));
2424 StringMatcher("Mnemonic", Cases, OS).Emit(Indent);
2427 /// emitMnemonicAliases - If the target has any MnemonicAlias<> definitions,
2428 /// emit a function for them and return true, otherwise return false.
2429 static bool emitMnemonicAliases(raw_ostream &OS, const AsmMatcherInfo &Info,
2430 CodeGenTarget &Target) {
2431 // Ignore aliases when match-prefix is set.
2432 if (!MatchPrefix.empty())
2435 std::vector<Record*> Aliases =
2436 Info.getRecords().getAllDerivedDefinitions("MnemonicAlias");
2437 if (Aliases.empty()) return false;
2439 OS << "static void applyMnemonicAliases(StringRef &Mnemonic, "
2440 "uint64_t Features, unsigned VariantID) {\n";
2441 OS << " switch (VariantID) {\n";
2442 unsigned VariantCount = Target.getAsmParserVariantCount();
2443 for (unsigned VC = 0; VC != VariantCount; ++VC) {
2444 Record *AsmVariant = Target.getAsmParserVariant(VC);
2445 int AsmParserVariantNo = AsmVariant->getValueAsInt("Variant");
2446 std::string AsmParserVariantName = AsmVariant->getValueAsString("Name");
2447 OS << " case " << AsmParserVariantNo << ":\n";
2448 emitMnemonicAliasVariant(OS, Info, Aliases, /*Indent=*/2,
2449 AsmParserVariantName);
2454 // Emit aliases that apply to all variants.
2455 emitMnemonicAliasVariant(OS, Info, Aliases);
2462 static void emitCustomOperandParsing(raw_ostream &OS, CodeGenTarget &Target,
2463 const AsmMatcherInfo &Info, StringRef ClassName,
2464 StringToOffsetTable &StringTable,
2465 unsigned MaxMnemonicIndex) {
2466 unsigned MaxMask = 0;
2467 for (std::vector<OperandMatchEntry>::const_iterator it =
2468 Info.OperandMatchInfo.begin(), ie = Info.OperandMatchInfo.end();
2470 MaxMask |= it->OperandMask;
2473 // Emit the static custom operand parsing table;
2474 OS << "namespace {\n";
2475 OS << " struct OperandMatchEntry {\n";
2476 OS << " " << getMinimalRequiredFeaturesType(Info)
2477 << " RequiredFeatures;\n";
2478 OS << " " << getMinimalTypeForRange(MaxMnemonicIndex)
2480 OS << " " << getMinimalTypeForRange(std::distance(
2481 Info.Classes.begin(), Info.Classes.end())) << " Class;\n";
2482 OS << " " << getMinimalTypeForRange(MaxMask)
2483 << " OperandMask;\n\n";
2484 OS << " StringRef getMnemonic() const {\n";
2485 OS << " return StringRef(MnemonicTable + Mnemonic + 1,\n";
2486 OS << " MnemonicTable[Mnemonic]);\n";
2490 OS << " // Predicate for searching for an opcode.\n";
2491 OS << " struct LessOpcodeOperand {\n";
2492 OS << " bool operator()(const OperandMatchEntry &LHS, StringRef RHS) {\n";
2493 OS << " return LHS.getMnemonic() < RHS;\n";
2495 OS << " bool operator()(StringRef LHS, const OperandMatchEntry &RHS) {\n";
2496 OS << " return LHS < RHS.getMnemonic();\n";
2498 OS << " bool operator()(const OperandMatchEntry &LHS,";
2499 OS << " const OperandMatchEntry &RHS) {\n";
2500 OS << " return LHS.getMnemonic() < RHS.getMnemonic();\n";
2504 OS << "} // end anonymous namespace.\n\n";
2506 OS << "static const OperandMatchEntry OperandMatchTable["
2507 << Info.OperandMatchInfo.size() << "] = {\n";
2509 OS << " /* Operand List Mask, Mnemonic, Operand Class, Features */\n";
2510 for (std::vector<OperandMatchEntry>::const_iterator it =
2511 Info.OperandMatchInfo.begin(), ie = Info.OperandMatchInfo.end();
2513 const OperandMatchEntry &OMI = *it;
2514 const MatchableInfo &II = *OMI.MI;
2518 // Write the required features mask.
2519 if (!II.RequiredFeatures.empty()) {
2520 for (unsigned i = 0, e = II.RequiredFeatures.size(); i != e; ++i) {
2522 OS << II.RequiredFeatures[i]->getEnumName();
2527 // Store a pascal-style length byte in the mnemonic.
2528 std::string LenMnemonic = char(II.Mnemonic.size()) + II.Mnemonic.str();
2529 OS << ", " << StringTable.GetOrAddStringOffset(LenMnemonic, false)
2530 << " /* " << II.Mnemonic << " */, ";
2534 OS << ", " << OMI.OperandMask;
2536 bool printComma = false;
2537 for (int i = 0, e = 31; i !=e; ++i)
2538 if (OMI.OperandMask & (1 << i)) {
2550 // Emit the operand class switch to call the correct custom parser for
2551 // the found operand class.
2552 OS << Target.getName() << ClassName << "::OperandMatchResultTy "
2553 << Target.getName() << ClassName << "::\n"
2554 << "tryCustomParseOperand(OperandVector"
2555 << " &Operands,\n unsigned MCK) {\n\n"
2556 << " switch(MCK) {\n";
2558 for (const auto &CI : Info.Classes) {
2559 if (CI.ParserMethod.empty())
2561 OS << " case " << CI.Name << ":\n"
2562 << " return " << CI.ParserMethod << "(Operands);\n";
2565 OS << " default:\n";
2566 OS << " return MatchOperand_NoMatch;\n";
2568 OS << " return MatchOperand_NoMatch;\n";
2571 // Emit the static custom operand parser. This code is very similar with
2572 // the other matcher. Also use MatchResultTy here just in case we go for
2573 // a better error handling.
2574 OS << Target.getName() << ClassName << "::OperandMatchResultTy "
2575 << Target.getName() << ClassName << "::\n"
2576 << "MatchOperandParserImpl(OperandVector"
2577 << " &Operands,\n StringRef Mnemonic) {\n";
2579 // Emit code to get the available features.
2580 OS << " // Get the current feature set.\n";
2581 OS << " uint64_t AvailableFeatures = getAvailableFeatures();\n\n";
2583 OS << " // Get the next operand index.\n";
2584 OS << " unsigned NextOpNum = Operands.size()-1;\n";
2586 // Emit code to search the table.
2587 OS << " // Search the table.\n";
2588 OS << " std::pair<const OperandMatchEntry*, const OperandMatchEntry*>";
2589 OS << " MnemonicRange =\n";
2590 OS << " std::equal_range(OperandMatchTable, OperandMatchTable+"
2591 << Info.OperandMatchInfo.size() << ", Mnemonic,\n"
2592 << " LessOpcodeOperand());\n\n";
2594 OS << " if (MnemonicRange.first == MnemonicRange.second)\n";
2595 OS << " return MatchOperand_NoMatch;\n\n";
2597 OS << " for (const OperandMatchEntry *it = MnemonicRange.first,\n"
2598 << " *ie = MnemonicRange.second; it != ie; ++it) {\n";
2600 OS << " // equal_range guarantees that instruction mnemonic matches.\n";
2601 OS << " assert(Mnemonic == it->getMnemonic());\n\n";
2603 // Emit check that the required features are available.
2604 OS << " // check if the available features match\n";
2605 OS << " if ((AvailableFeatures & it->RequiredFeatures) "
2606 << "!= it->RequiredFeatures) {\n";
2607 OS << " continue;\n";
2610 // Emit check to ensure the operand number matches.
2611 OS << " // check if the operand in question has a custom parser.\n";
2612 OS << " if (!(it->OperandMask & (1 << NextOpNum)))\n";
2613 OS << " continue;\n\n";
2615 // Emit call to the custom parser method
2616 OS << " // call custom parse method to handle the operand\n";
2617 OS << " OperandMatchResultTy Result = ";
2618 OS << "tryCustomParseOperand(Operands, it->Class);\n";
2619 OS << " if (Result != MatchOperand_NoMatch)\n";
2620 OS << " return Result;\n";
2623 OS << " // Okay, we had no match.\n";
2624 OS << " return MatchOperand_NoMatch;\n";
2628 void AsmMatcherEmitter::run(raw_ostream &OS) {
2629 CodeGenTarget Target(Records);
2630 Record *AsmParser = Target.getAsmParser();
2631 std::string ClassName = AsmParser->getValueAsString("AsmParserClassName");
2633 // Compute the information on the instructions to match.
2634 AsmMatcherInfo Info(AsmParser, Target, Records);
2637 // Sort the instruction table using the partial order on classes. We use
2638 // stable_sort to ensure that ambiguous instructions are still
2639 // deterministically ordered.
2640 std::stable_sort(Info.Matchables.begin(), Info.Matchables.end(),
2641 [](const std::unique_ptr<MatchableInfo> &a,
2642 const std::unique_ptr<MatchableInfo> &b){
2645 DEBUG_WITH_TYPE("instruction_info", {
2646 for (const auto &MI : Info.Matchables)
2650 // Check for ambiguous matchables.
2651 DEBUG_WITH_TYPE("ambiguous_instrs", {
2652 unsigned NumAmbiguous = 0;
2653 for (auto I = Info.Matchables.begin(), E = Info.Matchables.end(); I != E;
2655 for (auto J = std::next(I); J != E; ++J) {
2656 const MatchableInfo &A = **I;
2657 const MatchableInfo &B = **J;
2659 if (A.couldMatchAmbiguouslyWith(B)) {
2660 errs() << "warning: ambiguous matchables:\n";
2662 errs() << "\nis incomparable with:\n";
2670 errs() << "warning: " << NumAmbiguous
2671 << " ambiguous matchables!\n";
2674 // Compute the information on the custom operand parsing.
2675 Info.buildOperandMatchInfo();
2677 // Write the output.
2679 // Information for the class declaration.
2680 OS << "\n#ifdef GET_ASSEMBLER_HEADER\n";
2681 OS << "#undef GET_ASSEMBLER_HEADER\n";
2682 OS << " // This should be included into the middle of the declaration of\n";
2683 OS << " // your subclasses implementation of MCTargetAsmParser.\n";
2684 OS << " uint64_t ComputeAvailableFeatures(const FeatureBitset& FB) const;\n";
2685 OS << " void convertToMCInst(unsigned Kind, MCInst &Inst, "
2686 << "unsigned Opcode,\n"
2687 << " const OperandVector "
2689 OS << " void convertToMapAndConstraints(unsigned Kind,\n ";
2690 OS << " const OperandVector &Operands) override;\n";
2691 OS << " bool mnemonicIsValid(StringRef Mnemonic, unsigned VariantID) override;\n";
2692 OS << " unsigned MatchInstructionImpl(const OperandVector &Operands,\n"
2693 << " MCInst &Inst,\n"
2694 << " uint64_t &ErrorInfo,"
2695 << " bool matchingInlineAsm,\n"
2696 << " unsigned VariantID = 0);\n";
2698 if (!Info.OperandMatchInfo.empty()) {
2699 OS << "\n enum OperandMatchResultTy {\n";
2700 OS << " MatchOperand_Success, // operand matched successfully\n";
2701 OS << " MatchOperand_NoMatch, // operand did not match\n";
2702 OS << " MatchOperand_ParseFail // operand matched but had errors\n";
2704 OS << " OperandMatchResultTy MatchOperandParserImpl(\n";
2705 OS << " OperandVector &Operands,\n";
2706 OS << " StringRef Mnemonic);\n";
2708 OS << " OperandMatchResultTy tryCustomParseOperand(\n";
2709 OS << " OperandVector &Operands,\n";
2710 OS << " unsigned MCK);\n\n";
2713 OS << "#endif // GET_ASSEMBLER_HEADER_INFO\n\n";
2715 // Emit the operand match diagnostic enum names.
2716 OS << "\n#ifdef GET_OPERAND_DIAGNOSTIC_TYPES\n";
2717 OS << "#undef GET_OPERAND_DIAGNOSTIC_TYPES\n\n";
2718 emitOperandDiagnosticTypes(Info, OS);
2719 OS << "#endif // GET_OPERAND_DIAGNOSTIC_TYPES\n\n";
2722 OS << "\n#ifdef GET_REGISTER_MATCHER\n";
2723 OS << "#undef GET_REGISTER_MATCHER\n\n";
2725 // Emit the subtarget feature enumeration.
2726 emitSubtargetFeatureFlagEnumeration(Info, OS);
2728 // Emit the function to match a register name to number.
2729 // This should be omitted for Mips target
2730 if (AsmParser->getValueAsBit("ShouldEmitMatchRegisterName"))
2731 emitMatchRegisterName(Target, AsmParser, OS);
2733 OS << "#endif // GET_REGISTER_MATCHER\n\n";
2735 OS << "\n#ifdef GET_SUBTARGET_FEATURE_NAME\n";
2736 OS << "#undef GET_SUBTARGET_FEATURE_NAME\n\n";
2738 // Generate the helper function to get the names for subtarget features.
2739 emitGetSubtargetFeatureName(Info, OS);
2741 OS << "#endif // GET_SUBTARGET_FEATURE_NAME\n\n";
2743 OS << "\n#ifdef GET_MATCHER_IMPLEMENTATION\n";
2744 OS << "#undef GET_MATCHER_IMPLEMENTATION\n\n";
2746 // Generate the function that remaps for mnemonic aliases.
2747 bool HasMnemonicAliases = emitMnemonicAliases(OS, Info, Target);
2749 // Generate the convertToMCInst function to convert operands into an MCInst.
2750 // Also, generate the convertToMapAndConstraints function for MS-style inline
2751 // assembly. The latter doesn't actually generate a MCInst.
2752 emitConvertFuncs(Target, ClassName, Info.Matchables, OS);
2754 // Emit the enumeration for classes which participate in matching.
2755 emitMatchClassEnumeration(Target, Info.Classes, OS);
2757 // Emit the routine to match token strings to their match class.
2758 emitMatchTokenString(Target, Info.Classes, OS);
2760 // Emit the subclass predicate routine.
2761 emitIsSubclass(Target, Info.Classes, OS);
2763 // Emit the routine to validate an operand against a match class.
2764 emitValidateOperandClass(Info, OS);
2766 // Emit the available features compute function.
2767 emitComputeAvailableFeatures(Info, OS);
2770 StringToOffsetTable StringTable;
2772 size_t MaxNumOperands = 0;
2773 unsigned MaxMnemonicIndex = 0;
2774 bool HasDeprecation = false;
2775 for (const auto &MI : Info.Matchables) {
2776 MaxNumOperands = std::max(MaxNumOperands, MI->AsmOperands.size());
2777 HasDeprecation |= MI->HasDeprecation;
2779 // Store a pascal-style length byte in the mnemonic.
2780 std::string LenMnemonic = char(MI->Mnemonic.size()) + MI->Mnemonic.str();
2781 MaxMnemonicIndex = std::max(MaxMnemonicIndex,
2782 StringTable.GetOrAddStringOffset(LenMnemonic, false));
2785 OS << "static const char *const MnemonicTable =\n";
2786 StringTable.EmitString(OS);
2789 // Emit the static match table; unused classes get initalized to 0 which is
2790 // guaranteed to be InvalidMatchClass.
2792 // FIXME: We can reduce the size of this table very easily. First, we change
2793 // it so that store the kinds in separate bit-fields for each index, which
2794 // only needs to be the max width used for classes at that index (we also need
2795 // to reject based on this during classification). If we then make sure to
2796 // order the match kinds appropriately (putting mnemonics last), then we
2797 // should only end up using a few bits for each class, especially the ones
2798 // following the mnemonic.
2799 OS << "namespace {\n";
2800 OS << " struct MatchEntry {\n";
2801 OS << " " << getMinimalTypeForRange(MaxMnemonicIndex)
2803 OS << " uint16_t Opcode;\n";
2804 OS << " " << getMinimalTypeForRange(Info.Matchables.size())
2806 OS << " " << getMinimalRequiredFeaturesType(Info)
2807 << " RequiredFeatures;\n";
2808 OS << " " << getMinimalTypeForRange(
2809 std::distance(Info.Classes.begin(), Info.Classes.end()))
2810 << " Classes[" << MaxNumOperands << "];\n";
2811 OS << " StringRef getMnemonic() const {\n";
2812 OS << " return StringRef(MnemonicTable + Mnemonic + 1,\n";
2813 OS << " MnemonicTable[Mnemonic]);\n";
2817 OS << " // Predicate for searching for an opcode.\n";
2818 OS << " struct LessOpcode {\n";
2819 OS << " bool operator()(const MatchEntry &LHS, StringRef RHS) {\n";
2820 OS << " return LHS.getMnemonic() < RHS;\n";
2822 OS << " bool operator()(StringRef LHS, const MatchEntry &RHS) {\n";
2823 OS << " return LHS < RHS.getMnemonic();\n";
2825 OS << " bool operator()(const MatchEntry &LHS, const MatchEntry &RHS) {\n";
2826 OS << " return LHS.getMnemonic() < RHS.getMnemonic();\n";
2830 OS << "} // end anonymous namespace.\n\n";
2832 unsigned VariantCount = Target.getAsmParserVariantCount();
2833 for (unsigned VC = 0; VC != VariantCount; ++VC) {
2834 Record *AsmVariant = Target.getAsmParserVariant(VC);
2835 int AsmVariantNo = AsmVariant->getValueAsInt("Variant");
2837 OS << "static const MatchEntry MatchTable" << VC << "[] = {\n";
2839 for (const auto &MI : Info.Matchables) {
2840 if (MI->AsmVariantID != AsmVariantNo)
2843 // Store a pascal-style length byte in the mnemonic.
2844 std::string LenMnemonic = char(MI->Mnemonic.size()) + MI->Mnemonic.str();
2845 OS << " { " << StringTable.GetOrAddStringOffset(LenMnemonic, false)
2846 << " /* " << MI->Mnemonic << " */, "
2847 << Target.getName() << "::"
2848 << MI->getResultInst()->TheDef->getName() << ", "
2849 << MI->ConversionFnKind << ", ";
2851 // Write the required features mask.
2852 if (!MI->RequiredFeatures.empty()) {
2853 for (unsigned i = 0, e = MI->RequiredFeatures.size(); i != e; ++i) {
2855 OS << MI->RequiredFeatures[i]->getEnumName();
2861 for (unsigned i = 0, e = MI->AsmOperands.size(); i != e; ++i) {
2862 const MatchableInfo::AsmOperand &Op = MI->AsmOperands[i];
2865 OS << Op.Class->Name;
2873 // A method to determine if a mnemonic is in the list.
2874 OS << "bool " << Target.getName() << ClassName << "::\n"
2875 << "mnemonicIsValid(StringRef Mnemonic, unsigned VariantID) {\n";
2876 OS << " // Find the appropriate table for this asm variant.\n";
2877 OS << " const MatchEntry *Start, *End;\n";
2878 OS << " switch (VariantID) {\n";
2879 OS << " default: llvm_unreachable(\"invalid variant!\");\n";
2880 for (unsigned VC = 0; VC != VariantCount; ++VC) {
2881 Record *AsmVariant = Target.getAsmParserVariant(VC);
2882 int AsmVariantNo = AsmVariant->getValueAsInt("Variant");
2883 OS << " case " << AsmVariantNo << ": Start = std::begin(MatchTable" << VC
2884 << "); End = std::end(MatchTable" << VC << "); break;\n";
2887 OS << " // Search the table.\n";
2888 OS << " std::pair<const MatchEntry*, const MatchEntry*> MnemonicRange =\n";
2889 OS << " std::equal_range(Start, End, Mnemonic, LessOpcode());\n";
2890 OS << " return MnemonicRange.first != MnemonicRange.second;\n";
2893 // Finally, build the match function.
2894 OS << "unsigned " << Target.getName() << ClassName << "::\n"
2895 << "MatchInstructionImpl(const OperandVector &Operands,\n";
2896 OS << " MCInst &Inst, uint64_t &ErrorInfo,\n"
2897 << " bool matchingInlineAsm, unsigned VariantID) {\n";
2899 OS << " // Eliminate obvious mismatches.\n";
2900 OS << " if (Operands.size() > " << (MaxNumOperands+1) << ") {\n";
2901 OS << " ErrorInfo = " << (MaxNumOperands+1) << ";\n";
2902 OS << " return Match_InvalidOperand;\n";
2905 // Emit code to get the available features.
2906 OS << " // Get the current feature set.\n";
2907 OS << " uint64_t AvailableFeatures = getAvailableFeatures();\n\n";
2909 OS << " // Get the instruction mnemonic, which is the first token.\n";
2910 OS << " StringRef Mnemonic = ((" << Target.getName()
2911 << "Operand&)*Operands[0]).getToken();\n\n";
2913 if (HasMnemonicAliases) {
2914 OS << " // Process all MnemonicAliases to remap the mnemonic.\n";
2915 OS << " applyMnemonicAliases(Mnemonic, AvailableFeatures, VariantID);\n\n";
2918 // Emit code to compute the class list for this operand vector.
2919 OS << " // Some state to try to produce better error messages.\n";
2920 OS << " bool HadMatchOtherThanFeatures = false;\n";
2921 OS << " bool HadMatchOtherThanPredicate = false;\n";
2922 OS << " unsigned RetCode = Match_InvalidOperand;\n";
2923 OS << " uint64_t MissingFeatures = ~0ULL;\n";
2924 OS << " // Set ErrorInfo to the operand that mismatches if it is\n";
2925 OS << " // wrong for all instances of the instruction.\n";
2926 OS << " ErrorInfo = ~0ULL;\n";
2928 // Emit code to search the table.
2929 OS << " // Find the appropriate table for this asm variant.\n";
2930 OS << " const MatchEntry *Start, *End;\n";
2931 OS << " switch (VariantID) {\n";
2932 OS << " default: llvm_unreachable(\"invalid variant!\");\n";
2933 for (unsigned VC = 0; VC != VariantCount; ++VC) {
2934 Record *AsmVariant = Target.getAsmParserVariant(VC);
2935 int AsmVariantNo = AsmVariant->getValueAsInt("Variant");
2936 OS << " case " << AsmVariantNo << ": Start = std::begin(MatchTable" << VC
2937 << "); End = std::end(MatchTable" << VC << "); break;\n";
2940 OS << " // Search the table.\n";
2941 OS << " std::pair<const MatchEntry*, const MatchEntry*> MnemonicRange =\n";
2942 OS << " std::equal_range(Start, End, Mnemonic, LessOpcode());\n\n";
2944 OS << " // Return a more specific error code if no mnemonics match.\n";
2945 OS << " if (MnemonicRange.first == MnemonicRange.second)\n";
2946 OS << " return Match_MnemonicFail;\n\n";
2948 OS << " for (const MatchEntry *it = MnemonicRange.first, "
2949 << "*ie = MnemonicRange.second;\n";
2950 OS << " it != ie; ++it) {\n";
2952 OS << " // equal_range guarantees that instruction mnemonic matches.\n";
2953 OS << " assert(Mnemonic == it->getMnemonic());\n";
2955 // Emit check that the subclasses match.
2956 OS << " bool OperandsValid = true;\n";
2957 OS << " for (unsigned i = 0; i != " << MaxNumOperands << "; ++i) {\n";
2958 OS << " if (i + 1 >= Operands.size()) {\n";
2959 OS << " OperandsValid = (it->Classes[i] == " <<"InvalidMatchClass);\n";
2960 OS << " if (!OperandsValid) ErrorInfo = i + 1;\n";
2963 OS << " unsigned Diag = validateOperandClass(*Operands[i+1],\n";
2965 OS << "(MatchClassKind)it->Classes[i]);\n";
2966 OS << " if (Diag == Match_Success)\n";
2967 OS << " continue;\n";
2968 OS << " // If the generic handler indicates an invalid operand\n";
2969 OS << " // failure, check for a special case.\n";
2970 OS << " if (Diag == Match_InvalidOperand) {\n";
2971 OS << " Diag = validateTargetOperandClass(*Operands[i+1],\n";
2973 OS << "(MatchClassKind)it->Classes[i]);\n";
2974 OS << " if (Diag == Match_Success)\n";
2975 OS << " continue;\n";
2977 OS << " // If this operand is broken for all of the instances of this\n";
2978 OS << " // mnemonic, keep track of it so we can report loc info.\n";
2979 OS << " // If we already had a match that only failed due to a\n";
2980 OS << " // target predicate, that diagnostic is preferred.\n";
2981 OS << " if (!HadMatchOtherThanPredicate &&\n";
2982 OS << " (it == MnemonicRange.first || ErrorInfo <= i+1)) {\n";
2983 OS << " ErrorInfo = i+1;\n";
2984 OS << " // InvalidOperand is the default. Prefer specificity.\n";
2985 OS << " if (Diag != Match_InvalidOperand)\n";
2986 OS << " RetCode = Diag;\n";
2988 OS << " // Otherwise, just reject this instance of the mnemonic.\n";
2989 OS << " OperandsValid = false;\n";
2993 OS << " if (!OperandsValid) continue;\n";
2995 // Emit check that the required features are available.
2996 OS << " if ((AvailableFeatures & it->RequiredFeatures) "
2997 << "!= it->RequiredFeatures) {\n";
2998 OS << " HadMatchOtherThanFeatures = true;\n";
2999 OS << " uint64_t NewMissingFeatures = it->RequiredFeatures & "
3000 "~AvailableFeatures;\n";
3001 OS << " if (countPopulation(NewMissingFeatures) <=\n"
3002 " countPopulation(MissingFeatures))\n";
3003 OS << " MissingFeatures = NewMissingFeatures;\n";
3004 OS << " continue;\n";
3007 OS << " Inst.clear();\n\n";
3008 OS << " if (matchingInlineAsm) {\n";
3009 OS << " Inst.setOpcode(it->Opcode);\n";
3010 OS << " convertToMapAndConstraints(it->ConvertFn, Operands);\n";
3011 OS << " return Match_Success;\n";
3013 OS << " // We have selected a definite instruction, convert the parsed\n"
3014 << " // operands into the appropriate MCInst.\n";
3015 OS << " convertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands);\n";
3018 // Verify the instruction with the target-specific match predicate function.
3019 OS << " // We have a potential match. Check the target predicate to\n"
3020 << " // handle any context sensitive constraints.\n"
3021 << " unsigned MatchResult;\n"
3022 << " if ((MatchResult = checkTargetMatchPredicate(Inst)) !="
3023 << " Match_Success) {\n"
3024 << " Inst.clear();\n"
3025 << " RetCode = MatchResult;\n"
3026 << " HadMatchOtherThanPredicate = true;\n"
3030 // Call the post-processing function, if used.
3031 std::string InsnCleanupFn =
3032 AsmParser->getValueAsString("AsmParserInstCleanup");
3033 if (!InsnCleanupFn.empty())
3034 OS << " " << InsnCleanupFn << "(Inst);\n";
3036 if (HasDeprecation) {
3037 OS << " std::string Info;\n";
3038 OS << " if (MII.get(Inst.getOpcode()).getDeprecatedInfo(Inst, STI, Info)) {\n";
3039 OS << " SMLoc Loc = ((" << Target.getName()
3040 << "Operand&)*Operands[0]).getStartLoc();\n";
3041 OS << " getParser().Warning(Loc, Info, None);\n";
3045 OS << " return Match_Success;\n";
3048 OS << " // Okay, we had no match. Try to return a useful error code.\n";
3049 OS << " if (HadMatchOtherThanPredicate || !HadMatchOtherThanFeatures)\n";
3050 OS << " return RetCode;\n\n";
3051 OS << " // Missing feature matches return which features were missing\n";
3052 OS << " ErrorInfo = MissingFeatures;\n";
3053 OS << " return Match_MissingFeature;\n";
3056 if (!Info.OperandMatchInfo.empty())
3057 emitCustomOperandParsing(OS, Target, Info, ClassName, StringTable,
3060 OS << "#endif // GET_MATCHER_IMPLEMENTATION\n\n";
3065 void EmitAsmMatcher(RecordKeeper &RK, raw_ostream &OS) {
3066 emitSourceFileHeader("Assembly Matcher Source Fragment", OS);
3067 AsmMatcherEmitter(RK).run(OS);
3070 } // End llvm namespace