1 ; RUN: opt -S -instcombine < %s | FileCheck %s
3 define <4 x i32> @mulByZero(<4 x i16> %x) nounwind readnone ssp {
5 %a = tail call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16> %x, <4 x i16> zeroinitializer) nounwind
8 ; CHECK-NEXT: ret <4 x i32> zeroinitializer
11 define <4 x i32> @mulByOne(<4 x i16> %x) nounwind readnone ssp {
13 %a = tail call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16> %x, <4 x i16> <i16 1, i16 1, i16 1, i16 1>) nounwind
16 ; CHECK-NEXT: %a = sext <4 x i16> %x to <4 x i32>
17 ; CHECK-NEXT: ret <4 x i32> %a
20 define <4 x i32> @constantMul() nounwind readnone ssp {
22 %a = tail call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16> <i16 3, i16 3, i16 3, i16 3>, <4 x i16> <i16 2, i16 2, i16 2, i16 2>) nounwind
25 ; CHECK-NEXT: ret <4 x i32> <i32 6, i32 6, i32 6, i32 6>
28 define <4 x i32> @constantMulS() nounwind readnone ssp {
30 %b = tail call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16> <i16 -1, i16 -1, i16 -1, i16 -1>, <4 x i16> <i16 1, i16 1, i16 1, i16 1>) nounwind
33 ; CHECK-NEXT: ret <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>
36 define <4 x i32> @constantMulU() nounwind readnone ssp {
38 %b = tail call <4 x i32> @llvm.arm.neon.vmullu.v4i32(<4 x i16> <i16 -1, i16 -1, i16 -1, i16 -1>, <4 x i16> <i16 1, i16 1, i16 1, i16 1>) nounwind
41 ; CHECK-NEXT: ret <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535>
44 define <4 x i32> @complex1(<4 x i16> %x) nounwind readnone ssp {
46 %a = tail call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16> <i16 2, i16 2, i16 2, i16 2>, <4 x i16> %x) nounwind
47 %b = add <4 x i32> zeroinitializer, %a
50 ; CHECK-NEXT: %a = tail call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16> <i16 2, i16 2, i16 2, i16 2>, <4 x i16> %x) [[NUW:#[0-9]+]]
51 ; CHECK-NEXT: ret <4 x i32> %a
54 define <4 x i32> @complex2(<4 x i32> %x) nounwind readnone ssp {
56 %a = tail call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16> <i16 3, i16 3, i16 3, i16 3>, <4 x i16> <i16 2, i16 2, i16 2, i16 2>) nounwind
57 %b = add <4 x i32> %x, %a
60 ; CHECK-NEXT: %b = add <4 x i32> %x, <i32 6, i32 6, i32 6, i32 6>
61 ; CHECK-NEXT: ret <4 x i32> %b
64 declare <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16>, <4 x i16>) nounwind readnone
65 declare <4 x i32> @llvm.arm.neon.vmullu.v4i32(<4 x i16>, <4 x i16>) nounwind readnone
67 ; ARM64 variants - <rdar://problem/12349617>
69 define <4 x i32> @mulByZeroARM64(<4 x i16> %x) nounwind readnone ssp {
71 %a = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %x, <4 x i16> zeroinitializer) nounwind
74 ; CHECK-NEXT: ret <4 x i32> zeroinitializer
77 define <4 x i32> @mulByOneARM64(<4 x i16> %x) nounwind readnone ssp {
79 %a = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %x, <4 x i16> <i16 1, i16 1, i16 1, i16 1>) nounwind
82 ; CHECK-NEXT: %a = sext <4 x i16> %x to <4 x i32>
83 ; CHECK-NEXT: ret <4 x i32> %a
86 define <4 x i32> @constantMulARM64() nounwind readnone ssp {
88 %a = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> <i16 3, i16 3, i16 3, i16 3>, <4 x i16> <i16 2, i16 2, i16 2, i16 2>) nounwind
91 ; CHECK-NEXT: ret <4 x i32> <i32 6, i32 6, i32 6, i32 6>
94 define <4 x i32> @constantMulSARM64() nounwind readnone ssp {
96 %b = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> <i16 -1, i16 -1, i16 -1, i16 -1>, <4 x i16> <i16 1, i16 1, i16 1, i16 1>) nounwind
99 ; CHECK-NEXT: ret <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>
102 define <4 x i32> @constantMulUARM64() nounwind readnone ssp {
104 %b = tail call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> <i16 -1, i16 -1, i16 -1, i16 -1>, <4 x i16> <i16 1, i16 1, i16 1, i16 1>) nounwind
107 ; CHECK-NEXT: ret <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535>
110 define <4 x i32> @complex1ARM64(<4 x i16> %x) nounwind readnone ssp {
112 %a = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> <i16 2, i16 2, i16 2, i16 2>, <4 x i16> %x) nounwind
113 %b = add <4 x i32> zeroinitializer, %a
116 ; CHECK-NEXT: %a = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> <i16 2, i16 2, i16 2, i16 2>, <4 x i16> %x) [[NUW:#[0-9]+]]
117 ; CHECK-NEXT: ret <4 x i32> %a
120 define <4 x i32> @complex2ARM64(<4 x i32> %x) nounwind readnone ssp {
122 %a = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> <i16 3, i16 3, i16 3, i16 3>, <4 x i16> <i16 2, i16 2, i16 2, i16 2>) nounwind
123 %b = add <4 x i32> %x, %a
126 ; CHECK-NEXT: %b = add <4 x i32> %x, <i32 6, i32 6, i32 6, i32 6>
127 ; CHECK-NEXT: ret <4 x i32> %b
130 declare <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16>, <4 x i16>) nounwind readnone
131 declare <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16>, <4 x i16>) nounwind readnone
133 ; CHECK: attributes #0 = { nounwind readnone ssp }
134 ; CHECK: attributes #1 = { nounwind readnone }
135 ; CHECK: attributes [[NUW]] = { nounwind }