test/TableGen/TargetInstrSpec.td

   1 // RUN: llvm-tblgen %s | FileCheck %s
   2
   3 // CHECK: [(set VR128:$dst, (int_x86_sse2_add_pd VR128:$src1, VR128:$src2))]
   4 // CHECK-NOT: [(set VR128:$dst, (int_x86_sse2_add_pd VR128:$src1, VR128:$src2))]
   5
   6 // CHECK: [(set VR128:$dst, (int_x86_sse2_add_ps VR128:$src1, VR128:$src2))]
   7 // CHECK-NOT: [(set VR128:$dst, (int_x86_sse2_add_ps VR128:$src1, VR128:$src2))]
   8
   9 class ValueType<int size, int value> {
  10   int Size = size;
  11   int Value = value;
  12 }
  13
  14 def v2i64  : ValueType<128, 22>;   //  2 x i64 vector value
  15 def v2f64  : ValueType<128, 28>;   //  2 x f64 vector value
  16
  17 class Intrinsic<string name> {
  18   string Name = name;
  19 }
  20
  21 class Inst<bits<8> opcode, dag oopnds, dag iopnds, string asmstr,
  22            list<dag> pattern> {
  23   bits<8> Opcode = opcode;
  24   dag OutOperands = oopnds;
  25   dag InOperands = iopnds;
  26   string AssemblyString = asmstr;
  27   list<dag> Pattern = pattern;
  28 }
  29
  30 def ops;
  31 def outs;
  32 def ins;
  33
  34 def set;
  35
  36 // Define registers
  37 class Register<string n> {
  38   string Name = n;
  39 }
  40
  41 class RegisterClass<list<ValueType> regTypes, list<Register> regList> {
  42   list<ValueType> RegTypes = regTypes;
  43   list<Register> MemberList = regList;
  44 }
  45
  46 def XMM0: Register<"xmm0">;
  47 def XMM1: Register<"xmm1">;
  48 def XMM2: Register<"xmm2">;
  49 def XMM3: Register<"xmm3">;
  50 def XMM4: Register<"xmm4">;
  51 def XMM5: Register<"xmm5">;
  52 def XMM6: Register<"xmm6">;
  53 def XMM7: Register<"xmm7">;
  54 def XMM8:  Register<"xmm8">;
  55 def XMM9:  Register<"xmm9">;
  56 def XMM10: Register<"xmm10">;
  57 def XMM11: Register<"xmm11">;
  58 def XMM12: Register<"xmm12">;
  59 def XMM13: Register<"xmm13">;
  60 def XMM14: Register<"xmm14">;
  61 def XMM15: Register<"xmm15">;
  62
  63 def VR128 : RegisterClass<[v2i64, v2f64],
  64                           [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
  65                            XMM8, XMM9, XMM10, XMM11,
  66                            XMM12, XMM13, XMM14, XMM15]>;
  67
  68 // Dummy for subst
  69 def REGCLASS : RegisterClass<[], []>;
  70
  71 class decls {
  72   // Dummy for foreach
  73   dag pattern;
  74   int operand;
  75 }
  76
  77 def Decls : decls;
  78
  79 // Define intrinsics
  80 def int_x86_sse2_add_ps : Intrinsic<"addps">;
  81 def int_x86_sse2_add_pd : Intrinsic<"addpd">;
  82 def INTRINSIC : Intrinsic<"Dummy">;
  83
  84 multiclass arith<bits<8> opcode, string asmstr, string intr, list<dag> patterns> {
  85   def PS : Inst<opcode, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
  86                  !strconcat(asmstr, "\t$dst, $src1, $src2"),
  87                  !foreach(Decls.pattern, patterns,
  88                           !foreach(Decls.operand, Decls.pattern,
  89                                    !subst(INTRINSIC, !cast<Intrinsic>(!subst("SUFFIX", "_ps", intr)),
  90                                           !subst(REGCLASS, VR128, Decls.operand))))>;
  91
  92   def PD : Inst<opcode, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
  93                  !strconcat(asmstr, "\t$dst, $src1, $src2"),
  94                  !foreach(Decls.pattern, patterns,
  95                           !foreach(Decls.operand, Decls.pattern,
  96                                    !subst(INTRINSIC, !cast<Intrinsic>(!subst("SUFFIX", "_pd", intr)),
  97                                           !subst(REGCLASS, VR128, Decls.operand))))>;
  98 }
  99
 100 defm ADD : arith<0x58, "add", "int_x86_sse2_addSUFFIX",
 101                  [(set REGCLASS:$dst, (INTRINSIC REGCLASS:$src1, REGCLASS:$src2))]>;
 102