Add forgotten test case.
[oota-llvm.git] / test / TableGen / TargetInstrSpec.td
1 // RUN: tblgen %s | grep {\\\[(set VR128:\$dst, (int_x86_sse2_add_pd VR128:\$src1, VR128:\$src2))\\\]} | count 1
2 // RUN: tblgen %s | grep {\\\[(set VR128:\$dst, (int_x86_sse2_add_ps VR128:\$src1, VR128:\$src2))\\\]} | count 1
3 // XFAIL: vg_leak
4
5 class ValueType<int size, int value> {
6   int Size = size;
7   int Value = value;
8 }
9
10 def v2i64  : ValueType<128, 22>;   //  2 x i64 vector value
11 def v2f64  : ValueType<128, 28>;   //  2 x f64 vector value
12
13 class Intrinsic<string name> {
14   string Name = name;
15 }
16
17 class Inst<bits<8> opcode, dag oopnds, dag iopnds, string asmstr, 
18            list<dag> pattern> {
19   bits<8> Opcode = opcode;
20   dag OutOperands = oopnds;
21   dag InOperands = iopnds;
22   string AssemblyString = asmstr;
23   list<dag> Pattern = pattern;
24 }
25
26 def ops;
27 def outs;
28 def ins;
29
30 def set;
31
32 // Define registers
33 class Register<string n> {
34   string Name = n;
35 }
36
37 class RegisterClass<list<ValueType> regTypes, list<Register> regList> {
38   list<ValueType> RegTypes = regTypes;
39   list<Register> MemberList = regList;
40 }
41
42 def XMM0: Register<"xmm0">;
43 def XMM1: Register<"xmm1">;
44 def XMM2: Register<"xmm2">;
45 def XMM3: Register<"xmm3">;
46 def XMM4: Register<"xmm4">;
47 def XMM5: Register<"xmm5">;
48 def XMM6: Register<"xmm6">;
49 def XMM7: Register<"xmm7">;
50 def XMM8:  Register<"xmm8">;
51 def XMM9:  Register<"xmm9">;
52 def XMM10: Register<"xmm10">;
53 def XMM11: Register<"xmm11">;
54 def XMM12: Register<"xmm12">;
55 def XMM13: Register<"xmm13">;
56 def XMM14: Register<"xmm14">;
57 def XMM15: Register<"xmm15">;
58
59 def VR128 : RegisterClass<[v2i64, v2f64],
60                           [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
61                            XMM8, XMM9, XMM10, XMM11,
62                            XMM12, XMM13, XMM14, XMM15]>;
63
64 // Dummy for subst
65 def REGCLASS : RegisterClass<[], []>;
66
67 class decls {
68   // Dummy for foreach
69   dag pattern;
70   int operand;
71 }
72
73 def Decls : decls;
74
75 // Define intrinsics
76 def int_x86_sse2_add_ps : Intrinsic<"addps">;
77 def int_x86_sse2_add_pd : Intrinsic<"addpd">;
78 def INTRINSIC : Intrinsic<"Dummy">;
79
80 multiclass arith<bits<8> opcode, string asmstr, string intr, list<dag> patterns> {
81   def PS : Inst<opcode, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
82                  !strconcat(asmstr, "\t$dst, $src1, $src2"),
83                  !foreach(Decls.pattern, patterns, 
84                           !foreach(Decls.operand, Decls.pattern, 
85                                    !subst(INTRINSIC, !cast<Intrinsic>(!subst("SUFFIX", "_ps", intr)), 
86                                           !subst(REGCLASS, VR128, Decls.operand))))>;
87
88   def PD : Inst<opcode, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
89                  !strconcat(asmstr, "\t$dst, $src1, $src2"),
90                  !foreach(Decls.pattern, patterns, 
91                           !foreach(Decls.operand, Decls.pattern, 
92                                    !subst(INTRINSIC, !cast<Intrinsic>(!subst("SUFFIX", "_pd", intr)), 
93                                           !subst(REGCLASS, VR128, Decls.operand))))>;
94 }
95
96 defm ADD : arith<0x58, "add", "int_x86_sse2_addSUFFIX",
97                  [(set REGCLASS:$dst, (INTRINSIC REGCLASS:$src1, REGCLASS:$src2))]>;
98