[mips] [IAS] Add support for the DLA pseudo-instruction and fix problems with DLI
[oota-llvm.git] / test / MC / Mips / mips32r6 / relocations.s
1 # RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 \
2 # RUN:   | FileCheck %s -check-prefix=CHECK-FIXUP
3 # RUN: llvm-mc %s -filetype=obj -triple=mips-unknown-linux -mcpu=mips32r6 \
4 # RUN:   | llvm-readobj -r | FileCheck %s -check-prefix=CHECK-ELF
5 #------------------------------------------------------------------------------
6 # Check that the assembler can handle the documented syntax for fixups.
7 #------------------------------------------------------------------------------
8 # CHECK-FIXUP: addiupc $2, bar  # encoding: [0xec,0b01000AAA,A,A]
9 # CHECK-FIXUP:                  # fixup A - offset: 0,
10 # CHECK-FIXUP:                    value: bar, kind: fixup_MIPS_PC19_S2
11 # CHECK-FIXUP: beqc $5, $6, bar # encoding: [0x20,0xa6,A,A]
12 # CHECK-FIXUP:                  #   fixup A - offset: 0,
13 # CHECK-FIXUP:                      value: bar-4, kind: fixup_Mips_PC16
14 # CHECK-FIXUP: bnec $5, $6, bar # encoding: [0x60,0xa6,A,A]
15 # CHECK-FIXUP:                  #   fixup A - offset: 0,
16 # CHECK-FIXUP:                      value: bar-4, kind: fixup_Mips_PC16
17 # CHECK-FIXUP: beqzc $9, bar    # encoding: [0xd9,0b001AAAAA,A,A]
18 # CHECK-FIXUP:                  #   fixup A - offset: 0,
19 # CHECK-FIXUP:                      value: bar-4, kind: fixup_MIPS_PC21_S2
20 # CHECK-FIXUP: bnezc $9, bar    # encoding: [0xf9,0b001AAAAA,A,A]
21 # CHECK-FIXUP:                  #   fixup A - offset: 0,
22 # CHECK-FIXUP:                      value: bar-4, kind: fixup_MIPS_PC21_S2
23 # CHECK-FIXUP: balc  bar        # encoding: [0b111010AA,A,A,A]
24 # CHECK-FIXUP:                  #   fixup A - offset: 0,
25 # CHECK-FIXUP:                      value: bar-4, kind: fixup_MIPS_PC26_S2
26 # CHECK-FIXUP: bc    bar        # encoding: [0b110010AA,A,A,A]
27 # CHECK-FIXUP:                  #   fixup A - offset: 0,
28 # CHECK-FIXUP:                      value: bar-4, kind: fixup_MIPS_PC26_S2
29 # CHECK-FIXUP: aluipc $2, %pcrel_hi(bar)    # encoding: [0xec,0x5f,A,A]
30 # CHECK-FIXUP:                              #   fixup A - offset: 0,
31 # CHECK-FIXUP:                                  value: bar@PCREL_HI16,
32 # CHECK-FIXUP:                                  kind: fixup_MIPS_PCHI16
33 # CHECK-FIXUP: addiu $2, $2, %pcrel_lo(bar) # encoding: [0x24,0x42,A,A]
34 # CHECK-FIXUP:                              #   fixup A - offset: 0,
35 # CHECK-FIXUP:                                  value: bar@PCREL_LO16,
36 # CHECK-FIXUP:                                  kind: fixup_MIPS_PCLO16
37 # CHECK-FIXUP: lwpc    $2, bar  # encoding: [0xec,0b01001AAA,A,A]
38 # CHECK-FIXUP:                  #   fixup A - offset: 0,
39 # CHECK-FIXUP:                      value: bar, kind: fixup_MIPS_PC19_S2
40 # CHECK-FIXUP: lwupc   $2, bar  # encoding: [0xec,0b01010AAA,A,A]
41 # CHECK-FIXUP:                  #   fixup A - offset: 0,
42 # CHECK-FIXUP:                      value: bar, kind: fixup_MIPS_PC19_S2
43 #------------------------------------------------------------------------------
44 # Check that the appropriate relocations were created.
45 #------------------------------------------------------------------------------
46 # CHECK-ELF: Relocations [
47 # CHECK-ELF:     0x0 R_MIPS_PC19_S2 bar 0x0
48 # CHECK-ELF:     0x4 R_MIPS_PC16 bar 0x0
49 # CHECK-ELF:     0x8 R_MIPS_PC16 bar 0x0
50 # CHECK-ELF:     0xC R_MIPS_PC21_S2 bar 0x0
51 # CHECK-ELF:     0x10 R_MIPS_PC21_S2 bar 0x0
52 # CHECK-ELF:     0x14 R_MIPS_PC26_S2 bar 0x0
53 # CHECK-ELF:     0x18 R_MIPS_PC26_S2 bar 0x0
54 # CHECK-ELF:     0x1C R_MIPS_PCHI16 bar 0x0
55 # CHECK-ELF:     0x20 R_MIPS_PCLO16 bar 0x0
56 # CHECK-ELF:     0x24 R_MIPS_PC19_S2 bar 0x0
57 # CHECK-ELF:     0x28 R_MIPS_PC19_S2 bar 0x0
58 # CHECK-ELF: ]
59
60   addiupc   $2,bar
61   beqc  $5, $6, bar
62   bnec  $5, $6, bar
63   beqzc $9, bar
64   bnezc $9, bar
65   balc  bar
66   bc    bar
67   aluipc $2, %pcrel_hi(bar)
68   addiu  $2, $2, %pcrel_lo(bar)
69   lwpc      $2,bar
70   lwupc     $2,bar