1 # VMOV/VDUP between scalar and core registers with invalid predicate bits (pred != 0b1110)
4 # RUN: echo "0x00 0xde 0x10 0x0b" | llvm-mc -triple thumbv7 -disassemble 2>&1 | FileCheck %s
7 # RUN: echo "0xff 0xde 0xf0 0xfb" | llvm-mc -triple thumbv7 -disassemble 2>&1 | FileCheck %s
9 # CHECK: invalid instruction encoding