test/MC/ARM/thumb2-narrow-dp.ll

   1 // RUN: llvm-mc -triple thumbv7 -show-encoding < %s | FileCheck %s
   2
   3 // Test each of the Thumb1 data-processing instructions
   4 // The assembly syntax for these instructions allows an optional Rd register
   5 //   OP{S}{<c>}{<q>}  {<Rd>,} <Rn>, <Rm>
   6 // Assemblers should chose the narrow thumb encoding when possible, i.e.
   7 //   - Rd == Rn
   8 //   - Rd, Rn and Rm are < r8
   9 // In addition, some operations are commutative, allowing the transormation
  10 // when:
  11 //   - Rd == Rn || Rd == Rm
  12 //   - Rd, Rn and Rm are < r8
  13
  14 // AND (commutative)
  15     ANDS     r0, r2, r1          // Must be wide - 3 distinct registers
  16     ANDS     r2, r2, r1          // Should choose narrow
  17     ANDS     r2, r1, r2          // Should choose narrow - commutative
  18     ANDS.W   r0, r0, r1          // Explicitly wide
  19     ANDS.W   r3, r1, r3
  20     AND      r0, r1, r0          // Must use wide encoding as not flag-setting
  21     ANDS     r7, r7, r1          // Should use narrow
  22     ANDS     r7, r1, r7          // Commutative
  23     ANDS     r8, r1, r8          // high registers so must use wide encoding
  24     ANDS     r8, r8, r1
  25     ANDS     r0, r8, r0
  26     ANDS     r1, r1, r8
  27     ANDS     r2, r2, r1, lsl #1  // Must use wide - shifted register
  28     ANDS     r0, r1, r0, lsr #1
  29 // CHECK: ands.w  r0, r2, r1              @ encoding: [0x12,0xea,0x01,0x00]
  30 // CHECK: ands    r2, r1                  @ encoding: [0x0a,0x40]
  31 // CHECK: ands    r2, r1                  @ encoding: [0x0a,0x40]
  32 // CHECK: ands.w  r0, r0, r1              @ encoding: [0x10,0xea,0x01,0x00]
  33 // CHECK: ands.w  r3, r1, r3              @ encoding: [0x11,0xea,0x03,0x03]
  34 // CHECK: and.w   r0, r1, r0              @ encoding: [0x01,0xea,0x00,0x00]
  35 // CHECK: ands    r7, r1                  @ encoding: [0x0f,0x40]
  36 // CHECK: ands    r7, r1                  @ encoding: [0x0f,0x40]
  37 // CHECK: ands.w  r8, r1, r8              @ encoding: [0x11,0xea,0x08,0x08]
  38 // CHECK: ands.w  r8, r8, r1              @ encoding: [0x18,0xea,0x01,0x08]
  39 // CHECK: ands.w  r0, r8, r0              @ encoding: [0x18,0xea,0x00,0x00]
  40 // CHECK: ands.w  r1, r1, r8              @ encoding: [0x11,0xea,0x08,0x01]
  41 // CHECK: ands.w  r2, r2, r1, lsl #1      @ encoding: [0x12,0xea,0x41,0x02]
  42 // CHECK: ands.w  r0, r1, r0, lsr #1      @ encoding: [0x11,0xea,0x50,0x00]
  43
  44     IT EQ
  45     ANDEQ    r0, r2, r1          // Must be wide - 3 distinct registers
  46     IT EQ
  47     ANDEQ    r3, r3, r1          // Should choose narrow
  48     IT EQ
  49     ANDEQ    r3, r1, r3          // Should choose narrow - commutative
  50     IT EQ
  51     ANDEQ.W  r0, r0, r1          // Explicitly wide
  52     IT EQ
  53     ANDEQ.W  r2, r1, r2
  54     IT EQ
  55     ANDSEQ   r0, r1, r0          // Must use wide encoding as flag-setting
  56     IT EQ
  57     ANDEQ    r7, r7, r1          // Should use narrow
  58     IT EQ
  59     ANDEQ    r7, r1, r7          // Commutative
  60     IT EQ
  61     ANDEQ    r8, r1, r8          // high registers so must use wide encoding
  62     IT EQ
  63     ANDEQ    r8, r8, r1
  64     IT EQ
  65     ANDEQ    r4, r8, r4
  66     IT EQ
  67     ANDEQ    r4, r4, r8
  68     IT EQ
  69     ANDEQ    r0, r0, r1, lsl #1  // Must use wide - shifted register
  70     IT EQ
  71     ANDEQ    r5, r1, r5, lsr #1
  72 // CHECK: it eq                           @ encoding: [0x08,0xbf]
  73 // CHECK: andeq.w  r0, r2, r1             @ encoding: [0x02,0xea,0x01,0x00]
  74 // CHECK: it eq                           @ encoding: [0x08,0xbf]
  75 // CHECK: andeq    r3, r1                 @ encoding: [0x0b,0x40]
  76 // CHECK: it eq                           @ encoding: [0x08,0xbf]
  77 // CHECK: andeq    r3, r1                 @ encoding: [0x0b,0x40]
  78 // CHECK: it eq                           @ encoding: [0x08,0xbf]
  79 // CHECK: andeq.w  r0, r0, r1             @ encoding: [0x00,0xea,0x01,0x00]
  80 // CHECK: it eq                           @ encoding: [0x08,0xbf]
  81 // CHECK: andeq.w  r2, r1, r2             @ encoding: [0x01,0xea,0x02,0x02]
  82 // CHECK: it eq                           @ encoding: [0x08,0xbf]
  83 // CHECK: andseq.w r0, r1, r0             @ encoding: [0x11,0xea,0x00,0x00]
  84 // CHECK: it eq                           @ encoding: [0x08,0xbf]
  85 // CHECK: andeq    r7, r1                 @ encoding: [0x0f,0x40]
  86 // CHECK: it eq                           @ encoding: [0x08,0xbf]
  87 // CHECK: andeq    r7, r1                 @ encoding: [0x0f,0x40]
  88 // CHECK: it eq                           @ encoding: [0x08,0xbf]
  89 // CHECK: andeq.w  r8, r1, r8             @ encoding: [0x01,0xea,0x08,0x08]
  90 // CHECK: it eq                           @ encoding: [0x08,0xbf]
  91 // CHECK: andeq.w  r8, r8, r1             @ encoding: [0x08,0xea,0x01,0x08]
  92 // CHECK: it eq                           @ encoding: [0x08,0xbf]
  93 // CHECK: andeq.w  r4, r8, r4             @ encoding: [0x08,0xea,0x04,0x04]
  94 // CHECK: it eq                           @ encoding: [0x08,0xbf]
  95 // CHECK: andeq.w  r4, r4, r8             @ encoding: [0x04,0xea,0x08,0x04]
  96 // CHECK: it eq                           @ encoding: [0x08,0xbf]
  97 // CHECK: andeq.w  r0, r0, r1, lsl #1     @ encoding: [0x00,0xea,0x41,0x00]
  98 // CHECK: it eq                           @ encoding: [0x08,0xbf]
  99 // CHECK: andeq.w  r5, r1, r5, lsr #1     @ encoding: [0x01,0xea,0x55,0x05]
 100
 101 // EOR (commutative)
 102     EORS     r0, r2, r1          // Must be wide - 3 distinct registers
 103     EORS     r5, r5, r1          // Should choose narrow
 104     EORS     r5, r1, r5          // Should choose narrow - commutative
 105     EORS.W   r0, r0, r1          // Explicitly wide
 106     EORS.W   r2, r1, r2
 107     EOR      r1, r1, r1          // Must use wide encoding as not flag-setting
 108     EORS     r7, r7, r1          // Should use narrow
 109     EORS     r7, r1, r7          // Commutative
 110     EORS     r8, r1, r8          // high registers so must use wide encoding
 111     EORS     r8, r8, r1
 112     EORS     r6, r8, r6
 113     EORS     r0, r0, r8
 114     EORS     r2, r2, r1, lsl #1  // Must use wide - shifted register
 115     EORS     r0, r1, r0, lsr #1
 116 // CHECK: eors.w  r0, r2, r1              @ encoding: [0x92,0xea,0x01,0x00]
 117 // CHECK: eors    r5, r1                  @ encoding: [0x4d,0x40]
 118 // CHECK: eors    r5, r1                  @ encoding: [0x4d,0x40]
 119 // CHECK: eors.w  r0, r0, r1              @ encoding: [0x90,0xea,0x01,0x00]
 120 // CHECK: eors.w  r2, r1, r2              @ encoding: [0x91,0xea,0x02,0x02]
 121 // CHECK: eor.w   r1, r1, r1              @ encoding: [0x81,0xea,0x01,0x01]
 122 // CHECK: eors    r7, r1                  @ encoding: [0x4f,0x40]
 123 // CHECK: eors    r7, r1                  @ encoding: [0x4f,0x40]
 124 // CHECK: eors.w  r8, r1, r8              @ encoding: [0x91,0xea,0x08,0x08]
 125 // CHECK: eors.w  r8, r8, r1              @ encoding: [0x98,0xea,0x01,0x08]
 126 // CHECK: eors.w  r6, r8, r6              @ encoding: [0x98,0xea,0x06,0x06]
 127 // CHECK: eors.w  r0, r0, r8              @ encoding: [0x90,0xea,0x08,0x00]
 128 // CHECK: eors.w  r2, r2, r1, lsl #1      @ encoding: [0x92,0xea,0x41,0x02]
 129 // CHECK: eors.w  r0, r1, r0, lsr #1      @ encoding: [0x91,0xea,0x50,0x00]
 130
 131     IT EQ
 132     EOREQ    r3, r2, r1          // Must be wide - 3 distinct registers
 133     IT EQ
 134     EOREQ    r0, r0, r1          // Should choose narrow
 135     IT EQ
 136     EOREQ    r2, r1, r2          // Should choose narrow - commutative
 137     IT EQ
 138     EOREQ.W  r3, r3, r1          // Explicitly wide
 139     IT EQ
 140     EOREQ.W  r0, r1, r0
 141     IT EQ
 142     EORSEQ   r1, r1, r1          // Must use wide encoding as flag-setting
 143     IT EQ
 144     EOREQ    r7, r7, r1          // Should use narrow
 145     IT EQ
 146     EOREQ    r7, r1, r7          // Commutative
 147     IT EQ
 148     EOREQ    r8, r1, r8          // high registers so must use wide encoding
 149     IT EQ
 150     EOREQ    r8, r8, r1
 151     IT EQ
 152     EOREQ    r0, r8, r0
 153     IT EQ
 154     EOREQ    r3, r3, r8
 155     IT EQ
 156     EOREQ    r4, r4, r1, lsl #1  // Must use wide - shifted register
 157     IT EQ
 158     EOREQ    r0, r1, r0, lsr #1
 159 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 160 // CHECK: eoreq.w  r3, r2, r1             @ encoding: [0x82,0xea,0x01,0x03]
 161 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 162 // CHECK: eoreq    r0, r1                 @ encoding: [0x48,0x40]
 163 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 164 // CHECK: eoreq    r2, r1                 @ encoding: [0x4a,0x40]
 165 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 166 // CHECK: eoreq.w  r3, r3, r1             @ encoding: [0x83,0xea,0x01,0x03]
 167 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 168 // CHECK: eoreq.w  r0, r1, r0             @ encoding: [0x81,0xea,0x00,0x00]
 169 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 170 // CHECK: eorseq.w r1, r1, r1             @ encoding: [0x91,0xea,0x01,0x01]
 171 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 172 // CHECK: eoreq    r7, r1                 @ encoding: [0x4f,0x40]
 173 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 174 // CHECK: eoreq    r7, r1                 @ encoding: [0x4f,0x40]
 175 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 176 // CHECK: eoreq.w  r8, r1, r8             @ encoding: [0x81,0xea,0x08,0x08]
 177 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 178 // CHECK: eoreq.w  r8, r8, r1             @ encoding: [0x88,0xea,0x01,0x08]
 179 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 180 // CHECK: eoreq.w  r0, r8, r0             @ encoding: [0x88,0xea,0x00,0x00]
 181 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 182 // CHECK: eoreq.w  r3, r3, r8             @ encoding: [0x83,0xea,0x08,0x03]
 183 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 184 // CHECK: eoreq.w  r4, r4, r1, lsl #1     @ encoding: [0x84,0xea,0x41,0x04]
 185 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 186 // CHECK: eoreq.w  r0, r1, r0, lsr #1     @ encoding: [0x81,0xea,0x50,0x00]
 187
 188 // LSL
 189     LSLS     r0, r2, r1          // Must be wide - 3 distinct registers
 190     LSLS     r2, r2, r1          // Should choose narrow
 191     LSLS     r2, r1, r2          // Should choose wide - not commutative
 192     LSLS.W   r0, r0, r1          // Explicitly wide
 193     LSLS.W   r4, r1, r4
 194     LSL      r4, r1, r4          // Must use wide encoding as not flag-setting
 195     LSLS     r7, r7, r1          // Should use narrow
 196     LSLS     r8, r1, r8          // high registers so must use wide encoding
 197     LSLS     r8, r8, r1
 198     LSLS     r3, r8, r3
 199     LSLS     r5, r5, r8
 200 // CHECK: lsls.w  r0, r2, r1              @ encoding: [0x12,0xfa,0x01,0xf0]
 201 // CHECK: lsls    r2, r1                  @ encoding: [0x8a,0x40]
 202 // CHECK: lsls.w  r2, r1, r2              @ encoding: [0x11,0xfa,0x02,0xf2]
 203 // CHECK: lsls.w  r0, r0, r1              @ encoding: [0x10,0xfa,0x01,0xf0]
 204 // CHECK: lsls.w  r4, r1, r4              @ encoding: [0x11,0xfa,0x04,0xf4]
 205 // CHECK: lsl.w   r4, r1, r4              @ encoding: [0x01,0xfa,0x04,0xf4]
 206 // CHECK: lsls    r7, r1                  @ encoding: [0x8f,0x40]
 207 // CHECK: lsls.w  r8, r1, r8              @ encoding: [0x11,0xfa,0x08,0xf8]
 208 // CHECK: lsls.w  r8, r8, r1              @ encoding: [0x18,0xfa,0x01,0xf8]
 209 // CHECK: lsls.w  r3, r8, r3              @ encoding: [0x18,0xfa,0x03,0xf3]
 210 // CHECK: lsls.w  r5, r5, r8              @ encoding: [0x15,0xfa,0x08,0xf5]
 211
 212     IT EQ
 213     LSLEQ    r0, r2, r1          // Must be wide - 3 distinct registers
 214     IT EQ
 215     LSLEQ    r2, r2, r1          // Should choose narrow
 216     IT EQ
 217     LSLEQ    r2, r1, r2          // Should choose wide - not commutative
 218     IT EQ
 219     LSLEQ.W  r0, r0, r1          // Explicitly wide
 220     IT EQ
 221     LSLEQ.W  r3, r1, r3
 222     IT EQ
 223     LSLSEQ   r4, r1, r4          // Must use wide encoding as flag-setting
 224     IT EQ
 225     LSLEQ    r7, r7, r1          // Should use narrow
 226     IT EQ
 227     LSLEQ    r8, r1, r8          // high registers so must use wide encoding
 228     IT EQ
 229     LSLEQ    r8, r8, r1
 230     IT EQ
 231     LSLEQ    r0, r8, r0
 232     IT EQ
 233     LSLEQ    r3, r3, r8
 234 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 235 // CHECK: lsleq.w  r0, r2, r1             @ encoding: [0x02,0xfa,0x01,0xf0]
 236 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 237 // CHECK: lsleq    r2, r1                 @ encoding: [0x8a,0x40]
 238 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 239 // CHECK: lsleq.w  r2, r1, r2             @ encoding: [0x01,0xfa,0x02,0xf2]
 240 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 241 // CHECK: lsleq.w  r0, r0, r1             @ encoding: [0x00,0xfa,0x01,0xf0]
 242 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 243 // CHECK: lsleq.w  r3, r1, r3             @ encoding: [0x01,0xfa,0x03,0xf3]
 244 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 245 // CHECK: lslseq.w r4, r1, r4             @ encoding: [0x11,0xfa,0x04,0xf4]
 246 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 247 // CHECK: lsleq    r7, r1                 @ encoding: [0x8f,0x40]
 248 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 249 // CHECK: lsleq.w  r8, r1, r8             @ encoding: [0x01,0xfa,0x08,0xf8]
 250 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 251 // CHECK: lsleq.w  r8, r8, r1             @ encoding: [0x08,0xfa,0x01,0xf8]
 252 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 253 // CHECK: lsleq.w  r0, r8, r0             @ encoding: [0x08,0xfa,0x00,0xf0]
 254 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 255 // CHECK: lsleq.w  r3, r3, r8             @ encoding: [0x03,0xfa,0x08,0xf3]
 256
 257 // LSR
 258     LSRS     r6, r2, r1          // Must be wide - 3 distinct registers
 259     LSRS     r2, r2, r1          // Should choose narrow
 260     LSRS     r2, r1, r2          // Should choose wide - not commutative
 261     LSRS.W   r2, r2, r1          // Explicitly wide
 262     LSRS.W   r3, r1, r3
 263     LSR      r4, r1, r4          // Must use wide encoding as not flag-setting
 264     LSRS     r7, r7, r1          // Should use narrow
 265     LSRS     r8, r1, r8          // high registers so must use wide encoding
 266     LSRS     r8, r8, r1
 267     LSRS     r2, r8, r2
 268     LSRS     r5, r5, r8
 269 // CHECK: lsrs.w  r6, r2, r1              @ encoding: [0x32,0xfa,0x01,0xf6]
 270 // CHECK: lsrs    r2, r1                  @ encoding: [0xca,0x40]
 271 // CHECK: lsrs.w  r2, r1, r2              @ encoding: [0x31,0xfa,0x02,0xf2]
 272 // CHECK: lsrs.w  r2, r2, r1              @ encoding: [0x32,0xfa,0x01,0xf2]
 273 // CHECK: lsrs.w  r3, r1, r3              @ encoding: [0x31,0xfa,0x03,0xf3]
 274 // CHECK: lsr.w   r4, r1, r4              @ encoding: [0x21,0xfa,0x04,0xf4]
 275 // CHECK: lsrs    r7, r1                  @ encoding: [0xcf,0x40]
 276 // CHECK: lsrs.w  r8, r1, r8              @ encoding: [0x31,0xfa,0x08,0xf8]
 277 // CHECK: lsrs.w  r8, r8, r1              @ encoding: [0x38,0xfa,0x01,0xf8]
 278 // CHECK: lsrs.w  r2, r8, r2              @ encoding: [0x38,0xfa,0x02,0xf2]
 279 // CHECK: lsrs.w  r5, r5, r8              @ encoding: [0x35,0xfa,0x08,0xf5]
 280
 281     IT EQ
 282     LSREQ    r6, r2, r1          // Must be wide - 3 distinct registers
 283     IT EQ
 284     LSREQ    r7, r7, r1          // Should choose narrow
 285     IT EQ
 286     LSREQ    r7, r1, r7          // Should choose wide - not commutative
 287     IT EQ
 288     LSREQ.W  r7, r7, r1          // Explicitly wide
 289     IT EQ
 290     LSREQ.W  r2, r1, r2
 291     IT EQ
 292     LSRSEQ   r0, r1, r0          // Must use wide encoding as flag-setting
 293     IT EQ
 294     LSREQ    r7, r7, r1          // Should use narrow
 295     IT EQ
 296     LSREQ    r8, r1, r8          // high registers so must use wide encoding
 297     IT EQ
 298     LSREQ    r8, r8, r1
 299     IT EQ
 300     LSREQ    r1, r8, r1
 301     IT EQ
 302     LSREQ    r4, r4, r8
 303 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 304 // CHECK: lsreq.w  r6, r2, r1             @ encoding: [0x22,0xfa,0x01,0xf6]
 305 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 306 // CHECK: lsreq    r7, r1                 @ encoding: [0xcf,0x40]
 307 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 308 // CHECK: lsreq.w  r7, r1, r7             @ encoding: [0x21,0xfa,0x07,0xf7]
 309 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 310 // CHECK: lsreq.w  r7, r7, r1             @ encoding: [0x27,0xfa,0x01,0xf7]
 311 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 312 // CHECK: lsreq.w  r2, r1, r2             @ encoding: [0x21,0xfa,0x02,0xf2]
 313 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 314 // CHECK: lsrseq.w r0, r1, r0             @ encoding: [0x31,0xfa,0x00,0xf0]
 315 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 316 // CHECK: lsreq    r7, r1                 @ encoding: [0xcf,0x40]
 317 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 318 // CHECK: lsreq.w  r8, r1, r8             @ encoding: [0x21,0xfa,0x08,0xf8]
 319 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 320 // CHECK: lsreq.w  r8, r8, r1             @ encoding: [0x28,0xfa,0x01,0xf8]
 321 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 322 // CHECK: lsreq.w  r1, r8, r1             @ encoding: [0x28,0xfa,0x01,0xf1]
 323 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 324 // CHECK: lsreq.w  r4, r4, r8             @ encoding: [0x24,0xfa,0x08,0xf4]
 325
 326 // ASR
 327     ASRS     r7, r6, r5          // Must be wide - 3 distinct registers
 328     ASRS     r0, r0, r1          // Should choose narrow
 329     ASRS     r0, r1, r0          // Should choose wide - not commutative
 330     ASRS.W   r3, r3, r1          // Explicitly wide
 331     ASRS.W   r1, r1, r1
 332     ASR      r0, r1, r0          // Must use wide encoding as not flag-setting
 333     ASRS     r7, r7, r1          // Should use narrow
 334     ASRS     r8, r1, r8          // high registers so must use wide encoding
 335     ASRS     r8, r8, r1
 336     ASRS     r5, r8, r5
 337     ASRS     r5, r5, r8
 338 // CHECK: asrs.w  r7, r6, r5              @ encoding: [0x56,0xfa,0x05,0xf7]
 339 // CHECK: asrs    r0, r1                  @ encoding: [0x08,0x41]
 340 // CHECK: asrs.w  r0, r1, r0              @ encoding: [0x51,0xfa,0x00,0xf0]
 341 // CHECK: asrs.w  r3, r3, r1              @ encoding: [0x53,0xfa,0x01,0xf3]
 342 // CHECK: asrs.w  r1, r1, r1              @ encoding: [0x51,0xfa,0x01,0xf1]
 343 // CHECK: asr.w   r0, r1, r0              @ encoding: [0x41,0xfa,0x00,0xf0]
 344 // CHECK: asrs    r7, r1                  @ encoding: [0x0f,0x41]
 345 // CHECK: asrs.w  r8, r1, r8              @ encoding: [0x51,0xfa,0x08,0xf8]
 346 // CHECK: asrs.w  r8, r8, r1              @ encoding: [0x58,0xfa,0x01,0xf8]
 347 // CHECK: asrs.w  r5, r8, r5              @ encoding: [0x58,0xfa,0x05,0xf5]
 348 // CHECK: asrs.w  r5, r5, r8              @ encoding: [0x55,0xfa,0x08,0xf5]
 349
 350     IT EQ
 351     ASREQ    r0, r2, r1          // Must be wide - 3 distinct registers
 352     IT EQ
 353     ASREQ    r2, r2, r1          // Should choose narrow
 354     IT EQ
 355     ASREQ    r1, r2, r1          // Should choose wide - not commutative
 356     IT EQ
 357     ASREQ.W  r4, r4, r1          // Explicitly wide
 358     IT EQ
 359     ASREQ.W  r6, r1, r6
 360     IT EQ
 361     ASRSEQ   r3, r1, r3          // Must use wide encoding as flag-setting
 362     IT EQ
 363     ASREQ    r7, r7, r1          // Should use narrow
 364     IT EQ
 365     ASREQ    r8, r1, r8          // high registers so must use wide encoding
 366     IT EQ
 367     ASREQ    r8, r8, r1
 368     IT EQ
 369     ASREQ    r1, r8, r1
 370     IT EQ
 371     ASREQ    r3, r3, r8
 372 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 373 // CHECK: asreq.w  r0, r2, r1             @ encoding: [0x42,0xfa,0x01,0xf0]
 374 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 375 // CHECK: asreq    r2, r1                 @ encoding: [0x0a,0x41]
 376 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 377 // CHECK: asreq.w  r1, r2, r1             @ encoding: [0x42,0xfa,0x01,0xf1]
 378 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 379 // CHECK: asreq.w  r4, r4, r1             @ encoding: [0x44,0xfa,0x01,0xf4]
 380 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 381 // CHECK: asreq.w  r6, r1, r6             @ encoding: [0x41,0xfa,0x06,0xf6]
 382 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 383 // CHECK: asrseq.w r3, r1, r3             @ encoding: [0x51,0xfa,0x03,0xf3]
 384 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 385 // CHECK: asreq    r7, r1                 @ encoding: [0x0f,0x41]
 386 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 387 // CHECK: asreq.w  r8, r1, r8             @ encoding: [0x41,0xfa,0x08,0xf8]
 388 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 389 // CHECK: asreq.w  r8, r8, r1             @ encoding: [0x48,0xfa,0x01,0xf8]
 390 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 391 // CHECK: asreq.w  r1, r8, r1             @ encoding: [0x48,0xfa,0x01,0xf1]
 392 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 393 // CHECK: asreq.w  r3, r3, r8             @ encoding: [0x43,0xfa,0x08,0xf3]
 394
 395 // ADC (commutative)
 396     ADCS     r5, r2, r1          // Must be wide - 3 distinct registers
 397     ADCS     r5, r5, r1          // Should choose narrow
 398     ADCS     r3, r1, r3          // Should choose narrow - commutative
 399     ADCS.W   r2, r2, r1          // Explicitly wide
 400     ADCS.W   r3, r1, r3
 401     ADC      r0, r1, r0          // Must use wide encoding as not flag-setting
 402     ADCS     r7, r7, r1          // Should use narrow
 403     ADCS     r7, r1, r7          // Commutative
 404     ADCS     r8, r1, r8          // high registers so must use wide encoding
 405     ADCS     r8, r8, r1
 406     ADCS     r5, r8, r5
 407     ADCS     r2, r2, r8
 408     ADCS     r3, r3, r1, lsl #1  // Must use wide - shifted register
 409     ADCS     r4, r1, r4, lsr #1
 410 // CHECK: adcs.w  r5, r2, r1              @ encoding: [0x52,0xeb,0x01,0x05]
 411 // CHECK: adcs    r5, r1                  @ encoding: [0x4d,0x41]
 412 // CHECK: adcs    r3, r1                  @ encoding: [0x4b,0x41]
 413 // CHECK: adcs.w  r2, r2, r1              @ encoding: [0x52,0xeb,0x01,0x02]
 414 // CHECK: adcs.w  r3, r1, r3              @ encoding: [0x51,0xeb,0x03,0x03]
 415 // CHECK: adc.w   r0, r1, r0              @ encoding: [0x41,0xeb,0x00,0x00]
 416 // CHECK: adcs    r7, r1                  @ encoding: [0x4f,0x41]
 417 // CHECK: adcs    r7, r1                  @ encoding: [0x4f,0x41]
 418 // CHECK: adcs.w  r8, r1, r8              @ encoding: [0x51,0xeb,0x08,0x08]
 419 // CHECK: adcs.w  r8, r8, r1              @ encoding: [0x58,0xeb,0x01,0x08]
 420 // CHECK: adcs.w  r5, r8, r5              @ encoding: [0x58,0xeb,0x05,0x05]
 421 // CHECK: adcs.w  r2, r2, r8              @ encoding: [0x52,0xeb,0x08,0x02]
 422 // CHECK: adcs.w  r3, r3, r1, lsl #1      @ encoding: [0x53,0xeb,0x41,0x03]
 423 // CHECK: adcs.w  r4, r1, r4, lsr #1      @ encoding: [0x51,0xeb,0x54,0x04]
 424
 425     IT EQ
 426     ADCEQ    r1, r2, r3          // Must be wide - 3 distinct registers
 427     IT EQ
 428     ADCEQ    r1, r1, r1          // Should choose narrow
 429     IT EQ
 430     ADCEQ    r3, r1, r3          // Should choose narrow - commutative
 431     IT EQ
 432     ADCEQ.W  r3, r3, r1          // Explicitly wide
 433     IT EQ
 434     ADCEQ.W  r0, r1, r0
 435     IT EQ
 436     ADCSEQ   r3, r1, r3          // Must use wide encoding as flag-setting
 437     IT EQ
 438     ADCEQ    r7, r7, r1          // Should use narrow
 439     IT EQ
 440     ADCEQ    r7, r1, r7          // Commutative
 441     IT EQ
 442     ADCEQ    r8, r1, r8          // high registers so must use wide encoding
 443     IT EQ
 444     ADCEQ    r8, r8, r1
 445     IT EQ
 446     ADCEQ    r3, r8, r3
 447     IT EQ
 448     ADCEQ    r1, r1, r8
 449     IT EQ
 450     ADCEQ    r2, r2, r1, lsl #1  // Must use wide - shifted register
 451     IT EQ
 452     ADCEQ    r1, r1, r1, lsr #1
 453 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 454 // CHECK: adceq.w  r1, r2, r3             @ encoding: [0x42,0xeb,0x03,0x01]
 455 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 456 // CHECK: adceq    r1, r1                 @ encoding: [0x49,0x41]
 457 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 458 // CHECK: adceq    r3, r1                 @ encoding: [0x4b,0x41]
 459 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 460 // CHECK: adceq.w  r3, r3, r1             @ encoding: [0x43,0xeb,0x01,0x03]
 461 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 462 // CHECK: adceq.w  r0, r1, r0             @ encoding: [0x41,0xeb,0x00,0x00]
 463 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 464 // CHECK: adcseq.w r3, r1, r3             @ encoding: [0x51,0xeb,0x03,0x03]
 465 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 466 // CHECK: adceq    r7, r1                 @ encoding: [0x4f,0x41]
 467 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 468 // CHECK: adceq    r7, r1                 @ encoding: [0x4f,0x41]
 469 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 470 // CHECK: adceq.w  r8, r1, r8             @ encoding: [0x41,0xeb,0x08,0x08]
 471 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 472 // CHECK: adceq.w  r8, r8, r1             @ encoding: [0x48,0xeb,0x01,0x08]
 473 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 474 // CHECK: adceq.w  r3, r8, r3             @ encoding: [0x48,0xeb,0x03,0x03]
 475 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 476 // CHECK: adceq.w  r1, r1, r8             @ encoding: [0x41,0xeb,0x08,0x01]
 477 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 478 // CHECK: adceq.w  r2, r2, r1, lsl #1     @ encoding: [0x42,0xeb,0x41,0x02]
 479 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 480 // CHECK: adceq.w  r1, r1, r1, lsr #1     @ encoding: [0x41,0xeb,0x51,0x01]
 481
 482 // SBC
 483     SBCS     r3, r2, r1          // Must be wide - 3 distinct registers
 484     SBCS     r4, r4, r1          // Should choose narrow
 485     SBCS     r1, r4, r1          // Should choose wide - not commutative
 486     SBCS.W   r4, r4, r1          // Explicitly wide
 487     SBCS.W   r2, r1, r2
 488     SBC      r0, r1, r0          // Must use wide encoding as not flag-setting
 489     SBCS     r7, r7, r1          // Should use narrow
 490     SBCS     r8, r1, r8          // high registers so must use wide encoding
 491     SBCS     r8, r8, r1
 492     SBCS     r4, r8, r4
 493     SBCS     r3, r3, r8
 494     SBCS     r2, r2, r1, lsl #1  // Must use wide - shifted register
 495     SBCS     r5, r1, r5, lsr #1
 496 // CHECK: sbcs.w  r3, r2, r1              @ encoding: [0x72,0xeb,0x01,0x03]
 497 // CHECK: sbcs    r4, r1                  @ encoding: [0x8c,0x41]
 498 // CHECK: sbcs.w  r1, r4, r1              @ encoding: [0x74,0xeb,0x01,0x01]
 499 // CHECK: sbcs.w  r4, r4, r1              @ encoding: [0x74,0xeb,0x01,0x04]
 500 // CHECK: sbcs.w  r2, r1, r2              @ encoding: [0x71,0xeb,0x02,0x02]
 501 // CHECK: sbc.w   r0, r1, r0              @ encoding: [0x61,0xeb,0x00,0x00]
 502 // CHECK: sbcs    r7, r1                  @ encoding: [0x8f,0x41]
 503 // CHECK: sbcs.w  r8, r1, r8              @ encoding: [0x71,0xeb,0x08,0x08]
 504 // CHECK: sbcs.w  r8, r8, r1              @ encoding: [0x78,0xeb,0x01,0x08]
 505 // CHECK: sbcs.w  r4, r8, r4              @ encoding: [0x78,0xeb,0x04,0x04]
 506 // CHECK: sbcs.w  r3, r3, r8              @ encoding: [0x73,0xeb,0x08,0x03]
 507 // CHECK: sbcs.w  r2, r2, r1, lsl #1      @ encoding: [0x72,0xeb,0x41,0x02]
 508 // CHECK: sbcs.w  r5, r1, r5, lsr #1      @ encoding: [0x71,0xeb,0x55,0x05]
 509
 510     IT EQ
 511     SBCEQ    r5, r2, r1          // Must be wide - 3 distinct registers
 512     IT EQ
 513     SBCEQ    r5, r5, r1          // Should choose narrow
 514     IT EQ
 515     SBCEQ    r1, r5, r1          // Should choose narrow
 516     IT EQ
 517     SBCEQ.W  r5, r5, r1          // Explicitly wide
 518     IT EQ
 519     SBCEQ.W  r0, r1, r0
 520     IT EQ
 521     SBCSEQ   r2, r1, r2          // Must use wide encoding as flag-setting
 522     IT EQ
 523     SBCEQ    r7, r7, r1          // Should use narrow
 524     IT EQ
 525     SBCEQ    r8, r1, r8          // high registers so must use wide encoding
 526     IT EQ
 527     SBCEQ    r8, r8, r1
 528     IT EQ
 529     SBCEQ    r7, r8, r7
 530     IT EQ
 531     SBCEQ    r7, r7, r8
 532     IT EQ
 533     SBCEQ    r2, r2, r1, lsl #1  // Must use wide - shifted register
 534     IT EQ
 535     SBCEQ    r5, r1, r5, lsr #1
 536 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 537 // CHECK: sbceq.w  r5, r2, r1             @ encoding: [0x62,0xeb,0x01,0x05]
 538 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 539 // CHECK: sbceq    r5, r1                 @ encoding: [0x8d,0x41]
 540 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 541 // CHECK: sbceq.w  r1, r5, r1             @ encoding: [0x65,0xeb,0x01,0x01]
 542 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 543 // CHECK: sbceq.w  r5, r5, r1             @ encoding: [0x65,0xeb,0x01,0x05]
 544 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 545 // CHECK: sbceq.w  r0, r1, r0             @ encoding: [0x61,0xeb,0x00,0x00]
 546 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 547 // CHECK: sbcseq.w r2, r1, r2             @ encoding: [0x71,0xeb,0x02,0x02]
 548 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 549 // CHECK: sbceq    r7, r1                 @ encoding: [0x8f,0x41]
 550 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 551 // CHECK: sbceq.w  r8, r1, r8             @ encoding: [0x61,0xeb,0x08,0x08]
 552 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 553 // CHECK: sbceq.w  r8, r8, r1             @ encoding: [0x68,0xeb,0x01,0x08]
 554 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 555 // CHECK: sbceq.w  r7, r8, r7             @ encoding: [0x68,0xeb,0x07,0x07]
 556 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 557 // CHECK: sbceq.w  r7, r7, r8             @ encoding: [0x67,0xeb,0x08,0x07]
 558 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 559 // CHECK: sbceq.w  r2, r2, r1, lsl #1     @ encoding: [0x62,0xeb,0x41,0x02]
 560 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 561 // CHECK: sbceq.w  r5, r1, r5, lsr #1     @ encoding: [0x61,0xeb,0x55,0x05]
 562
 563 // ROR
 564     RORS     r3, r2, r1          // Must be wide - 3 distinct registers
 565     RORS     r0, r0, r1          // Should choose narrow
 566     RORS     r1, r0, r1          // Should choose wide - not commutative
 567     RORS.W   r2, r2, r1          // Explicitly wide
 568     RORS.W   r2, r1, r2
 569     ROR      r5, r1, r5          // Must use wide encoding as not flag-setting
 570     RORS     r7, r7, r1          // Should use narrow
 571     RORS     r8, r1, r8          // high registers so must use wide encoding
 572     RORS     r8, r8, r1
 573     RORS     r6, r8, r6
 574     RORS     r6, r6, r8
 575 // CHECK: rors.w  r3, r2, r1              @ encoding: [0x72,0xfa,0x01,0xf3]
 576 // CHECK: rors    r0, r1                  @ encoding: [0xc8,0x41]
 577 // CHECK: rors.w  r1, r0, r1              @ encoding: [0x70,0xfa,0x01,0xf1]
 578 // CHECK: rors.w  r2, r2, r1              @ encoding: [0x72,0xfa,0x01,0xf2]
 579 // CHECK: rors.w  r2, r1, r2              @ encoding: [0x71,0xfa,0x02,0xf2]
 580 // CHECK: ror.w   r5, r1, r5              @ encoding: [0x61,0xfa,0x05,0xf5]
 581 // CHECK: rors    r7, r1                  @ encoding: [0xcf,0x41]
 582 // CHECK: rors.w  r8, r1, r8              @ encoding: [0x71,0xfa,0x08,0xf8]
 583 // CHECK: rors.w  r8, r8, r1              @ encoding: [0x78,0xfa,0x01,0xf8]
 584 // CHECK: rors.w  r6, r8, r6              @ encoding: [0x78,0xfa,0x06,0xf6]
 585 // CHECK: rors.w  r6, r6, r8              @ encoding: [0x76,0xfa,0x08,0xf6]
 586
 587     IT EQ
 588     ROREQ    r4, r2, r1          // Must be wide - 3 distinct registers
 589     IT EQ
 590     ROREQ    r4, r4, r1          // Should choose narrow
 591     IT EQ
 592     ROREQ    r1, r4, r1          // Should choose wide - not commutative
 593     IT EQ
 594     ROREQ.W  r4, r4, r1          // Explicitly wide
 595     IT EQ
 596     ROREQ.W  r0, r1, r0
 597     IT EQ
 598     RORSEQ   r0, r1, r0          // Must use wide encoding as flag-setting
 599     IT EQ
 600     ROREQ    r7, r7, r1          // Should use narrow
 601     IT EQ
 602     ROREQ    r8, r1, r8          // high registers so must use wide encoding
 603     IT EQ
 604     ROREQ    r8, r8, r1
 605     IT EQ
 606     ROREQ    r3, r8, r3
 607     IT EQ
 608     ROREQ    r1, r1, r8
 609 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 610 // CHECK: roreq.w  r4, r2, r1             @ encoding: [0x62,0xfa,0x01,0xf4]
 611 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 612 // CHECK: roreq    r4, r1                 @ encoding: [0xcc,0x41]
 613 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 614 // CHECK: roreq.w  r1, r4, r1             @ encoding: [0x64,0xfa,0x01,0xf1]
 615 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 616 // CHECK: roreq.w  r4, r4, r1             @ encoding: [0x64,0xfa,0x01,0xf4]
 617 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 618 // CHECK: roreq.w  r0, r1, r0             @ encoding: [0x61,0xfa,0x00,0xf0]
 619 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 620 // CHECK: rorseq.w r0, r1, r0             @ encoding: [0x71,0xfa,0x00,0xf0]
 621 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 622 // CHECK: roreq    r7, r1                 @ encoding: [0xcf,0x41]
 623 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 624 // CHECK: roreq.w  r8, r1, r8             @ encoding: [0x61,0xfa,0x08,0xf8]
 625 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 626 // CHECK: roreq.w  r8, r8, r1             @ encoding: [0x68,0xfa,0x01,0xf8]
 627 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 628 // CHECK: roreq.w  r3, r8, r3             @ encoding: [0x68,0xfa,0x03,0xf3]
 629 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 630 // CHECK: roreq.w  r1, r1, r8             @ encoding: [0x61,0xfa,0x08,0xf1]
 631
 632 // TST - only two register version available
 633 // RSB - only two register version available
 634 // CMP - only two register version available
 635 // CMN - only two register version available
 636
 637 // ORR (commutative)
 638     ORRS     r7, r2, r1          // Must be wide - 3 distinct registers
 639     ORRS     r2, r2, r1          // Should choose narrow
 640     ORRS     r3, r1, r3          // Should choose narrow - commutative
 641     ORRS.W   r4, r4, r1          // Explicitly wide
 642     ORRS.W   r5, r1, r5
 643     ORR      r2, r1, r2          // Must use wide encoding as not flag-setting
 644     ORRS     r7, r7, r1          // Should use narrow
 645     ORRS     r7, r1, r7          // Commutative
 646     ORRS     r8, r1, r8          // high registers so must use wide encoding
 647     ORRS     r8, r8, r1
 648     ORRS     r1, r8, r1
 649     ORRS     r0, r0, r8
 650     ORRS     r1, r1, r1, lsl #1  // Must use wide - shifted register
 651     ORRS     r0, r1, r0, lsr #1
 652 // CHECK: orrs.w  r7, r2, r1              @ encoding: [0x52,0xea,0x01,0x07]
 653 // CHECK: orrs    r2, r1                  @ encoding: [0x0a,0x43]
 654 // CHECK: orrs    r3, r1                  @ encoding: [0x0b,0x43]
 655 // CHECK: orrs.w  r4, r4, r1              @ encoding: [0x54,0xea,0x01,0x04]
 656 // CHECK: orrs.w  r5, r1, r5              @ encoding: [0x51,0xea,0x05,0x05]
 657 // CHECK: orr.w   r2, r1, r2              @ encoding: [0x41,0xea,0x02,0x02]
 658 // CHECK: orrs    r7, r1                  @ encoding: [0x0f,0x43]
 659 // CHECK: orrs    r7, r1                  @ encoding: [0x0f,0x43]
 660 // CHECK: orrs.w  r8, r1, r8              @ encoding: [0x51,0xea,0x08,0x08]
 661 // CHECK: orrs.w  r8, r8, r1              @ encoding: [0x58,0xea,0x01,0x08]
 662 // CHECK: orrs.w  r1, r8, r1              @ encoding: [0x58,0xea,0x01,0x01]
 663 // CHECK: orrs.w  r0, r0, r8              @ encoding: [0x50,0xea,0x08,0x00]
 664 // CHECK: orrs.w  r1, r1, r1, lsl #1      @ encoding: [0x51,0xea,0x41,0x01]
 665 // CHECK: orrs.w  r0, r1, r0, lsr #1      @ encoding: [0x51,0xea,0x50,0x00]
 666
 667     IT EQ
 668     ORREQ    r0, r2, r1          // Must be wide - 3 distinct registers
 669     IT EQ
 670     ORREQ    r5, r5, r1          // Should choose narrow
 671     IT EQ
 672     ORREQ    r5, r1, r5          // Should choose narrow - commutative
 673     IT EQ
 674     ORREQ.W  r2, r2, r1          // Explicitly wide
 675     IT EQ
 676     ORREQ.W  r3, r1, r3
 677     IT EQ
 678     ORRSEQ   r4, r1, r4          // Must use wide encoding as flag-setting
 679     IT EQ
 680     ORREQ    r7, r7, r1          // Should use narrow
 681     IT EQ
 682     ORREQ    r7, r1, r7          // Commutative
 683     IT EQ
 684     ORREQ    r8, r1, r8          // high registers so must use wide encoding
 685     IT EQ
 686     ORREQ    r8, r8, r1
 687     IT EQ
 688     ORREQ    r0, r8, r0
 689     IT EQ
 690     ORREQ    r0, r0, r8
 691     IT EQ
 692     ORREQ    r2, r2, r1, lsl #1  // Must use wide - shifted register
 693     IT EQ
 694     ORREQ    r2, r1, r2, lsr #1
 695 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 696 // CHECK: orreq.w  r0, r2, r1             @ encoding: [0x42,0xea,0x01,0x00]
 697 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 698 // CHECK: orreq    r5, r1                 @ encoding: [0x0d,0x43]
 699 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 700 // CHECK: orreq    r5, r1                 @ encoding: [0x0d,0x43]
 701 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 702 // CHECK: orreq.w  r2, r2, r1             @ encoding: [0x42,0xea,0x01,0x02]
 703 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 704 // CHECK: orreq.w  r3, r1, r3             @ encoding: [0x41,0xea,0x03,0x03]
 705 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 706 // CHECK: orrseq.w r4, r1, r4             @ encoding: [0x51,0xea,0x04,0x04]
 707 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 708 // CHECK: orreq    r7, r1                 @ encoding: [0x0f,0x43]
 709 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 710 // CHECK: orreq    r7, r1                 @ encoding: [0x0f,0x43]
 711 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 712 // CHECK: orreq.w  r8, r1, r8             @ encoding: [0x41,0xea,0x08,0x08]
 713 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 714 // CHECK: orreq.w  r8, r8, r1             @ encoding: [0x48,0xea,0x01,0x08]
 715 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 716 // CHECK: orreq.w  r0, r8, r0             @ encoding: [0x48,0xea,0x00,0x00]
 717 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 718 // CHECK: orreq.w  r0, r0, r8             @ encoding: [0x40,0xea,0x08,0x00]
 719 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 720 // CHECK: orreq.w  r2, r2, r1, lsl #1     @ encoding: [0x42,0xea,0x41,0x02]
 721 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 722 // CHECK: orreq.w  r2, r1, r2, lsr #1     @ encoding: [0x41,0xea,0x52,0x02]
 723
 724 // MUL - not affected by this change
 725
 726 // BIC
 727     BICS     r3, r2, r1          // Must be wide - 3 distinct registers
 728     BICS     r2, r2, r1          // Should choose narrow
 729     BICS     r1, r2, r1          // Should choose wide - not commutative
 730     BICS.W   r2, r2, r1          // Explicitly wide
 731     BICS.W   r0, r1, r0
 732     BIC      r0, r1, r0          // Must use wide encoding as not flag-setting
 733     BICS     r7, r7, r1          // Should use narrow
 734     BICS     r8, r1, r8          // high registers so must use wide encoding
 735     BICS     r8, r8, r1
 736     BICS     r7, r8, r7
 737     BICS     r5, r5, r8
 738     BICS     r3, r3, r1, lsl #1  // Must use wide - shifted register
 739     BICS     r4, r1, r4, lsr #1
 740 // CHECK: bics.w  r3, r2, r1              @ encoding: [0x32,0xea,0x01,0x03]
 741 // CHECK: bics    r2, r1                  @ encoding: [0x8a,0x43]
 742 // CHECK: bics.w  r1, r2, r1              @ encoding: [0x32,0xea,0x01,0x01]
 743 // CHECK: bics.w  r2, r2, r1              @ encoding: [0x32,0xea,0x01,0x02]
 744 // CHECK: bics.w  r0, r1, r0              @ encoding: [0x31,0xea,0x00,0x00]
 745 // CHECK: bic.w   r0, r1, r0              @ encoding: [0x21,0xea,0x00,0x00]
 746 // CHECK: bics    r7, r1                  @ encoding: [0x8f,0x43]
 747 // CHECK: bics.w  r8, r1, r8              @ encoding: [0x31,0xea,0x08,0x08]
 748 // CHECK: bics.w  r8, r8, r1              @ encoding: [0x38,0xea,0x01,0x08]
 749 // CHECK: bics.w  r7, r8, r7              @ encoding: [0x38,0xea,0x07,0x07]
 750 // CHECK: bics.w  r5, r5, r8              @ encoding: [0x35,0xea,0x08,0x05]
 751 // CHECK: bics.w  r3, r3, r1, lsl #1      @ encoding: [0x33,0xea,0x41,0x03]
 752 // CHECK: bics.w  r4, r1, r4, lsr #1      @ encoding: [0x31,0xea,0x54,0x04]
 753
 754     IT EQ
 755     BICEQ    r0, r2, r1          // Must be wide - 3 distinct registers
 756     IT EQ
 757     BICEQ    r5, r5, r1          // Should choose narrow
 758     IT EQ
 759     BICEQ    r1, r5, r1          // Should choose wide - not commutative
 760     IT EQ
 761     BICEQ.W  r4, r4, r1          // Explicitly wide
 762     IT EQ
 763     BICEQ.W  r2, r1, r2
 764     IT EQ
 765     BICSEQ   r5, r1, r5          // Must use wide encoding as flag-setting
 766     IT EQ
 767     BICEQ    r7, r7, r1          // Should use narrow
 768     IT EQ
 769     BICEQ    r8, r1, r8          // high registers so must use wide encoding
 770     IT EQ
 771     BICEQ    r8, r8, r1
 772     IT EQ
 773     BICEQ    r0, r8, r0
 774     IT EQ
 775     BICEQ    r2, r2, r8
 776     IT EQ
 777     BICEQ    r4, r4, r1, lsl #1  // Must use wide - shifted register
 778     IT EQ
 779     BICEQ    r5, r1, r5, lsr #1
 780 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 781 // CHECK: biceq.w  r0, r2, r1             @ encoding: [0x22,0xea,0x01,0x00]
 782 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 783 // CHECK: biceq    r5, r1                 @ encoding: [0x8d,0x43]
 784 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 785 // CHECK: biceq.w  r1, r5, r1             @ encoding: [0x25,0xea,0x01,0x01]
 786 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 787 // CHECK: biceq.w  r4, r4, r1             @ encoding: [0x24,0xea,0x01,0x04]
 788 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 789 // CHECK: biceq.w  r2, r1, r2             @ encoding: [0x21,0xea,0x02,0x02]
 790 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 791 // CHECK: bicseq.w r5, r1, r5             @ encoding: [0x31,0xea,0x05,0x05]
 792 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 793 // CHECK: biceq    r7, r1                 @ encoding: [0x8f,0x43]
 794 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 795 // CHECK: biceq.w  r8, r1, r8             @ encoding: [0x21,0xea,0x08,0x08]
 796 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 797 // CHECK: biceq.w  r8, r8, r1             @ encoding: [0x28,0xea,0x01,0x08]
 798 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 799 // CHECK: biceq.w  r0, r8, r0             @ encoding: [0x28,0xea,0x00,0x00]
 800 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 801 // CHECK: biceq.w  r2, r2, r8             @ encoding: [0x22,0xea,0x08,0x02]
 802 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 803 // CHECK: biceq.w  r4, r4, r1, lsl #1     @ encoding: [0x24,0xea,0x41,0x04]
 804 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 805 // CHECK: biceq.w  r5, r1, r5, lsr #1     @ encoding: [0x21,0xea,0x55,0x05]
 806
 807 // CMN - only two register version available