1 ;RUN: llc -mtriple=armv7-apple-darwin -show-mc-encoding < %s | FileCheck %s
4 ;FIXME: Once the ARM integrated assembler is up and going, these sorts of tests
5 ; should run on .s source files rather than using llc to generate the
8 define i32 @foo(i32 %a, i32 %b) {
11 ; CHECK: trap @ encoding: [0xf0,0x00,0xf0,0x07]
12 ; CHECK: bx lr @ encoding: [0x1e,0xff,0x2f,0xe1]
14 tail call void @llvm.trap()
18 define i32 @f2(i32 %a, i32 %b) {
21 ; CHECK: add r0, r1, r0 @ encoding: [0x00,0x00,0x81,0xe0]
22 ; CHECK: bx lr @ encoding: [0x1e,0xff,0x2f,0xe1]
23 %add = add nsw i32 %b, %a
28 define i32 @f3(i32 %a, i32 %b) {
31 ; CHECK: add r0, r0, r1, lsl #3 @ encoding: [0x81,0x01,0x80,0xe0]
32 ; CHECK: bx lr @ encoding: [0x1e,0xff,0x2f,0xe1]
34 %add = add nsw i32 %mul, %a
38 define i32 @f4(i32 %a, i32 %b) {
41 ; CHECK: add r0, r0, #254, 28 @ encoding: [0xfe,0x0e,0x80,0xe2]
43 ; CHECK: bx lr @ encoding: [0x1e,0xff,0x2f,0xe1]
44 %add = add nsw i32 %a, 4064
48 define i32 @f5(i32 %a, i32 %b, i32 %c) {
51 ; CHECK: cmp r0, r1 @ encoding: [0x01,0x00,0x50,0xe1]
52 ; CHECK: mov r0, r2 @ encoding: [0x02,0x00,0xa0,0xe1]
53 ; CHECK: movgt r0, r1 @ encoding: [0x01,0x00,0xa0,0xc1]
54 %cmp = icmp sgt i32 %a, %b
55 %retval.0 = select i1 %cmp, i32 %b, i32 %c
59 define i64 @f6(i64 %a, i64 %b, i64 %c) {
62 ; CHECK: adds r0, r2, r0 @ encoding: [0x00,0x00,0x92,0xe0]
63 ; CHECK: adc r1, r3, r1 @ encoding: [0x01,0x10,0xa3,0xe0]
64 %add = add nsw i64 %b, %a
68 define i32 @f7(i32 %a, i32 %b) {
71 ; CHECK: uxtab r0, r0, r1 @ encoding: [0x71,0x00,0xe0,0xe6]
72 %and = and i32 %b, 255
73 %add = add i32 %and, %a
77 define i32 @f8(i32 %a) {
80 ; CHECK: movt r0, #42405 @ encoding: [0xa5,0x05,0x4a,0xe3]
81 %and = and i32 %a, 65535
82 %or = or i32 %and, -1515913216
89 ; CHECK: movw r0, #42405 @ encoding: [0xa5,0x05,0x0a,0xe3]
93 define i64 @f10(i64 %a) {
96 ; CHECK: asrs r1, r1, #1 @ encoding: [0xc1,0x10,0xb0,0xe1]
97 ; CHECK: rrx r0, r0 @ encoding: [0x60,0x00,0xa0,0xe1]
102 define i32 @f11([1 x i32] %A.coerce0, [1 x i32] %B.coerce0) {
105 ; CHECK: ubfx r1, r1, #8, #5 @ encoding: [0x51,0x14,0xe4,0xe7]
106 ; CHECK: sbfx r0, r0, #13, #7 @ encoding: [0xd0,0x06,0xa6,0xe7]
107 %tmp11 = extractvalue [1 x i32] %A.coerce0, 0
108 %tmp4 = extractvalue [1 x i32] %B.coerce0, 0
109 %0 = shl i32 %tmp11, 12
110 %bf.val.sext = ashr i32 %0, 25
111 %1 = lshr i32 %tmp4, 8
112 %bf.clear2 = and i32 %1, 31
113 %mul = mul nsw i32 %bf.val.sext, %bf.clear2
117 define i32 @f12(i32 %a) {
119 ; CHECK: bfc r0, #4, #20 @ encoding: [0x1f,0x02,0xd7,0xe7]
120 %tmp = and i32 %a, 4278190095
126 ; CHECK: mvn r0, #0 @ encoding: [0x00,0x00,0xe0,0xe3]
127 ; CHECK: mvn r1, #2, 2 @ encoding: [0x02,0x11,0xe0,0xe3]
129 ret i64 9223372036854775807
132 define i32 @f14(i32 %x, i32 %y) {
134 ; CHECK: smmul r0, r1, r0 @ encoding: [0x11,0xf0,0x50,0xe7]
135 %tmp = sext i32 %x to i64
136 %tmp1 = sext i32 %y to i64
137 %tmp2 = mul i64 %tmp1, %tmp
138 %tmp3 = lshr i64 %tmp2, 32
139 %tmp3.upgrd.1 = trunc i64 %tmp3 to i32
140 ret i32 %tmp3.upgrd.1
143 define i32 @f15(i32 %x, i32 %y) {
145 ; CHECK: umull r1, r0, r1, r0 @ encoding: [0x91,0x10,0x80,0xe0]
146 %tmp = zext i32 %x to i64
147 %tmp1 = zext i32 %y to i64
148 %tmp2 = mul i64 %tmp1, %tmp
149 %tmp3 = lshr i64 %tmp2, 32
150 %tmp3.upgrd.2 = trunc i64 %tmp3 to i32
151 ret i32 %tmp3.upgrd.2
153 declare void @llvm.trap() nounwind