SimplifyCFG: don't remove unreachable default switch destinations
[oota-llvm.git] / test / MC / ARM / neont2-mul-encoding.s
1 @ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unknown -show-encoding < %s | FileCheck %s
2
3 .code 16
4
5         vmul.i8 d16, d16, d17
6         vmul.i16        d16, d16, d17
7         vmul.i32        d16, d16, d17
8         vmul.f32        d16, d16, d17
9         vmul.i8 q8, q8, q9
10         vmul.i16        q8, q8, q9
11         vmul.i32        q8, q8, q9
12         vmul.f32        q8, q8, q9
13         vmul.p8 d16, d16, d17
14         vmul.p8 q8, q8, q9
15         vmul.i16        d18, d8, d0[3]
16
17 @ CHECK: vmul.i8        d16, d16, d17   @ encoding: [0x40,0xef,0xb1,0x09]
18 @ CHECK: vmul.i16       d16, d16, d17   @ encoding: [0x50,0xef,0xb1,0x09]
19 @ CHECK: vmul.i32       d16, d16, d17   @ encoding: [0x60,0xef,0xb1,0x09]
20 @ CHECK: vmul.f32       d16, d16, d17   @ encoding: [0x40,0xff,0xb1,0x0d]
21 @ CHECK: vmul.i8        q8, q8, q9      @ encoding: [0x40,0xef,0xf2,0x09]
22 @ CHECK: vmul.i16       q8, q8, q9      @ encoding: [0x50,0xef,0xf2,0x09]
23 @ CHECK: vmul.i32       q8, q8, q9      @ encoding: [0x60,0xef,0xf2,0x09]
24 @ CHECK: vmul.f32       q8, q8, q9      @ encoding: [0x40,0xff,0xf2,0x0d]
25 @ CHECK: vmul.p8        d16, d16, d17   @ encoding: [0x40,0xff,0xb1,0x09]
26 @ CHECK: vmul.p8        q8, q8, q9      @ encoding: [0x40,0xff,0xf2,0x09]
27 @ CHECK: vmul.i16       d18, d8, d0[3]  @ encoding: [0xd8,0xef,0x68,0x28]
28
29
30         vqdmulh.s16     d16, d16, d17
31         vqdmulh.s32     d16, d16, d17
32         vqdmulh.s16     q8, q8, q9
33         vqdmulh.s32     q8, q8, q9
34         vqdmulh.s16     d11, d2, d3[0]
35
36 @ CHECK: vqdmulh.s16    d16, d16, d17   @ encoding: [0x50,0xef,0xa1,0x0b]
37 @ CHECK: vqdmulh.s32    d16, d16, d17   @ encoding: [0x60,0xef,0xa1,0x0b]
38 @ CHECK: vqdmulh.s16    q8, q8, q9      @ encoding: [0x50,0xef,0xe2,0x0b]
39 @ CHECK: vqdmulh.s32    q8, q8, q9      @ encoding: [0x60,0xef,0xe2,0x0b]
40 @ CHECK: vqdmulh.s16    d11, d2, d3[0]  @ encoding: [0x92,0xef,0x43,0xbc]
41
42
43         vqrdmulh.s16    d16, d16, d17
44         vqrdmulh.s32    d16, d16, d17
45         vqrdmulh.s16    q8, q8, q9
46         vqrdmulh.s32    q8, q8, q9
47
48 @ CHECK: vqrdmulh.s16   d16, d16, d17   @ encoding: [0x50,0xff,0xa1,0x0b]
49 @ CHECK: vqrdmulh.s32   d16, d16, d17   @ encoding: [0x60,0xff,0xa1,0x0b]
50 @ CHECK: vqrdmulh.s16   q8, q8, q9      @ encoding: [0x50,0xff,0xe2,0x0b]
51 @ CHECK: vqrdmulh.s32   q8, q8, q9      @ encoding: [0x60,0xff,0xe2,0x0b]
52
53
54         vmull.s8        q8, d16, d17
55         vmull.s16       q8, d16, d17
56         vmull.s32       q8, d16, d17
57         vmull.u8        q8, d16, d17
58         vmull.u16       q8, d16, d17
59         vmull.u32       q8, d16, d17
60         vmull.p8        q8, d16, d17
61
62 @ CHECK: vmull.s8       q8, d16, d17    @ encoding: [0xc0,0xef,0xa1,0x0c]
63 @ CHECK: vmull.s16      q8, d16, d17    @ encoding: [0xd0,0xef,0xa1,0x0c]
64 @ CHECK: vmull.s32      q8, d16, d17    @ encoding: [0xe0,0xef,0xa1,0x0c]
65 @ CHECK: vmull.u8       q8, d16, d17    @ encoding: [0xc0,0xff,0xa1,0x0c]
66 @ CHECK: vmull.u16      q8, d16, d17    @ encoding: [0xd0,0xff,0xa1,0x0c]
67 @ CHECK: vmull.u32      q8, d16, d17    @ encoding: [0xe0,0xff,0xa1,0x0c]
68 @ CHECK: vmull.p8       q8, d16, d17    @ encoding: [0xc0,0xef,0xa1,0x0e]
69
70
71         vqdmull.s16     q8, d16, d17
72         vqdmull.s32     q8, d16, d17
73         vqdmull.s16     q1, d7, d1[1]
74
75 @ CHECK: vqdmull.s16    q8, d16, d17    @ encoding: [0xd0,0xef,0xa1,0x0d]
76 @ CHECK: vqdmull.s32    q8, d16, d17    @ encoding: [0xe0,0xef,0xa1,0x0d]
77 @ CHECK: vqdmull.s16    q1, d7, d1[1]   @ encoding: [0x97,0xef,0x49,0x2b]
78