Mark ARM subtarget features that are available for the assembler.
[oota-llvm.git] / test / MC / ARM / neon-shift-encoding.s
1 // RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s
2
3 // CHECK: vshl.u8       d16, d17, d16           @ encoding: [0xa1,0x04,0x40,0xf3]
4         vshl.u8 d16, d17, d16
5 // CHECK: vshl.u16      d16, d17, d16   @ encoding: [0xa1,0x04,0x50,0xf3]
6         vshl.u16        d16, d17, d16
7 // CHECK: vshl.u32      d16, d17, d16   @ encoding: [0xa1,0x04,0x60,0xf3]
8         vshl.u32        d16, d17, d16
9 // CHECK: vshl.u64      d16, d17, d16   @ encoding: [0xa1,0x04,0x70,0xf3]
10         vshl.u64        d16, d17, d16
11 // CHECK: vshl.i8       d16, d16, #7            @ encoding: [0x30,0x05,0xcf,0xf2]
12         vshl.i8 d16, d16, #7
13 // CHECK: vshl.i16      d16, d16, #15   @ encoding: [0x30,0x05,0xdf,0xf2]
14         vshl.i16        d16, d16, #15
15 // CHECK: vshl.i32      d16, d16, #31   @ encoding: [0x30,0x05,0xff,0xf2]
16         vshl.i32        d16, d16, #31
17 // CHECK: vshl.i64      d16, d16, #63   @ encoding: [0xb0,0x05,0xff,0xf2]
18         vshl.i64        d16, d16, #63
19 // CHECK: vshl.u8       q8, q9, q8              @ encoding: [0xe2,0x04,0x40,0xf3]
20         vshl.u8 q8, q9, q8
21 // CHECK: vshl.u16      q8, q9, q8      @ encoding: [0xe2,0x04,0x50,0xf3]
22         vshl.u16        q8, q9, q8
23 // CHECK: vshl.u32      q8, q9, q8      @ encoding: [0xe2,0x04,0x60,0xf3]
24         vshl.u32        q8, q9, q8
25 // CHECK: vshl.u64      q8, q9, q8      @ encoding: [0xe2,0x04,0x70,0xf3]
26         vshl.u64        q8, q9, q8
27 // CHECK: vshl.i8       q8, q8, #7              @ encoding: [0x70,0x05,0xcf,0xf2]
28         vshl.i8 q8, q8, #7
29 // CHECK: vshl.i16      q8, q8, #15     @ encoding: [0x70,0x05,0xdf,0xf2]
30         vshl.i16        q8, q8, #15
31 // CHECK: vshl.i32      q8, q8, #31     @ encoding: [0x70,0x05,0xff,0xf2]
32         vshl.i32        q8, q8, #31
33 // CHECK: vshl.i64      q8, q8, #63     @ encoding: [0xf0,0x05,0xff,0xf2]
34         vshl.i64        q8, q8, #63
35 // CHECK: vshr.u8       d16, d16, #8            @ encoding: [0x30,0x00,0xc8,0xf3]
36         vshr.u8 d16, d16, #8
37 // CHECK: vshr.u16      d16, d16, #16   @ encoding: [0x30,0x00,0xd0,0xf3]
38         vshr.u16        d16, d16, #16
39 // CHECK: vshr.u32      d16, d16, #32   @ encoding: [0x30,0x00,0xe0,0xf3]
40         vshr.u32        d16, d16, #32
41 // CHECK: vshr.u64      d16, d16, #64   @ encoding: [0xb0,0x00,0xc0,0xf3]
42         vshr.u64        d16, d16, #64
43 // CHECK: vshr.u8       q8, q8, #8              @ encoding: [0x70,0x00,0xc8,0xf3]
44         vshr.u8 q8, q8, #8
45 // CHECK: vshr.u16      q8, q8, #16     @ encoding: [0x70,0x00,0xd0,0xf3]
46         vshr.u16        q8, q8, #16
47 // CHECK: vshr.u32      q8, q8, #32     @ encoding: [0x70,0x00,0xe0,0xf3]
48         vshr.u32        q8, q8, #32
49 // CHECK: vshr.u64      q8, q8, #64     @ encoding: [0xf0,0x00,0xc0,0xf3]
50         vshr.u64        q8, q8, #64
51 // CHECK: vshr.s8       d16, d16, #8            @ encoding: [0x30,0x00,0xc8,0xf2]
52         vshr.s8 d16, d16, #8
53 // CHECK: vshr.s16      d16, d16, #16   @ encoding: [0x30,0x00,0xd0,0xf2]
54         vshr.s16        d16, d16, #16
55 // CHECK: vshr.s32      d16, d16, #32   @ encoding: [0x30,0x00,0xe0,0xf2]
56         vshr.s32        d16, d16, #32
57 // CHECK: vshr.s64      d16, d16, #64   @ encoding: [0xb0,0x00,0xc0,0xf2]
58         vshr.s64        d16, d16, #64
59 // CHECK: vshr.s8       q8, q8, #8              @ encoding: [0x70,0x00,0xc8,0xf2]
60         vshr.s8 q8, q8, #8
61 // CHECK: vshr.s16      q8, q8, #16     @ encoding: [0x70,0x00,0xd0,0xf2]
62         vshr.s16        q8, q8, #16
63 // CHECK: vshr.s32      q8, q8, #32     @ encoding: [0x70,0x00,0xe0,0xf2
64         vshr.s32        q8, q8, #32
65 // CHECK: vshr.s64      q8, q8, #64     @ encoding: [0xf0,0x00,0xc0,0xf2]
66         vshr.s64        q8, q8, #64
67 // CHECK: vshll.s8      q8, d16, #7     @ encoding: [0x30,0x0a,0xcf,0xf2]
68         vshll.s8        q8, d16, #7
69 // CHECK: vshll.s16     q8, d16, #15    @ encoding: [0x30,0x0a,0xdf,0xf2]
70         vshll.s16       q8, d16, #15
71 // CHECK: vshll.s32     q8, d16, #31    @ encoding: [0x30,0x0a,0xff,0xf2]
72         vshll.s32       q8, d16, #31
73 // CHECK: vshll.u8      q8, d16, #7     @ encoding: [0x30,0x0a,0xcf,0xf3]
74         vshll.u8        q8, d16, #7
75 // CHECK: vshll.u16     q8, d16, #15    @ encoding: [0x30,0x0a,0xdf,0xf3]
76         vshll.u16       q8, d16, #15
77 // CHECK: vshll.u32     q8, d16, #31    @ encoding: [0x30,0x0a,0xff,0xf3]
78         vshll.u32       q8, d16, #31
79 // CHECK: vshll.i8      q8, d16, #8     @ encoding: [0x20,0x03,0xf2,0xf3]
80         vshll.i8        q8, d16, #8
81 // CHECK: vshll.i16     q8, d16, #16    @ encoding: [0x20,0x03,0xf6,0xf3]
82         vshll.i16       q8, d16, #16
83 // CHECK: vshll.i32     q8, d16, #32    @ encoding: [0x20,0x03,0xfa,0xf3]
84         vshll.i32       q8, d16, #32
85 // CHECK: vshrn.i16     d16, q8, #8     @ encoding: [0x30,0x08,0xc8,0xf2]
86         vshrn.i16       d16, q8, #8
87 // CHECK: vshrn.i32     d16, q8, #16    @ encoding: [0x30,0x08,0xd0,0xf2]
88         vshrn.i32       d16, q8, #16
89 // CHECK: vshrn.i64     d16, q8, #32    @ encoding: [0x30,0x08,0xe0,0xf2]
90         vshrn.i64       d16, q8, #32
91 // CHECK: vrshl.s8      d16, d17, d16   @ encoding: [0xa1,0x05,0x40,0xf2]
92         vrshl.s8        d16, d17, d16
93 // CHECK: vrshl.s16     d16, d17, d16   @ encoding: [0xa1,0x05,0x50,0xf2]
94         vrshl.s16       d16, d17, d16
95 // CHECK: vrshl.s32     d16, d17, d16   @ encoding: [0xa1,0x05,0x60,0xf2]
96         vrshl.s32       d16, d17, d16
97 // CHECK: vrshl.s64     d16, d17, d16   @ encoding: [0xa1,0x05,0x70,0
98         vrshl.s64       d16, d17, d16
99 // CHECK: vrshl.u8      d16, d17, d16   @ encoding: [0xa1,0x05,0x40,0xf3]
100         vrshl.u8        d16, d17, d16
101 // CHECK: vrshl.u16     d16, d17, d16   @ encoding: [0xa1,0x05,0x50,0xf3]
102         vrshl.u16       d16, d17, d16
103 // CHECK: vrshl.u32     d16, d17, d16   @ encoding: [0xa1,0x05,0x60,0xf3]
104         vrshl.u32       d16, d17, d16
105 // CHECK: vrshl.u64     d16, d17, d16   @ encoding: [0xa1,0x05,0x70,0xf3]
106         vrshl.u64       d16, d17, d16
107 // CHECK: vrshl.s8      q8, q9, q8      @ encoding: [0xe2,0x05,0x40,0xf2]
108         vrshl.s8        q8, q9, q8
109 // CHECK: vrshl.s16     q8, q9, q8      @ encoding: [0xe2,0x05,0x50,0xf2]
110         vrshl.s16       q8, q9, q8
111 // CHECK: vrshl.s32     q8, q9, q8      @ encoding: [0xe2,0x05,0x60,0xf2]
112         vrshl.s32       q8, q9, q8
113 // CHECK: vrshl.s64     q8, q9, q8      @ encoding: [0xe2,0x05,0x70,0xf2]
114         vrshl.s64       q8, q9, q8
115 // CHECK: vrshl.u8      q8, q9, q8      @ encoding: [0xe2,0x05,0x40,0xf3]
116         vrshl.u8        q8, q9, q8
117 // CHECK: vrshl.u16     q8, q9, q8      @ encoding: [0xe2,0x05,0x50,0xf3]
118         vrshl.u16       q8, q9, q8
119 // CHECK: vrshl.u32     q8, q9, q8      @ encoding: [0xe2,0x05,0x60,0xf3]
120         vrshl.u32       q8, q9, q8
121 // CHECK: vrshl.u64     q8, q9, q8      @ encoding: [0xe2,0x05,0x70,0xf3]
122         vrshl.u64       q8, q9, q8
123 // CHECK: vrshr.s8      d16, d16, #8    @ encoding: [0x30,0x02,0xc8,0xf2]
124         vrshr.s8        d16, d16, #8
125 // CHECK: vrshr.s16     d16, d16, #16   @ encoding: [0x30,0x02,0xd0,0xf2]
126         vrshr.s16       d16, d16, #16
127 // CHECK: vrshr.s32     d16, d16, #32   @ encoding: [0x30,0x02,0xe0,0xf2]
128         vrshr.s32       d16, d16, #32
129 // CHECK: vrshr.s64     d16, d16, #64   @ encoding: [0xb0,0x02,0xc0,0xf2]
130         vrshr.s64       d16, d16, #64
131 // CHECK: vrshr.u8      d16, d16, #8    @ encoding: [0x30,0x02,0xc8,0xf3]
132         vrshr.u8        d16, d16, #8
133 // CHECK: vrshr.u16     d16, d16, #16   @ encoding: [0x30,0x02,0xd0,0xf3]
134         vrshr.u16       d16, d16, #16
135 // CHECK: vrshr.u32     d16, d16, #32   @ encoding: [0x30,0x02,0xe0,0xf3]
136         vrshr.u32       d16, d16, #32
137 // CHECK: vrshr.u64     d16, d16, #64   @ encoding: [0xb0,0x02,0xc0,0xf3]
138         vrshr.u64       d16, d16, #64
139 // CHECK: vrshr.s8      q8, q8, #8      @ encoding: [0x70,0x02,0xc8,0xf2]
140         vrshr.s8        q8, q8, #8
141 // CHECK: vrshr.s16     q8, q8, #16     @ encoding: [0x70,0x02,0xd0,0xf2]
142         vrshr.s16       q8, q8, #16
143 // CHECK: vrshr.s32     q8, q8, #32     @ encoding: [0x70,0x02,0xe0,0xf2]
144         vrshr.s32       q8, q8, #32
145 // CHECK: vrshr.s64     q8, q8, #64     @ encoding: [0xf0,0x02,0xc0,0xf2]
146         vrshr.s64       q8, q8, #64
147 // CHECK: vrshr.u8      q8, q8, #8      @ encoding: [0x70,0x02,0xc8,0xf3]
148         vrshr.u8        q8, q8, #8
149 // CHECK: vrshr.u16     q8, q8, #16     @ encoding: [0x70,0x02,0xd0,0xf3]
150         vrshr.u16       q8, q8, #16
151 // CHECK: vrshr.u32     q8, q8, #32     @ encoding: [0x70,0x02,0xe0,0xf3]
152         vrshr.u32       q8, q8, #32
153 // CHECK: vrshr.u64     q8, q8, #64     @ encoding: [0xf0,0x02,0xc0,0xf3]
154         vrshr.u64       q8, q8, #64
155 // CHECK: vrshrn.i16    d16, q8, #8     @ encoding: [0x70,0x08,0xc8,0xf2]
156         vrshrn.i16      d16, q8, #8
157 // CHECK: vrshrn.i32    d16, q8, #16    @ encoding: [0x70,0x08,0xd0,0xf2]
158         vrshrn.i32      d16, q8, #16
159 // CHECK: vrshrn.i64    d16, q8, #32    @ encoding: [0x70,0x08,0xe0,0xf2]
160         vrshrn.i64      d16, q8, #32