Mark ARM subtarget features that are available for the assembler.
[oota-llvm.git] / test / MC / ARM / neon-mul-accum-encoding.s
1 // RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s
2 // XFAIL: *
3
4 // CHECK: vmla.i8       d16, d18, d17           @ encoding: [0xa1,0x09,0x42,0xf2]
5         vmla.i8 d16, d18, d17
6 // CHECK: vmla.i16      d16, d18, d17   @ encoding: [0xa1,0x09,0x52,0xf2]
7         vmla.i16        d16, d18, d17
8 // CHECK: vmla.i16      d16, d18, d17   @ encoding: [0xa1,0x09,0x52,0xf2]
9         vmla.i32        d16, d18, d17
10 // CHECK: vmla.f32      d16, d18, d17   @ encoding: [0xb1,0x0d,0x42,0xf2]
11         vmla.f32        d16, d18, d17
12 // CHECK: vmla.i8       q9, q8, q10             @ encoding: [0xe4,0x29,0x40,0xf2]
13         vmla.i8 q9, q8, q10
14 // CHECK: vmla.i16      q9, q8, q10     @ encoding: [0xe4,0x29,0x50,0xf2]
15         vmla.i16        q9, q8, q10
16 // CHECK: vmla.i32      q9, q8, q10     @ encoding: [0xe4,0x29,0x60,0xf2]
17         vmla.i32        q9, q8, q10
18 // CHECK: vmla.f32      q9, q8, q10     @ encoding: [0xf4,0x2d,0x40,0xf2]
19         vmla.f32        q9, q8, q10
20 // CHECK: vmlal.s8      q8, d19, d18    @ encoding: [0xa2,0x08,0xc3,0xf2]
21         vmlal.s8        q8, d19, d18
22 // CHECK: vmlal.s16     q8, d19, d18    @ encoding: [0xa2,0x08,0xd3,0xf2]
23         vmlal.s16       q8, d19, d18
24 // CHECK: vmlal.s32     q8, d19, d18    @ encoding: [0xa2,0x08,0xe3,0xf2]
25         vmlal.s32       q8, d19, d18
26 // CHECK: vmlal.u8      q8, d19, d18    @ encoding: [0xa2,0x08,0xc3,0xf3]
27         vmlal.u8        q8, d19, d18
28 // CHECK: vmlal.u16     q8, d19, d18    @ encoding: [0xa2,0x08,0xd3,0xf3]
29         vmlal.u16       q8, d19, d18
30 // CHECK: vmlal.u32     q8, d19, d18    @ encoding: [0xa2,0x08,0xe3,0xf3]
31         vmlal.u32       q8, d19, d18
32 // CHECK: vqdmlal.s16   q8, d19, d18    @ encoding: [0xa2,0x09,0xd3,0xf2]
33         vqdmlal.s16     q8, d19, d18
34 // CHECK: vqdmlal.s32   q8, d19, d18    @ encoding: [0xa2,0x09,0xe3,0xf2]
35         vqdmlal.s32     q8, d19, d18
36 // CHECK: vmls.i8       d16, d18, d17           @ encoding: [0xa1,0x09,0x42,0xf3]
37         vmls.i8 d16, d18, d17
38 // CHECK: vmls.i16      d16, d18, d17   @ encoding: [0xa1,0x09,0x52,0xf3]
39         vmls.i16        d16, d18, d17
40 // CHECK: vmls.i32      d16, d18, d17   @ encoding: [0xa1,0x09,0x62,0xf3]
41         vmls.i32        d16, d18, d17
42 // CHECK: vmls.f32      d16, d18, d17   @ encoding: [0xb1,0x0d,0x62,0xf2]
43         vmls.f32        d16, d18, d17
44 // CHECK: vmls.i8       q9, q8, q10             @ encoding: [0xe4,0x29,0x40,0xf3]
45         vmls.i8 q9, q8, q10
46 // CHECK: vmls.i16      q9, q8, q10     @ encoding: [0xe4,0x29,0x50,0xf3]
47         vmls.i16        q9, q8, q10
48 // CHECK: vmls.i32      q9, q8, q10     @ encoding: [0xe4,0x29,0x60,0xf3]
49         vmls.i32        q9, q8, q10
50 // CHECK: vmls.f32      q9, q8, q10     @ encoding: [0xf4,0x2d,0x60,0xf2]
51         vmls.f32        q9, q8, q10
52 // CHECK: vmlsl.s8      q8, d19, d18    @ encoding: [0xa2,0x0a,0xc3,0xf2]
53         vmlsl.s8        q8, d19, d18
54 // CHECK: vmlsl.s16     q8, d19, d18    @ encoding: [0xa2,0x0a,0xd3,0xf2]
55         vmlsl.s16       q8, d19, d18
56 // CHECK: vmlsl.s32     q8, d19, d18    @ encoding: [0xa2,0x0a,0xe3,0xf2]
57         vmlsl.s32       q8, d19, d18
58 // CHECK: vmlsl.u8      q8, d19, d18    @ encoding: [0xa2,0x0a,0xc3,0xf3]
59         vmlsl.u8        q8, d19, d18
60 // CHECK: vmlsl.u16     q8, d19, d18    @ encoding: [0xa2,0x0a,0xd3,0xf3]
61         vmlsl.u16       q8, d19, d18
62 // CHECK: vmlsl.u32     q8, d19, d18    @ encoding: [0xa2,0x0a,0xe3,0xf3]
63         vmlsl.u32       q8, d19, d18
64 // CHECK: vqdmlsl.s16   q8, d19, d18    @ encoding: [0xa2,0x0b,0xd3,0xf2]
65         vqdmlsl.s16     q8, d19, d18
66 // CHECK: vqdmlsl.s32   q8, d19, d18    @ encoding: [0xa2,0x0b,0xe3,0xf2]
67         vqdmlsl.s32     q8, d19, d18