[Hexagon] Adding missing vector multiply instruction encodings. Converting multiply...
[oota-llvm.git] / test / MC / ARM / load-store-acquire-release-v8.s
1 @ RUN: llvm-mc -triple=armv8 -show-encoding < %s | FileCheck %s
2 @ RUN: not llvm-mc -triple=armv7 -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=CHECK-V7
3         ldaexb  r3, [r4]
4         ldaexh  r2, [r5]
5         ldaex  r1, [r7]
6         ldaexd  r6, r7, [r8]
7
8 @ CHECK: ldaexb r3, [r4]                @ encoding: [0x9f,0x3e,0xd4,0xe1]
9 @ CHECK: ldaexh r2, [r5]                @ encoding: [0x9f,0x2e,0xf5,0xe1]
10 @ CHECK: ldaex r1, [r7]                @ encoding: [0x9f,0x1e,0x97,0xe1]
11 @ CHECK: ldaexd r6, r7, [r8]            @ encoding: [0x9f,0x6e,0xb8,0xe1]
12 @ CHECK-V7: instruction requires: armv8
13 @ CHECK-V7: instruction requires: armv8
14 @ CHECK-V7: instruction requires: armv8
15 @ CHECK-V7: instruction requires: armv8
16
17         stlexb  r1, r3, [r4]
18         stlexh  r4, r2, [r5]
19         stlex  r2, r1, [r7]
20         stlexd  r6, r2, r3, [r8]
21 @ CHECK: stlexb r1, r3, [r4]            @ encoding: [0x93,0x1e,0xc4,0xe1]
22 @ CHECK: stlexh r4, r2, [r5]            @ encoding: [0x92,0x4e,0xe5,0xe1]
23 @ CHECK: stlex r2, r1, [r7]            @ encoding: [0x91,0x2e,0x87,0xe1]
24 @ CHECK: stlexd r6, r2, r3, [r8]        @ encoding: [0x92,0x6e,0xa8,0xe1]
25 @ CHECK-V7: instruction requires: armv8
26 @ CHECK-V7: instruction requires: armv8
27 @ CHECK-V7: instruction requires: armv8
28 @ CHECK-V7: instruction requires: armv8
29
30          lda r5, [r6]
31          ldab r5, [r6]
32          ldah r12, [r9]
33 @ CHECK: lda r5, [r6]                   @ encoding: [0x9f,0x5c,0x96,0xe1]
34 @ CHECK: ldab r5, [r6]                  @ encoding: [0x9f,0x5c,0xd6,0xe1]
35 @ CHECK: ldah r12, [r9]                 @ encoding: [0x9f,0xcc,0xf9,0xe1]
36 @ CHECK-V7: instruction requires: armv8
37 @ CHECK-V7: instruction requires: armv8
38 @ CHECK-V7: instruction requires: armv8
39
40          stl r3, [r0]
41          stlb r2, [r1]
42          stlh r2, [r3]
43 @ CHECK: stl r3, [r0]                   @ encoding: [0x93,0xfc,0x80,0xe1]
44 @ CHECK: stlb r2, [r1]                  @ encoding: [0x92,0xfc,0xc1,0xe1]
45 @ CHECK: stlh r2, [r3]                  @ encoding: [0x92,0xfc,0xe3,0xe1]
46 @ CHECK-V7: instruction requires: armv8
47 @ CHECK-V7: instruction requires: armv8
48 @ CHECK-V7: instruction requires: armv8