1 @ RUN: llvm-mc -triple=thumbv6-apple-darwin -show-encoding < %s | FileCheck %s
5 @ Check that the assembler can handle the documented syntax from the ARM ARM.
6 @ For complex constructs like shifter operands, check more thoroughly for them
7 @ once then spot check that following instructions accept the form generally.
8 @ This gives us good coverage while keeping the overall size of the test
14 @------------------------------------------------------------------------------
16 @------------------------------------------------------------------------------
19 @ CHECK: adcs r4, r6 @ encoding: [0x74,0x41]
22 @------------------------------------------------------------------------------
24 @------------------------------------------------------------------------------
29 @ CHECK: adds r1, r2, #3 @ encoding: [0xd1,0x1c]
30 @ CHECK: adds r2, r2, #3 @ encoding: [0xd2,0x1c]
31 @ CHECK: adds r2, #8 @ encoding: [0x08,0x32]
34 @------------------------------------------------------------------------------
36 @------------------------------------------------------------------------------
40 @ CHECK: adds r1, r2, r3 @ encoding: [0xd1,0x18]
41 @ CHECK: add r2, r8 @ encoding: [0x42,0x44]
44 @------------------------------------------------------------------------------
45 @ FIXME: ADD (SP plus immediate)
46 @------------------------------------------------------------------------------
47 @------------------------------------------------------------------------------
48 @ FIXME: ADD (SP plus register)
49 @------------------------------------------------------------------------------
52 @------------------------------------------------------------------------------
54 @------------------------------------------------------------------------------
57 @ CHECK: adr r2, _baz @ encoding: [A,0xa2]
58 @ fixup A - offset: 0, value: _baz, kind: fixup_thumb_adr_pcrel_10
61 @------------------------------------------------------------------------------
63 @------------------------------------------------------------------------------
68 @ CHECK: asrs r2, r3, #32 @ encoding: [0x1a,0x10]
69 @ CHECK: asrs r2, r3, #5 @ encoding: [0x5a,0x11]
70 @ CHECK: asrs r2, r3, #1 @ encoding: [0x5a,0x10]
73 @------------------------------------------------------------------------------
75 @------------------------------------------------------------------------------
78 @ CHECK: asrs r5, r2 @ encoding: [0x15,0x41]
81 @------------------------------------------------------------------------------
83 @------------------------------------------------------------------------------
87 @ CHECK: b _baz @ encoding: [A,0xe0'A']
88 @ fixup A - offset: 0, value: _baz, kind: fixup_arm_thumb_br
89 @ CHECK: beq _bar @ encoding: [A,0xd0]
90 @ fixup A - offset: 0, value: _bar, kind: fixup_arm_thumb_bcc
93 @------------------------------------------------------------------------------
95 @------------------------------------------------------------------------------
98 @ CHECK: bics r1, r6 @ encoding: [0xb1,0x43]
101 @------------------------------------------------------------------------------
103 @------------------------------------------------------------------------------
107 @ CHECK: bkpt #0 @ encoding: [0x00,0xbe]
108 @ CHECK: bkpt #255 @ encoding: [0xff,0xbe]
111 @------------------------------------------------------------------------------
113 @------------------------------------------------------------------------------
117 @ CHECK: bl _bar @ encoding: [A,0xf0'A',A,0xf8'A']
118 @ fixup A - offset: 0, value: _bar, kind: fixup_arm_thumb_bl
119 @ CHECK: blx _baz @ encoding: [A,0xf0'A',A,0xe8'A']
120 @ fixup A - offset: 0, value: _baz, kind: fixup_arm_thumb_blx
123 @------------------------------------------------------------------------------
125 @------------------------------------------------------------------------------
128 @ CHECK: blx r4 @ encoding: [0xa0,0x47]
131 @------------------------------------------------------------------------------
133 @------------------------------------------------------------------------------
136 @ CHECK: bx r2 @ encoding: [0x10,0x47]
139 @------------------------------------------------------------------------------
141 @------------------------------------------------------------------------------
145 @ CHECK: cmn r5, r1 @ encoding: [0xcd,0x42]
148 @------------------------------------------------------------------------------
150 @------------------------------------------------------------------------------
155 @ CHECK: cmp r6, #32 @ encoding: [0x20,0x2e]
156 @ CHECK: cmp r3, r4 @ encoding: [0xa3,0x42]
157 @ CHECK: cmp r8, r1 @ encoding: [0x88,0x45]
159 @------------------------------------------------------------------------------
161 @------------------------------------------------------------------------------
164 @ CHECK: eors r4, r5 @ encoding: [0x6c,0x40]
167 @------------------------------------------------------------------------------
169 @------------------------------------------------------------------------------
170 ldm r3, {r0, r1, r2, r3, r4, r5, r6, r7}
171 ldm r2!, {r1, r3, r4, r5, r7}
174 @ CHECK: ldm r3, {r0, r1, r2, r3, r4, r5, r6, r7} @ encoding: [0xff,0xcb]
175 @ CHECK: ldm r2!, {r1, r3, r4, r5, r7} @ encoding: [0xba,0xca]
176 @ CHECK: ldm r1, {r1} @ encoding: [0x02,0xc9]