test/MC/ARM/basic-thumb-instructions.s

   1 @ RUN: llvm-mc -triple=thumbv6-apple-darwin -show-encoding < %s | FileCheck %s
   2   .syntax unified
   3   .globl _func
   4
   5 @ Check that the assembler can handle the documented syntax from the ARM ARM.
   6 @ For complex constructs like shifter operands, check more thoroughly for them
   7 @ once then spot check that following instructions accept the form generally.
   8 @ This gives us good coverage while keeping the overall size of the test
   9 @ more reasonable.
  10
  11 _func:
  12 @ CHECK: _func
  13
  14 @------------------------------------------------------------------------------
  15 @ ADC (register)
  16 @------------------------------------------------------------------------------
  17         adcs r4, r6
  18
  19 @ CHECK: adcs   r4, r6                  @ encoding: [0x74,0x41]
  20
  21
  22 @------------------------------------------------------------------------------
  23 @ ADD (immediate)
  24 @------------------------------------------------------------------------------
  25         adds r1, r2, #3
  26         adds r2, #3
  27         adds r2, #8
  28
  29 @ CHECK: adds   r1, r2, #3              @ encoding: [0xd1,0x1c]
  30 @ CHECK: adds   r2, r2, #3              @ encoding: [0xd2,0x1c]
  31 @ CHECK: adds   r2, #8                  @ encoding: [0x08,0x32]
  32
  33
  34 @------------------------------------------------------------------------------
  35 @ ADD (register)
  36 @------------------------------------------------------------------------------
  37         adds r1, r2, r3
  38         add r2, r8
  39
  40 @ CHECK: adds   r1, r2, r3              @ encoding: [0xd1,0x18]
  41 @ CHECK: add    r2, r8                  @ encoding: [0x42,0x44]
  42
  43
  44 @------------------------------------------------------------------------------
  45 @ FIXME: ADD (SP plus immediate)
  46 @------------------------------------------------------------------------------
  47 @------------------------------------------------------------------------------
  48 @ FIXME: ADD (SP plus register)
  49 @------------------------------------------------------------------------------
  50
  51
  52 @------------------------------------------------------------------------------
  53 @ ADR
  54 @------------------------------------------------------------------------------
  55         adr r2, _baz
  56
  57 @ CHECK: adr    r2, _baz                @ encoding: [A,0xa2]
  58             @   fixup A - offset: 0, value: _baz, kind: fixup_thumb_adr_pcrel_10
  59
  60
  61 @------------------------------------------------------------------------------
  62 @ ASR (immediate)
  63 @------------------------------------------------------------------------------
  64         asrs r2, r3, #32
  65         asrs r2, r3, #5
  66         asrs r2, r3, #1
  67
  68 @ CHECK: asrs   r2, r3, #32             @ encoding: [0x1a,0x10]
  69 @ CHECK: asrs   r2, r3, #5              @ encoding: [0x5a,0x11]
  70 @ CHECK: asrs   r2, r3, #1              @ encoding: [0x5a,0x10]
  71
  72
  73 @------------------------------------------------------------------------------
  74 @ ASR (register)
  75 @------------------------------------------------------------------------------
  76         asrs r5, r2
  77
  78 @ CHECK: asrs   r5, r2                  @ encoding: [0x15,0x41]
  79
  80
  81 @------------------------------------------------------------------------------
  82 @ B
  83 @------------------------------------------------------------------------------
  84         b _baz
  85         beq _bar
  86
  87 @ CHECK: b      _baz                    @ encoding: [A,0xe0'A']
  88              @   fixup A - offset: 0, value: _baz, kind: fixup_arm_thumb_br
  89 @ CHECK: beq    _bar                    @ encoding: [A,0xd0]
  90              @   fixup A - offset: 0, value: _bar, kind: fixup_arm_thumb_bcc
  91
  92
  93 @------------------------------------------------------------------------------
  94 @ BICS
  95 @------------------------------------------------------------------------------
  96         bics r1, r6
  97
  98 @ CHECK: bics   r1, r6                  @ encoding: [0xb1,0x43]
  99
 100
 101 @------------------------------------------------------------------------------
 102 @ BKPT
 103 @------------------------------------------------------------------------------
 104         bkpt #0
 105         bkpt #255
 106
 107 @ CHECK: bkpt   #0                      @ encoding: [0x00,0xbe]
 108 @ CHECK: bkpt   #255                    @ encoding: [0xff,0xbe]
 109
 110
 111 @------------------------------------------------------------------------------
 112 @ BL/BLX (immediate)
 113 @------------------------------------------------------------------------------
 114         bl _bar
 115         blx _baz
 116
 117 @ CHECK: bl     _bar                    @ encoding: [A,0xf0'A',A,0xf8'A']
 118              @   fixup A - offset: 0, value: _bar, kind: fixup_arm_thumb_bl
 119 @ CHECK: blx    _baz                    @ encoding: [A,0xf0'A',A,0xe8'A']
 120              @   fixup A - offset: 0, value: _baz, kind: fixup_arm_thumb_blx
 121
 122
 123 @------------------------------------------------------------------------------
 124 @ BLX (register)
 125 @------------------------------------------------------------------------------
 126         blx r4
 127
 128 @ CHECK: blx    r4                      @ encoding: [0xa0,0x47]
 129
 130
 131 @------------------------------------------------------------------------------
 132 @ BX
 133 @------------------------------------------------------------------------------
 134         bx r2
 135
 136 @ CHECK: bx     r2                      @ encoding: [0x10,0x47]
 137
 138
 139 @------------------------------------------------------------------------------
 140 @ CMN
 141 @------------------------------------------------------------------------------
 142
 143         cmn r5, r1
 144
 145 @ CHECK: cmn    r5, r1                  @ encoding: [0xcd,0x42]
 146
 147
 148 @------------------------------------------------------------------------------
 149 @ CMP
 150 @------------------------------------------------------------------------------
 151         cmp r6, #32
 152         cmp r3, r4
 153         cmp r8, r1
 154
 155 @ CHECK: cmp    r6, #32                 @ encoding: [0x20,0x2e]
 156 @ CHECK: cmp    r3, r4                  @ encoding: [0xa3,0x42]
 157 @ CHECK: cmp    r8, r1                  @ encoding: [0x88,0x45]
 158
 159 @------------------------------------------------------------------------------
 160 @ EOR
 161 @------------------------------------------------------------------------------
 162         eors r4, r5
 163
 164 @ CHECK: eors   r4, r5                  @ encoding: [0x6c,0x40]
 165
 166
 167 @------------------------------------------------------------------------------
 168 @ LDM
 169 @------------------------------------------------------------------------------
 170         ldm r3, {r0, r1, r2, r3, r4, r5, r6, r7}
 171         ldm r2!, {r1, r3, r4, r5, r7}
 172         ldm r1, {r1}
 173
 174 @ CHECK: ldm    r3, {r0, r1, r2, r3, r4, r5, r6, r7} @ encoding: [0xff,0xcb]
 175 @ CHECK: ldm    r2!, {r1, r3, r4, r5, r7} @ encoding: [0xba,0xca]
 176 @ CHECK: ldm    r1, {r1}                @ encoding: [0x02,0xc9]
 177
 178
 179 @------------------------------------------------------------------------------
 180 @ LDR (immediate)
 181 @------------------------------------------------------------------------------
 182         ldr r1, [r5]
 183         ldr r2, [r6, #32]
 184         ldr r3, [r7, #124]
 185         ldr r1, [sp]
 186         ldr r2, [sp, #24]
 187         ldr r3, [sp, #1020]
 188
 189
 190 @ CHECK: ldr    r1, [r5]                @ encoding: [0x29,0x68]
 191 @ CHECK: ldr    r2, [r6, #32]           @ encoding: [0x32,0x6a]
 192 @ CHECK: ldr    r3, [r7, #124]          @ encoding: [0xfb,0x6f]
 193 @ CHECK: ldr    r1, [sp]                @ encoding: [0x00,0x99]
 194 @ CHECK: ldr    r2, [sp, #24]           @ encoding: [0x06,0x9a]
 195 @ CHECK: ldr    r3, [sp, #1020]         @ encoding: [0xff,0x9b]
 196
 197
 198 @------------------------------------------------------------------------------
 199 @ LDR (literal)
 200 @------------------------------------------------------------------------------
 201         ldr r1, _foo
 202
 203 @ CHECK: ldr    r1, _foo                @ encoding: [A,0x49]
 204              @   fixup A - offset: 0, value: _foo, kind: fixup_arm_thumb_cp
 205
 206
 207 @------------------------------------------------------------------------------
 208 @ LDR (register)
 209 @------------------------------------------------------------------------------
 210         ldr r1, [r2, r3]
 211
 212 @ CHECK: ldr    r1, [r2, r3]            @ encoding: [0xd1,0x58]