test/MC/ARM/arm_instructions.s

   1 @ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding %s | FileCheck %s
   2
   3 @ CHECK: trap
   4 @ CHECK: encoding: [0xfe,0xde,0xff,0xe7]
   5         trap
   6
   7 @ CHECK: bx     lr
   8 @ CHECK: encoding: [0x1e,0xff,0x2f,0xe1]
   9         bx lr
  10
  11 @ CHECK: vqdmull.s32    q8, d17, d16
  12 @ CHECK: encoding: [0xa0,0x0d,0xe1,0xf2]
  13         vqdmull.s32     q8, d17, d16
  14
  15 @ CHECK: and    r1, r2, r3 @ encoding: [0x03,0x10,0x02,0xe0]
  16         and r1,r2,r3
  17
  18 @ CHECK: ands   r1, r2, r3 @ encoding: [0x03,0x10,0x12,0xe0]
  19         ands r1,r2,r3
  20
  21 @ CHECK: eor    r1, r2, r3 @ encoding: [0x03,0x10,0x22,0xe0]
  22         eor r1,r2,r3
  23
  24 @ CHECK: eors   r1, r2, r3 @ encoding: [0x03,0x10,0x32,0xe0]
  25         eors r1,r2,r3
  26
  27 @ CHECK: sub    r1, r2, r3 @ encoding: [0x03,0x10,0x42,0xe0]
  28         sub r1,r2,r3
  29
  30 @ CHECK: subs   r1, r2, r3 @ encoding: [0x03,0x10,0x52,0xe0]
  31         subs r1,r2,r3
  32
  33 @ CHECK: add    r1, r2, r3 @ encoding: [0x03,0x10,0x82,0xe0]
  34         add r1,r2,r3
  35
  36 @ CHECK: adds   r1, r2, r3 @ encoding: [0x03,0x10,0x92,0xe0]
  37         adds r1,r2,r3
  38
  39 @ CHECK: adc    r1, r2, r3 @ encoding: [0x03,0x10,0xa2,0xe0]
  40         adc r1,r2,r3
  41
  42 @ CHECK: bic    r1, r2, r3 @ encoding: [0x03,0x10,0xc2,0xe1]
  43         bic r1,r2,r3
  44
  45 @ CHECK: bics   r1, r2, r3 @ encoding: [0x03,0x10,0xd2,0xe1]
  46         bics r1,r2,r3
  47
  48 @ CHECK: mov    r1, r2 @ encoding: [0x02,0x10,0xa0,0xe1]
  49         mov r1,r2
  50
  51 @ CHECK: mvn    r1, r2 @ encoding: [0x02,0x10,0xe0,0xe1]
  52         mvn r1,r2
  53
  54 @ CHECK: mvns   r1, r2 @ encoding: [0x02,0x10,0xf0,0xe1]
  55         mvns r1,r2
  56
  57 @ CHECK: bfi  r0, r0, #5, #7 @ encoding: [0x90,0x02,0xcb,0xe7]
  58         bfi  r0, r0, #5, #7
  59
  60 @ CHECK: bkpt  #10 @ encoding: [0x7a,0x00,0x20,0xe1]
  61         bkpt  #10
  62
  63 @ CHECK: cdp  p7, #1, c1, c1, c1, #4 @ encoding: [0x81,0x17,0x11,0xee]
  64         cdp  p7, #1, c1, c1, c1, #4
  65 @ CHECK: cdp2  p7, #1, c1, c1, c1, #4 @ encoding: [0x81,0x17,0x11,0xfe]
  66         cdp2  p7, #1, c1, c1, c1, #4
  67
  68 @ CHECK: wfe @ encoding: [0x02,0xf0,0x20,0xe3]
  69         wfe
  70
  71 @ CHECK: wfi @ encoding: [0x03,0xf0,0x20,0xe3]
  72         wfi
  73
  74 @ CHECK: yield @ encoding: [0x01,0xf0,0x20,0xe3]
  75         yield
  76
  77 @ CHECK: cpsie  aif @ encoding: [0xc0,0x01,0x08,0xf1]
  78         cpsie  aif
  79
  80 @ CHECK: cps  #15 @ encoding: [0x0f,0x00,0x02,0xf1]
  81         cps  #15
  82
  83 @ CHECK: cpsie  if, #10 @ encoding: [0xca,0x00,0x0a,0xf1]
  84         cpsie  if, #10
  85
  86 @ CHECK: add    r1, r2, r3, lsl r4      @ encoding: [0x13,0x14,0x82,0xe0]
  87   add r1, r2, r3, lsl r4
  88
  89 @ CHECK: strexb  r0, r1, [r2] @ encoding: [0x91,0x0f,0xc2,0xe1]
  90         strexb  r0, r1, [r2]
  91
  92 @ CHECK: strexh  r0, r1, [r2] @ encoding: [0x91,0x0f,0xe2,0xe1]
  93         strexh  r0, r1, [r2]
  94
  95 @ CHECK: strex  r0, r1, [r2] @ encoding: [0x91,0x0f,0x82,0xe1]
  96         strex  r0, r1, [r2]
  97
  98 @ CHECK: strexd  r0, r2, r3, [r1] @ encoding: [0x92,0x0f,0xa1,0xe1]
  99         strexd  r0, r2, r3, [r1]
 100
 101 @ CHECK: ldrexb  r0, [r0] @ encoding: [0x9f,0x0f,0xd0,0xe1]
 102         ldrexb  r0, [r0]
 103
 104 @ CHECK: ldrexh  r0, [r0] @ encoding: [0x9f,0x0f,0xf0,0xe1]
 105         ldrexh  r0, [r0]
 106
 107 @ CHECK: ldrex  r0, [r0] @ encoding: [0x9f,0x0f,0x90,0xe1]
 108         ldrex  r0, [r0]
 109
 110 @ CHECK: ldrexd  r0, r1, [r0] @ encoding: [0x9f,0x0f,0xb0,0xe1]
 111         ldrexd  r0, r1, [r0]
 112
 113 @ CHECK: ssat16  r0, #7, r0 @ encoding: [0x30,0x0f,0xa6,0xe6]
 114         ssat16  r0, #7, r0
 115