test/MC/AArch64/neon-simd-ldst-one-elem.s

   1 // RUN: llvm-mc -triple=arm64 -mattr=+neon -show-encoding < %s | FileCheck %s
   2
   3 // Check that the assembler can handle the documented syntax for AArch64
   4
   5 //------------------------------------------------------------------------------
   6 // Load single 1-element structure to all lanes of 1 register
   7 //------------------------------------------------------------------------------
   8          ld1r { v0.16b }, [x0]
   9          ld1r { v15.8h }, [x15]
  10          ld1r { v31.4s }, [sp]
  11          ld1r { v0.2d }, [x0]
  12          ld1r { v0.8b }, [x0]
  13          ld1r { v15.4h }, [x15]
  14          ld1r { v31.2s }, [sp]
  15          ld1r { v0.1d }, [x0]
  16 // CHECK: ld1r { v0.16b }, [x0]          // encoding: [0x00,0xc0,0x40,0x4d]
  17 // CHECK: ld1r { v15.8h }, [x15]         // encoding: [0xef,0xc5,0x40,0x4d]
  18 // CHECK: ld1r { v31.4s }, [sp]          // encoding: [0xff,0xcb,0x40,0x4d]
  19 // CHECK: ld1r { v0.2d }, [x0]           // encoding: [0x00,0xcc,0x40,0x4d]
  20 // CHECK: ld1r { v0.8b }, [x0]           // encoding: [0x00,0xc0,0x40,0x0d]
  21 // CHECK: ld1r { v15.4h }, [x15]         // encoding: [0xef,0xc5,0x40,0x0d]
  22 // CHECK: ld1r { v31.2s }, [sp]          // encoding: [0xff,0xcb,0x40,0x0d]
  23 // CHECK: ld1r { v0.1d }, [x0]           // encoding: [0x00,0xcc,0x40,0x0d]
  24
  25 //------------------------------------------------------------------------------
  26 // Load single N-element structure to all lanes of N consecutive
  27 // registers (N = 2,3,4)
  28 //------------------------------------------------------------------------------
  29          ld2r { v0.16b, v1.16b }, [x0]
  30          ld2r { v15.8h, v16.8h }, [x15]
  31          ld2r { v31.4s, v0.4s }, [sp]
  32          ld2r { v0.2d, v1.2d }, [x0]
  33          ld2r { v0.8b, v1.8b }, [x0]
  34          ld2r { v15.4h, v16.4h }, [x15]
  35          ld2r { v31.2s, v0.2s }, [sp]
  36          ld2r { v31.1d, v0.1d }, [sp]
  37 // CHECK: ld2r { v0.16b, v1.16b }, [x0]  // encoding: [0x00,0xc0,0x60,0x4d]
  38 // CHECK: ld2r { v15.8h, v16.8h }, [x15] // encoding: [0xef,0xc5,0x60,0x4d]
  39 // CHECK: ld2r { v31.4s, v0.4s }, [sp]   // encoding: [0xff,0xcb,0x60,0x4d]
  40 // CHECK: ld2r { v0.2d, v1.2d }, [x0]    // encoding: [0x00,0xcc,0x60,0x4d]
  41 // CHECK: ld2r { v0.8b, v1.8b }, [x0]    // encoding: [0x00,0xc0,0x60,0x0d]
  42 // CHECK: ld2r { v15.4h, v16.4h }, [x15] // encoding: [0xef,0xc5,0x60,0x0d]
  43 // CHECK: ld2r { v31.2s, v0.2s }, [sp]   // encoding: [0xff,0xcb,0x60,0x0d]
  44 // CHECK: ld2r { v31.1d, v0.1d }, [sp]   // encoding: [0xff,0xcf,0x60,0x0d]
  45
  46          ld3r { v0.16b, v1.16b, v2.16b }, [x0]
  47          ld3r { v15.8h, v16.8h, v17.8h }, [x15]
  48          ld3r { v31.4s, v0.4s, v1.4s }, [sp]
  49          ld3r { v0.2d, v1.2d, v2.2d }, [x0]
  50          ld3r { v0.8b, v1.8b, v2.8b }, [x0]
  51          ld3r { v15.4h, v16.4h, v17.4h }, [x15]
  52          ld3r { v31.2s, v0.2s, v1.2s }, [sp]
  53          ld3r { v31.1d, v0.1d, v1.1d }, [sp]
  54 // CHECK: ld3r { v0.16b, v1.16b, v2.16b }, [x0] // encoding: [0x00,0xe0,0x40,0x4d]
  55 // CHECK: ld3r { v15.8h, v16.8h, v17.8h }, [x15] // encoding: [0xef,0xe5,0x40,0x4d]
  56 // CHECK: ld3r { v31.4s, v0.4s, v1.4s }, [sp] // encoding: [0xff,0xeb,0x40,0x4d]
  57 // CHECK: ld3r { v0.2d, v1.2d, v2.2d }, [x0] // encoding: [0x00,0xec,0x40,0x4d]
  58 // CHECK: ld3r { v0.8b, v1.8b, v2.8b }, [x0] // encoding: [0x00,0xe0,0x40,0x0d]
  59 // CHECK: ld3r { v15.4h, v16.4h, v17.4h }, [x15] // encoding: [0xef,0xe5,0x40,0x0d]
  60 // CHECK: ld3r { v31.2s, v0.2s, v1.2s }, [sp] // encoding: [0xff,0xeb,0x40,0x0d]
  61 // CHECK: ld3r { v31.1d, v0.1d, v1.1d }, [sp] // encoding: [0xff,0xef,0x40,0x0d]
  62
  63          ld4r { v0.16b, v1.16b, v2.16b, v3.16b }, [x0]
  64          ld4r { v15.8h, v16.8h, v17.8h, v18.8h }, [x15]
  65          ld4r { v31.4s, v0.4s, v1.4s, v2.4s }, [sp]
  66          ld4r { v0.2d, v1.2d, v2.2d, v3.2d }, [x0]
  67          ld4r { v0.8b, v1.8b, v2.8b, v3.8b }, [x0]
  68          ld4r { v15.4h, v16.4h, v17.4h, v18.4h }, [x15]
  69          ld4r { v31.2s, v0.2s, v1.2s, v2.2s }, [sp]
  70          ld4r { v31.1d, v0.1d, v1.1d, v2.1d }, [sp]
  71 // CHECK: ld4r { v0.16b, v1.16b, v2.16b, v3.16b }, [x0] // encoding: [0x00,0xe0,0x60,0x4d]
  72 // CHECK: ld4r { v15.8h, v16.8h, v17.8h, v18.8h }, [x15] // encoding: [0xef,0xe5,0x60,0x4d]
  73 // CHECK: ld4r { v31.4s, v0.4s, v1.4s, v2.4s }, [sp] // encoding: [0xff,0xeb,0x60,0x4d]
  74 // CHECK: ld4r { v0.2d, v1.2d, v2.2d, v3.2d }, [x0] // encoding: [0x00,0xec,0x60,0x4d]
  75 // CHECK: ld4r { v0.8b, v1.8b, v2.8b, v3.8b }, [x0] // encoding: [0x00,0xe0,0x60,0x0d]
  76 // CHECK: ld4r { v15.4h, v16.4h, v17.4h, v18.4h }, [x15] // encoding: [0xef,0xe5,0x60,0x0d]
  77 // CHECK: ld4r { v31.2s, v0.2s, v1.2s, v2.2s }, [sp] // encoding: [0xff,0xeb,0x60,0x0d]
  78 // CHECK: ld4r { v31.1d, v0.1d, v1.1d, v2.1d }, [sp] // encoding: [0xff,0xef,0x60,0x0d]
  79
  80 //------------------------------------------------------------------------------
  81 // Load single 1-element structure to one lane of 1 register.
  82 //------------------------------------------------------------------------------
  83          ld1 { v0.b }[9], [x0]
  84          ld1 { v15.h }[7], [x15]
  85          ld1 { v31.s }[3], [sp]
  86          ld1 { v0.d }[1], [x0]
  87 // CHECK: ld1 { v0.b }[9], [x0]         // encoding: [0x00,0x04,0x40,0x4d]
  88 // CHECK: ld1 { v15.h }[7], [x15]       // encoding: [0xef,0x59,0x40,0x4d]
  89 // CHECK: ld1 { v31.s }[3], [sp]        // encoding: [0xff,0x93,0x40,0x4d]
  90 // CHECK: ld1 { v0.d }[1], [x0]         // encoding: [0x00,0x84,0x40,0x4d]
  91
  92 //------------------------------------------------------------------------------
  93 // Load single N-element structure to one lane of N consecutive registers
  94 // (N = 2,3,4)
  95 //------------------------------------------------------------------------------
  96          ld2 { v0.b, v1.b }[9], [x0]
  97          ld2 { v15.h, v16.h }[7], [x15]
  98          ld2 { v31.s, v0.s }[3], [sp]
  99          ld2 { v0.d, v1.d }[1], [x0]
 100 // CHECK: ld2 { v0.b, v1.b }[9], [x0]   // encoding: [0x00,0x04,0x60,0x4d]
 101 // CHECK: ld2 { v15.h, v16.h }[7], [x15] // encoding: [0xef,0x59,0x60,0x4d]
 102 // CHECK: ld2 { v31.s, v0.s }[3], [sp]  // encoding: [0xff,0x93,0x60,0x4d]
 103 // CHECK: ld2 { v0.d, v1.d }[1], [x0]   // encoding: [0x00,0x84,0x60,0x4d]
 104
 105          ld3 { v0.b, v1.b, v2.b }[9], [x0]
 106          ld3 { v15.h, v16.h, v17.h }[7], [x15]
 107          ld3 { v31.s, v0.s, v1.s }[3], [sp]
 108          ld3 { v0.d, v1.d, v2.d }[1], [x0]
 109 // CHECK: ld3 { v0.b, v1.b, v2.b }[9], [x0] // encoding: [0x00,0x24,0x40,0x4d]
 110 // CHECK: ld3 { v15.h, v16.h, v17.h }[7], [x15] // encoding: [0xef,0x79,0x40,0x4d]
 111 // CHECK: ld3 { v31.s, v0.s, v1.s }[3], [sp] // encoding: [0xff,0xb3,0x40,0x4d]
 112 // CHECK: ld3 { v0.d, v1.d, v2.d }[1], [x0] // encoding: [0x00,0xa4,0x40,0x4d]
 113
 114          ld4 { v0.b, v1.b, v2.b, v3.b }[9], [x0]
 115          ld4 { v15.h, v16.h, v17.h, v18.h }[7], [x15]
 116          ld4 { v31.s, v0.s, v1.s, v2.s }[3], [sp]
 117          ld4 { v0.d, v1.d, v2.d, v3.d }[1], [x0]
 118 // CHECK: ld4 { v0.b, v1.b, v2.b, v3.b }[9], [x0] // encoding: [0x00,0x24,0x60,0x4d]
 119 // CHECK: ld4 { v15.h, v16.h, v17.h, v18.h }[7], [x15] // encoding: [0xef,0x79,0x60,0x4d]
 120 // CHECK: ld4 { v31.s, v0.s, v1.s, v2.s }[3], [sp] // encoding: [0xff,0xb3,0x60,0x4d]
 121 // CHECK: ld4 { v0.d, v1.d, v2.d, v3.d }[1], [x0] // encoding: [0x00,0xa4,0x60,0x4d]
 122
 123 //------------------------------------------------------------------------------
 124 // Store single 1-element structure from one lane of 1 register.
 125 //------------------------------------------------------------------------------
 126          st1 { v0.b }[9], [x0]
 127          st1 { v15.h }[7], [x15]
 128          st1 { v31.s }[3], [sp]
 129          st1 { v0.d }[1], [x0]
 130 // CHECK: st1 { v0.b }[9], [x0]         // encoding: [0x00,0x04,0x00,0x4d]
 131 // CHECK: st1 { v15.h }[7], [x15]       // encoding: [0xef,0x59,0x00,0x4d]
 132 // CHECK: st1 { v31.s }[3], [sp]        // encoding: [0xff,0x93,0x00,0x4d]
 133 // CHECK: st1 { v0.d }[1], [x0]         // encoding: [0x00,0x84,0x00,0x4d]
 134
 135 //------------------------------------------------------------------------------
 136 // Store single N-element structure from one lane of N consecutive registers
 137 // (N = 2,3,4)
 138 //------------------------------------------------------------------------------
 139          st2 { v0.b, v1.b }[9], [x0]
 140          st2 { v15.h, v16.h }[7], [x15]
 141          st2 { v31.s, v0.s }[3], [sp]
 142          st2 { v0.d, v1.d }[1], [x0]
 143 // CHECK: st2 { v0.b, v1.b }[9], [x0]   // encoding: [0x00,0x04,0x20,0x4d]
 144 // CHECK: st2 { v15.h, v16.h }[7], [x15] // encoding: [0xef,0x59,0x20,0x4d]
 145 // CHECK: st2 { v31.s, v0.s }[3], [sp]  // encoding: [0xff,0x93,0x20,0x4d]
 146 // CHECK: st2 { v0.d, v1.d }[1], [x0]   // encoding: [0x00,0x84,0x20,0x4d]
 147
 148          st3 { v0.b, v1.b, v2.b }[9], [x0]
 149          st3 { v15.h, v16.h, v17.h }[7], [x15]
 150          st3 { v31.s, v0.s, v1.s }[3], [sp]
 151          st3 { v0.d, v1.d, v2.d }[1], [x0]
 152 // CHECK: st3 { v0.b, v1.b, v2.b }[9], [x0] // encoding: [0x00,0x24,0x00,0x4d]
 153 // CHECK: st3 { v15.h, v16.h, v17.h }[7], [x15] // encoding: [0xef,0x79,0x00,0x4d]
 154 // CHECK: st3 { v31.s, v0.s, v1.s }[3], [sp] // encoding: [0xff,0xb3,0x00,0x4d]
 155 // CHECK: st3 { v0.d, v1.d, v2.d }[1], [x0] // encoding: [0x00,0xa4,0x00,0x4d]
 156
 157          st4 { v0.b, v1.b, v2.b, v3.b }[9], [x0]
 158          st4 { v15.h, v16.h, v17.h, v18.h }[7], [x15]
 159          st4 { v31.s, v0.s, v1.s, v2.s }[3], [sp]
 160          st4 { v0.d, v1.d, v2.d, v3.d }[1], [x0]
 161 // CHECK: st4 { v0.b, v1.b, v2.b, v3.b }[9], [x0] // encoding: [0x00,0x24,0x20,0x4d]
 162 // CHECK: st4 { v15.h, v16.h, v17.h, v18.h }[7], [x15] // encoding: [0xef,0x79,0x20,0x4d]
 163 // CHECK: st4 { v31.s, v0.s, v1.s, v2.s }[3], [sp] // encoding: [0xff,0xb3,0x20,0x4d]
 164 // CHECK: st4 { v0.d, v1.d, v2.d, v3.d }[1], [x0] // encoding: [0x00,0xa4,0x20,0x4d]
 165
 166 //------------------------------------------------------------------------------
 167 // Post-index oad single 1-element structure to all lanes of 1 register
 168 //------------------------------------------------------------------------------
 169          ld1r { v0.16b }, [x0], #1
 170          ld1r { v15.8h }, [x15], #2
 171          ld1r { v31.4s }, [sp], #4
 172          ld1r { v0.2d }, [x0], #8
 173          ld1r { v0.8b }, [x0], x0
 174          ld1r { v15.4h }, [x15], x1
 175          ld1r { v31.2s }, [sp], x2
 176          ld1r { v0.1d }, [x0], x3
 177 // CHECK: ld1r { v0.16b }, [x0], #1      // encoding: [0x00,0xc0,0xdf,0x4d]
 178 // CHECK: ld1r { v15.8h }, [x15], #2     // encoding: [0xef,0xc5,0xdf,0x4d]
 179 // CHECK: ld1r { v31.4s }, [sp], #4      // encoding: [0xff,0xcb,0xdf,0x4d]
 180 // CHECK: ld1r { v0.2d }, [x0], #8       // encoding: [0x00,0xcc,0xdf,0x4d]
 181 // CHECK: ld1r { v0.8b }, [x0], x0       // encoding: [0x00,0xc0,0xc0,0x0d]
 182 // CHECK: ld1r { v15.4h }, [x15], x1     // encoding: [0xef,0xc5,0xc1,0x0d]
 183 // CHECK: ld1r { v31.2s }, [sp], x2      // encoding: [0xff,0xcb,0xc2,0x0d]
 184 // CHECK: ld1r { v0.1d }, [x0], x3       // encoding: [0x00,0xcc,0xc3,0x0d]
 185
 186 //------------------------------------------------------------------------------
 187 // Post-index load single N-element structure to all lanes of N consecutive
 188 // registers (N = 2,3,4)
 189 //------------------------------------------------------------------------------
 190          ld2r { v0.16b, v1.16b }, [x0], #2
 191          ld2r { v15.8h, v16.8h }, [x15], #4
 192          ld2r { v31.4s, v0.4s }, [sp], #8
 193          ld2r { v0.2d, v1.2d }, [x0], #16
 194          ld2r { v0.8b, v1.8b }, [x0], x6
 195          ld2r { v15.4h, v16.4h }, [x15], x7
 196          ld2r { v31.2s, v0.2s }, [sp], x9
 197          ld2r { v31.1d, v0.1d }, [x0], x5
 198 // CHECK: ld2r { v0.16b, v1.16b }, [x0], #2 // encoding: [0x00,0xc0,0xff,0x4d]
 199 // CHECK: ld2r { v15.8h, v16.8h }, [x15], #4 // encoding: [0xef,0xc5,0xff,0x4d]
 200 // CHECK: ld2r { v31.4s, v0.4s }, [sp], #8 // encoding: [0xff,0xcb,0xff,0x4d]
 201 // CHECK: ld2r { v0.2d, v1.2d }, [x0], #16 // encoding: [0x00,0xcc,0xff,0x4d]
 202 // CHECK: ld2r { v0.8b, v1.8b }, [x0], x6 // encoding: [0x00,0xc0,0xe6,0x0d]
 203 // CHECK: ld2r { v15.4h, v16.4h }, [x15], x7 // encoding: [0xef,0xc5,0xe7,0x0d]
 204 // CHECK: ld2r { v31.2s, v0.2s }, [sp], x9 // encoding: [0xff,0xcb,0xe9,0x0d]
 205 // CHECK: ld2r { v31.1d, v0.1d }, [x0], x5 // encoding: [0x1f,0xcc,0xe5,0x0d]
 206
 207          ld3r { v0.16b, v1.16b, v2.16b }, [x0], x9
 208          ld3r { v15.8h, v16.8h, v17.8h }, [x15], x6
 209          ld3r { v31.4s, v0.4s, v1.4s }, [sp], x7
 210          ld3r { v0.2d, v1.2d, v2.2d }, [x0], x5
 211          ld3r { v0.8b, v1.8b, v2.8b }, [x0], #3
 212          ld3r { v15.4h, v16.4h, v17.4h }, [x15], #6
 213          ld3r { v31.2s, v0.2s, v1.2s }, [sp], #12
 214          ld3r { v31.1d, v0.1d, v1.1d }, [sp], #24
 215 // CHECK: ld3r { v0.16b, v1.16b, v2.16b }, [x0], x9 // encoding: [0x00,0xe0,0xc9,0x4d]
 216 // CHECK: ld3r { v15.8h, v16.8h, v17.8h }, [x15], x6 // encoding: [0xef,0xe5,0xc6,0x4d]
 217 // CHECK: ld3r { v31.4s, v0.4s, v1.4s }, [sp], x7 // encoding: [0xff,0xeb,0xc7,0x4d]
 218 // CHECK: ld3r { v0.2d, v1.2d, v2.2d }, [x0], x5 // encoding: [0x00,0xec,0xc5,0x4d]
 219 // CHECK: ld3r { v0.8b, v1.8b, v2.8b }, [x0], #3 // encoding: [0x00,0xe0,0xdf,0x0d]
 220 // CHECK: ld3r { v15.4h, v16.4h, v17.4h }, [x15], #6 // encoding: [0xef,0xe5,0xdf,0x0d]
 221 // CHECK: ld3r { v31.2s, v0.2s, v1.2s }, [sp], #12 // encoding: [0xff,0xeb,0xdf,0x0d]
 222 // CHECK: ld3r { v31.1d, v0.1d, v1.1d }, [sp], #24 // encoding: [0xff,0xef,0xdf,0x0d]
 223
 224          ld4r { v0.16b, v1.16b, v2.16b, v3.16b }, [x0], #4
 225          ld4r { v15.8h, v16.8h, v17.8h, v18.8h }, [x15], #8
 226          ld4r { v31.4s, v0.4s, v1.4s, v2.4s }, [sp], #16
 227          ld4r { v0.2d, v1.2d, v2.2d, v3.2d }, [x0], #32
 228          ld4r { v0.8b, v1.8b, v2.8b, v3.8b }, [x0], x5
 229          ld4r { v15.4h, v16.4h, v17.4h, v18.4h }, [x15], x9
 230          ld4r { v31.2s, v0.2s, v1.2s, v2.2s }, [sp], x30
 231          ld4r { v31.1d, v0.1d, v1.1d, v2.1d }, [sp], x7
 232 // CHECK: ld4r { v0.16b, v1.16b, v2.16b, v3.16b }, [x0], #4 // encoding: [0x00,0xe0,0xff,0x4d]
 233 // CHECK: ld4r { v15.8h, v16.8h, v17.8h, v18.8h }, [x15], #8 // encoding: [0xef,0xe5,0xff,0x4d]
 234 // CHECK: ld4r { v31.4s, v0.4s, v1.4s, v2.4s }, [sp], #16 // encoding: [0xff,0xeb,0xff,0x4d]
 235 // CHECK: ld4r { v0.2d, v1.2d, v2.2d, v3.2d }, [x0], #32 // encoding: [0x00,0xec,0xff,0x4d]
 236 // CHECK: ld4r { v0.8b, v1.8b, v2.8b, v3.8b }, [x0], x5 // encoding: [0x00,0xe0,0xe5,0x0d]
 237 // CHECK: ld4r { v15.4h, v16.4h, v17.4h, v18.4h }, [x15], x9 // encoding: [0xef,0xe5,0xe9,0x0d]
 238 // CHECK: ld4r { v31.2s, v0.2s, v1.2s, v2.2s }, [sp], x30 // encoding: [0xff,0xeb,0xfe,0x0d]
 239 // CHECK: ld4r { v31.1d, v0.1d, v1.1d, v2.1d }, [sp], x7 // encoding: [0xff,0xef,0xe7,0x0d]
 240
 241 //------------------------------------------------------------------------------
 242 // Post-index load single 1-element structure to one lane of 1 register.
 243 //------------------------------------------------------------------------------
 244          ld1 { v0.b }[9], [x0], #1
 245          ld1 { v15.h }[7], [x15], x9
 246          ld1 { v31.s }[3], [sp], x6
 247          ld1 { v0.d }[1], [x0], #8
 248 // CHECK: ld1 { v0.b }[9], [x0], #1     // encoding: [0x00,0x04,0xdf,0x4d]
 249 // CHECK: ld1 { v15.h }[7], [x15], x9   // encoding: [0xef,0x59,0xc9,0x4d]
 250 // CHECK: ld1 { v31.s }[3], [sp], x6    // encoding: [0xff,0x93,0xc6,0x4d]
 251 // CHECK: ld1 { v0.d }[1], [x0], #8     // encoding: [0x00,0x84,0xdf,0x4d]
 252
 253 //------------------------------------------------------------------------------
 254 // Post-index load single N-element structure to one lane of N consecutive
 255 // registers (N = 2,3,4)
 256 //------------------------------------------------------------------------------
 257          ld2 { v0.b, v1.b }[9], [x0], x3
 258          ld2 { v15.h, v16.h }[7], [x15], #4
 259          ld2 { v31.s, v0.s }[3], [sp], #8
 260          ld2 { v0.d, v1.d }[1], [x0], x0
 261 // CHECK: ld2 { v0.b, v1.b }[9], [x0], x3 // encoding: [0x00,0x04,0xe3,0x4d]
 262 // CHECK: ld2 { v15.h, v16.h }[7], [x15], #4 // encoding: [0xef,0x59,0xff,0x4d]
 263 // CHECK: ld2 { v31.s, v0.s }[3], [sp], #8 // encoding: [0xff,0x93,0xff,0x4d]
 264 // CHECK: ld2 { v0.d, v1.d }[1], [x0], x0 // encoding: [0x00,0x84,0xe0,0x4d]
 265
 266          ld3 { v0.b, v1.b, v2.b }[9], [x0], #3
 267          ld3 { v15.h, v16.h, v17.h }[7], [x15], #6
 268          ld3 { v31.s, v0.s, v1.s }[3], [sp], x3
 269          ld3 { v0.d, v1.d, v2.d }[1], [x0], x6
 270 // CHECK: ld3 { v0.b, v1.b, v2.b }[9], [x0], #3 // encoding: [0x00,0x24,0xdf,0x4d]
 271 // CHECK: ld3 { v15.h, v16.h, v17.h }[7], [x15], #6 // encoding: [0xef,0x79,0xdf,0x4d]
 272 // CHECK: ld3 { v31.s, v0.s, v1.s }[3], [sp], x3 // encoding: [0xff,0xb3,0xc3,0x4d]
 273 // CHECK: ld3 { v0.d, v1.d, v2.d }[1], [x0], x6 // encoding: [0x00,0xa4,0xc6,0x4d]
 274
 275          ld4 { v0.b, v1.b, v2.b, v3.b }[9], [x0], x5
 276          ld4 { v15.h, v16.h, v17.h, v18.h }[7], [x15], x7
 277          ld4 { v31.s, v0.s, v1.s, v2.s }[3], [sp], #16
 278          ld4 { v0.d, v1.d, v2.d, v3.d }[1], [x0], #32
 279 // CHECK: ld4 { v0.b, v1.b, v2.b, v3.b }[9], [x0], x5 // encoding: [0x00,0x24,0xe5,0x4d]
 280 // CHECK: ld4 { v15.h, v16.h, v17.h, v18.h }[7], [x15], x7 // encoding: [0xef,0x79,0xe7,0x4d]
 281 // CHECK: ld4 { v31.s, v0.s, v1.s, v2.s }[3], [sp], #16 // encoding: [0xff,0xb3,0xff,0x4d]
 282 // CHECK: ld4 { v0.d, v1.d, v2.d, v3.d }[1], [x0], #32 // encoding: [0x00,0xa4,0xff,0x4d]
 283
 284 //------------------------------------------------------------------------------
 285 // Post-index store single 1-element structure from one lane of 1 register.
 286 //------------------------------------------------------------------------------
 287          st1 { v0.b }[9], [x0], #1
 288          st1 { v15.h }[7], [x15], x9
 289          st1 { v31.s }[3], [sp], x6
 290          st1 { v0.d }[1], [x0], #8
 291 // CHECK: st1 { v0.b }[9], [x0], #1     // encoding: [0x00,0x04,0x9f,0x4d]
 292 // CHECK: st1 { v15.h }[7], [x15], x9   // encoding: [0xef,0x59,0x89,0x4d]
 293 // CHECK: st1 { v31.s }[3], [sp], x6    // encoding: [0xff,0x93,0x86,0x4d]
 294 // CHECK: st1 { v0.d }[1], [x0], #8     // encoding: [0x00,0x84,0x9f,0x4d]
 295
 296 //------------------------------------------------------------------------------
 297 // Post-index store single N-element structure from one lane of N consecutive
 298 // registers (N = 2,3,4)
 299 //------------------------------------------------------------------------------
 300          st2 { v0.b, v1.b }[9], [x0], x3
 301          st2 { v15.h, v16.h }[7], [x15], #4
 302          st2 { v31.s, v0.s }[3], [sp], #8
 303          st2 { v0.d, v1.d }[1], [x0], x0
 304 // CHECK: st2 { v0.b, v1.b }[9], [x0], x3 // encoding: [0x00,0x04,0xa3,0x4d]
 305 // CHECK: st2 { v15.h, v16.h }[7], [x15], #4 // encoding: [0xef,0x59,0xbf,0x4d]
 306 // CHECK: st2 { v31.s, v0.s }[3], [sp], #8 // encoding: [0xff,0x93,0xbf,0x4d]
 307 // CHECK: st2 { v0.d, v1.d }[1], [x0], x0 // encoding: [0x00,0x84,0xa0,0x4d]
 308
 309          st3 { v0.b, v1.b, v2.b }[9], [x0], #3
 310          st3 { v15.h, v16.h, v17.h }[7], [x15], #6
 311          st3 { v31.s, v0.s, v1.s }[3], [sp], x3
 312          st3 { v0.d, v1.d, v2.d }[1], [x0], x6
 313 // CHECK: st3 { v0.b, v1.b, v2.b }[9], [x0], #3 // encoding: [0x00,0x24,0x9f,0x4d]
 314 // CHECK: st3 { v15.h, v16.h, v17.h }[7], [x15], #6 // encoding: [0xef,0x79,0x9f,0x4d]
 315 // CHECK: st3 { v31.s, v0.s, v1.s }[3], [sp], x3 // encoding: [0xff,0xb3,0x83,0x4d]
 316 // CHECK: st3 { v0.d, v1.d, v2.d }[1], [x0], x6 // encoding: [0x00,0xa4,0x86,0x4d]
 317
 318          st4 { v0.b, v1.b, v2.b, v3.b }[9], [x0], x5
 319          st4 { v15.h, v16.h, v17.h, v18.h }[7], [x15], x7
 320          st4 { v31.s, v0.s, v1.s, v2.s }[3], [sp], #16
 321          st4 { v0.d, v1.d, v2.d, v3.d }[1], [x0], #32
 322 // CHECK: st4 { v0.b, v1.b, v2.b, v3.b }[9], [x0], x5 // encoding: [0x00,0x24,0xa5,0x4d]
 323 // CHECK: st4 { v15.h, v16.h, v17.h, v18.h }[7], [x15], x7 // encoding: [0xef,0x79,0xa7,0x4d]
 324 // CHECK: st4 { v31.s, v0.s, v1.s, v2.s }[3], [sp], #16 // encoding: [0xff,0xb3,0xbf,0x4d]
 325 // CHECK: st4 { v0.d, v1.d, v2.d, v3.d }[1], [x0], #32 // encoding: [0x00,0xa4,0xbf,0x4d]