1 ; RUN: not llvm-mc -triple arm64-apple-darwin -show-encoding < %s 2> %t | FileCheck %s
2 ; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
6 ; The first should encode as an expression. The second should error expecting
10 ; CHECK: ldr x3, foo+4 ; encoding: [0bAAA00011,A,A,0x58]
11 ; CHECK: ; fixup A - offset: 0, value: foo+4, kind: fixup_aarch64_ldr_pcrel_imm19
12 ; CHECK-ERRORS: error: invalid operand for instruction
14 ; The last argument should be flagged as an error. rdar://9576009
15 ld4.8b {v0, v1, v2, v3}, [x0], #33
16 ; CHECK-ERRORS: error: invalid operand for instruction
17 ; CHECK-ERRORS: ld4.8b {v0, v1, v2, v3}, [x0], #33
27 ldp w3, w4, [x5, #11]!
28 ldp x3, x4, [x5, #12]!
29 ldp q3, q4, [x5, #12]!
36 ; CHECK-ERRORS: error: index must be an integer in range [-256, 255].
37 ; CHECK-ERRORS: ldr x0, [x0, #804]
39 ; CHECK-ERRORS: error: index must be an integer in range [-256, 255].
40 ; CHECK-ERRORS: ldr w0, [x0, #802]
42 ; CHECK-ERRORS: error: index must be an integer in range [-256, 255].
43 ; CHECK-ERRORS: ldr x0, [x0, #804]!
45 ; CHECK-ERRORS: error: invalid operand for instruction
46 ; CHECK-ERRORS: ldr w0, [w0, #301]!
48 ; CHECK-ERRORS: error: index must be an integer in range [-256, 255].
49 ; CHECK-ERRORS: ldr x0, [x0], #804
51 ; CHECK-ERRORS: error: invalid operand for instruction
52 ; CHECK-ERRORS: ldr w0, [w0], #301
54 ; CHECK-ERRORS: error: index must be a multiple of 4 in range [-256, 252].
55 ; CHECK-ERRORS: ldp w3, w4, [x5, #11]!
57 ; CHECK-ERRORS: error: index must be a multiple of 8 in range [-512, 504].
58 ; CHECK-ERRORS: ldp x3, x4, [x5, #12]!
60 ; CHECK-ERRORS: error: index must be a multiple of 16 in range [-1024, 1008].
61 ; CHECK-ERRORS: ldp q3, q4, [x5, #12]!
63 ; CHECK-ERRORS: error: index must be a multiple of 4 in range [-256, 252].
64 ; CHECK-ERRORS: ldp w3, w4, [x5], #11
66 ; CHECK-ERRORS: error: index must be a multiple of 8 in range [-512, 504].
67 ; CHECK-ERRORS: ldp x3, x4, [x5], #12
69 ; CHECK-ERRORS: error: index must be a multiple of 16 in range [-1024, 1008].
70 ; CHECK-ERRORS: ldp q3, q4, [x5], #12
72 ; CHECK-ERRORS: error: index must be an integer in range [-256, 255].
73 ; CHECK-ERRORS: ldur x0, [x1, #-257]
77 ldrb w1, [x3, w3, sxtw #4]
78 ldrh w1, [x3, w3, sxtw #4]
79 ldr w1, [x3, w3, sxtw #4]
80 ldr x1, [x3, w3, sxtw #4]
81 ldr b1, [x3, w3, sxtw #4]
82 ldr h1, [x3, w3, sxtw #4]
83 ldr s1, [x3, w3, sxtw #4]
84 ldr d1, [x3, w3, sxtw #4]
85 ldr q1, [x3, w3, sxtw #1]
87 ; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0
88 ; CHECK-ERRORS:ldrb w1, [x3, w3, sxtw #4]
90 ; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0 or #1
91 ; CHECK-ERRORS:ldrh w1, [x3, w3, sxtw #4]
93 ; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0 or #2
94 ; CHECK-ERRORS:ldr w1, [x3, w3, sxtw #4]
96 ; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0 or #3
97 ; CHECK-ERRORS:ldr x1, [x3, w3, sxtw #4]
99 ; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0
100 ; CHECK-ERRORS:ldr b1, [x3, w3, sxtw #4]
102 ; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0 or #1
103 ; CHECK-ERRORS:ldr h1, [x3, w3, sxtw #4]
105 ; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0 or #2
106 ; CHECK-ERRORS:ldr s1, [x3, w3, sxtw #4]
108 ; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0 or #3
109 ; CHECK-ERRORS:ldr d1, [x3, w3, sxtw #4]
111 ; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0 or #4
112 ; CHECK-ERRORS:ldr q1, [x3, w3, sxtw #1]
115 ; Check that register offset addressing modes only accept 32-bit offset
116 ; registers when using uxtw/sxtw extends. Everything else requires a 64-bit
118 str d1, [x3, w3, sxtx #3]
119 ldr s1, [x3, d3, sxtx #2]
121 ; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0 or #3
122 ; CHECK-ERRORS: str d1, [x3, w3, sxtx #3]
124 ; CHECK-ERRORS: error: index must be an integer in range [-256, 255].
125 ; CHECK-ERRORS: ldr s1, [x3, d3, sxtx #2]
128 ; Shift immediates range checking.
130 rshrn v9.8b, v11.8h, #17
131 sqrshrn v7.4h, v8.4s, #39
132 uqshrn2 v4.4s, v5.2d, #67
134 ; CHECK-ERRORS: error: immediate must be an integer in range [1, 8].
135 ; CHECK-ERRORS: sqrshrn b4, h9, #10
137 ; CHECK-ERRORS: error: immediate must be an integer in range [1, 8].
138 ; CHECK-ERRORS: rshrn v9.8b, v11.8h, #17
140 ; CHECK-ERRORS: error: immediate must be an integer in range [1, 16].
141 ; CHECK-ERRORS: sqrshrn v7.4h, v8.4s, #39
143 ; CHECK-ERRORS: error: immediate must be an integer in range [1, 32].
144 ; CHECK-ERRORS: uqshrn2 v4.4s, v5.2d, #67
148 st1.s4 {v14, v15}, [x2], #32
149 ; CHECK-ERRORS: error: invalid type suffix for instruction
150 ; CHECK-ERRORS: st1.s4 {v14, v15}, [x2], #32
155 ; Load pair instructions where Rt==Rt2 and writeback load/store instructions
156 ; where Rt==Rn or Rt2==Rn are unpredicatable.
157 ldp x1, x2, [x2], #16
158 ldp x2, x2, [x2], #16
159 ldp w1, w2, [x2], #16
160 ldp w2, w2, [x2], #16
163 ldp s1, s1, [x1, #8]!
165 ldp d1, d1, [x1], #16
166 ldp d1, d1, [x1, #16]!
167 ldp d1, d1, [x1, #16]
168 ldp q1, q1, [x1], #32
169 ldp q1, q1, [x1, #32]!
170 ldp q1, q1, [x1, #32]
182 ; CHECK-ERRORS: error: unpredictable LDP instruction, writeback base is also a destination
183 ; CHECK-ERRORS: ldp x1, x2, [x2], #16
185 ; CHECK-ERRORS: error: unpredictable LDP instruction, writeback base is also a destination
186 ; CHECK-ERRORS: ldp x2, x2, [x2], #16
188 ; CHECK-ERRORS: error: unpredictable LDP instruction, writeback base is also a destination
189 ; CHECK-ERRORS: ldp w1, w2, [x2], #16
191 ; CHECK-ERRORS: error: unpredictable LDP instruction, writeback base is also a destination
192 ; CHECK-ERRORS: ldp w2, w2, [x2], #16
194 ; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
195 ; CHECK-ERRORS: ldp x1, x1, [x2]
197 ; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
198 ; CHECK-ERRORS: ldp s1, s1, [x1], #8
200 ; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
201 ; CHECK-ERRORS: ldp s1, s1, [x1, #8]!
203 ; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
204 ; CHECK-ERRORS: ldp s1, s1, [x1, #8]
206 ; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
207 ; CHECK-ERRORS: ldp d1, d1, [x1], #16
209 ; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
210 ; CHECK-ERRORS: ldp d1, d1, [x1, #16]!
212 ; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
213 ; CHECK-ERRORS: ldp d1, d1, [x1, #16]
215 ; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
216 ; CHECK-ERRORS: ldp q1, q1, [x1], #32
218 ; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
219 ; CHECK-ERRORS: ldp q1, q1, [x1, #32]!
221 ; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
222 ; CHECK-ERRORS: ldp q1, q1, [x1, #32]
224 ; CHECK-ERRORS: error: unpredictable LDR instruction, writeback base is also a source
225 ; CHECK-ERRORS: ldr x2, [x2], #8
227 ; CHECK-ERRORS: error: unpredictable LDR instruction, writeback base is also a source
228 ; CHECK-ERRORS: ldr x2, [x2, #8]!
230 ; CHECK-ERRORS: error: unpredictable LDR instruction, writeback base is also a source
231 ; CHECK-ERRORS: ldr w2, [x2], #8
233 ; CHECK-ERRORS: error: unpredictable LDR instruction, writeback base is also a source
234 ; CHECK-ERRORS: ldr w2, [x2, #8]!
236 ; CHECK-ERRORS: error: unpredictable STR instruction, writeback base is also a source
237 ; CHECK-ERRORS: str x2, [x2], #8
239 ; CHECK-ERRORS: error: unpredictable STR instruction, writeback base is also a source
240 ; CHECK-ERRORS: str x2, [x2, #8]!
242 ; CHECK-ERRORS: error: unpredictable STR instruction, writeback base is also a source
243 ; CHECK-ERRORS: str w2, [x2], #8
245 ; CHECK-ERRORS: error: unpredictable STR instruction, writeback base is also a source
246 ; CHECK-ERRORS: str w2, [x2, #8]!
249 ; The validity checking for shifted-immediate operands. rdar://13174476
250 ; Where the immediate is out of range.
251 add w1, w2, w3, lsr #75
253 ; CHECK-ERRORS: error: expected 'sxtx' 'uxtx' or 'lsl' with optional integer in range [0, 4]
254 ; CHECK-ERRORS: add w1, w2, w3, lsr #75
257 ; logical instructions on 32-bit regs with shift > 31 is not legal
258 orr w0, w0, w0, lsl #32
259 ; CHECK-ERRORS: error: expected 'lsl', 'lsr' or 'asr' with optional integer in range [0, 31]
260 ; CHECK-ERRORS: orr w0, w0, w0, lsl #32
262 eor w0, w0, w0, lsl #32
263 ; CHECK-ERRORS: error: expected 'lsl', 'lsr' or 'asr' with optional integer in range [0, 31]
264 ; CHECK-ERRORS: eor w0, w0, w0, lsl #32
266 and w0, w0, w0, lsl #32
267 ; CHECK-ERRORS: error: expected 'lsl', 'lsr' or 'asr' with optional integer in range [0, 31]
268 ; CHECK-ERRORS: and w0, w0, w0, lsl #32
270 ands w0, w0, w0, lsl #32
271 ; CHECK-ERRORS: error: expected 'lsl', 'lsr' or 'asr' with optional integer in range [0, 31]
272 ; CHECK-ERRORS: ands w0, w0, w0, lsl #32
275 ; Relocated expressions should not be accepted for 32-bit adds or sub (imm)
276 add w3, w5, sym@PAGEOFF
277 ; CHECK-ERRORS: error: invalid immediate expression
278 ; CHECK-ERRORS: add w3, w5, sym@PAGEOFF
281 adds w3, w5, sym@PAGEOFF
282 adds x9, x12, sym@PAGEOFF
283 ; CHECK-ERRORS: error: invalid immediate expression
284 ; CHECK-ERRORS: adds w3, w5, sym@PAGEOFF
286 ; CHECK-ERRORS: error: invalid immediate expression
287 ; CHECK-ERRORS: adds x9, x12, sym@PAGEOFF
290 sub x3, x5, sym@PAGEOFF
291 sub w20, w30, sym@PAGEOFF
292 ; CHECK-ERRORS: error: invalid immediate expression
293 ; CHECK-ERRORS: sub x3, x5, sym@PAGEOFF
295 ; CHECK-ERRORS: error: invalid immediate expression
296 ; CHECK-ERRORS: sub w20, w30, sym@PAGEOFF
299 subs w9, w10, sym@PAGEOFF
300 subs x20, x30, sym@PAGEOFF
301 ; CHECK-ERRORS: error: invalid immediate expression
302 ; CHECK-ERRORS: subs w9, w10, sym@PAGEOFF
304 ; CHECK-ERRORS: error: invalid immediate expression
305 ; CHECK-ERRORS: subs x20, x30, sym@PAGEOFF
308 tbl v0.8b, { v1 }, v0.8b
309 tbl v0.16b, { v1.8b, v2.8b, v3.8b }, v0.16b
310 tbx v3.16b, { v12.8b, v13.8b, v14.8b }, v6.8b
311 tbx v2.8b, { v0 }, v6.8b
312 ; CHECK-ERRORS: error: invalid operand for instruction
313 ; CHECK-ERRORS: tbl v0.8b, { v1 }, v0.8b
315 ; CHECK-ERRORS: error: invalid operand for instruction
316 ; CHECK-ERRORS: tbl v0.16b, { v1.8b, v2.8b, v3.8b }, v0.16b
318 ; CHECK-ERRORS: error: invalid operand for instruction
319 ; CHECK-ERRORS: tbx v3.16b, { v12.8b, v13.8b, v14.8b }, v6.8b
321 ; CHECK-ERRORS: error: invalid operand for instruction
322 ; CHECK-ERRORS: tbx v2.8b, { v0 }, v6.8b
326 ; CHECK-ERRORS: error: invalid condition code
327 ; CHECK-ERRORS: b.c #0x4
331 ; CHECK-ERRORS: error: specified ic op does not use a register
333 ; CHECK-ERRORS: error: specified ic op does not use a register
335 ; CHECK-ERRORS: error: specified ic op requires a register
338 ; CHECK-ERRORS: error: specified dc op requires a register
340 ; CHECK-ERRORS: error: specified dc op requires a register
342 ; CHECK-ERRORS: error: specified dc op requires a register
344 ; CHECK-ERRORS: error: specified dc op requires a register
346 ; CHECK-ERRORS: error: specified dc op requires a register
348 ; CHECK-ERRORS: error: specified dc op requires a register
350 ; CHECK-ERRORS: error: specified dc op requires a register
352 ; CHECK-ERRORS: error: specified dc op requires a register
355 ; CHECK-ERRORS: error: specified at op requires a register
357 ; CHECK-ERRORS: error: specified at op requires a register
359 ; CHECK-ERRORS: error: specified at op requires a register
361 ; CHECK-ERRORS: error: specified at op requires a register
363 ; CHECK-ERRORS: error: specified at op requires a register
365 ; CHECK-ERRORS: error: specified at op requires a register
367 ; CHECK-ERRORS: error: specified at op requires a register
369 ; CHECK-ERRORS: error: specified at op requires a register
371 ; CHECK-ERRORS: error: specified at op requires a register
373 ; CHECK-ERRORS: error: specified at op requires a register
375 ; CHECK-ERRORS: error: specified at op requires a register
377 ; CHECK-ERRORS: error: specified at op requires a register
380 ; CHECK-ERRORS: error: specified tlbi op does not use a register
382 ; CHECK-ERRORS: error: specified tlbi op does not use a register
384 ; CHECK-ERRORS: error: specified tlbi op does not use a register
386 ; CHECK-ERRORS: error: specified tlbi op does not use a register
388 ; CHECK-ERRORS: error: specified tlbi op does not use a register
390 ; CHECK-ERRORS: error: specified tlbi op does not use a register
392 ; CHECK-ERRORS: error: specified tlbi op does not use a register
394 ; CHECK-ERRORS: error: specified tlbi op does not use a register
396 ; CHECK-ERRORS: error: specified tlbi op requires a register
398 ; CHECK-ERRORS: error: specified tlbi op requires a register
400 ; CHECK-ERRORS: error: specified tlbi op requires a register
402 ; CHECK-ERRORS: error: specified tlbi op requires a register
404 ; CHECK-ERRORS: error: specified tlbi op requires a register
406 ; CHECK-ERRORS: error: specified tlbi op requires a register
408 ; CHECK-ERRORS: error: specified tlbi op requires a register
410 ; CHECK-ERRORS: error: specified tlbi op requires a register
412 ; CHECK-ERRORS: error: specified tlbi op requires a register
414 ; CHECK-ERRORS: error: specified tlbi op requires a register
416 ; CHECK-ERRORS: error: specified tlbi op requires a register
418 ; CHECK-ERRORS: error: specified tlbi op requires a register
420 ; CHECK-ERRORS: error: specified tlbi op requires a register
422 ; CHECK-ERRORS: error: specified tlbi op requires a register
424 ; CHECK-ERRORS: error: specified tlbi op requires a register
426 ; CHECK-ERRORS: error: specified tlbi op requires a register
428 ; CHECK-ERRORS: error: specified tlbi op requires a register
431 ; Check that we give the proper "too few operands" diagnostic even when
432 ; using short-form NEON.
434 add.16b v0, v1, v2, v3
440 ; CHECK-ERRORS: error: invalid operand for instruction
441 ; CHECK-ERRORS: add.16b v0, v1, v2, v3
443 ; CHECK-ERRORS: error: too few operands for instruction
444 ; CHECK-ERRORS: add.8b v0, v1
446 ; CHECK-ERRORS: error: too few operands for instruction
447 ; CHECK-ERRORS: sub.8h v0, v1
449 ; CHECK-ERRORS: error: too few operands for instruction
450 ; CHECK-ERRORS: fadd.4s v0
452 ; CHECK-ERRORS: error: too few operands for instruction
453 ; CHECK-ERRORS: fmul.2s
456 ; Also for 2-operand instructions.
458 frsqrte.4s v0, v1, v2
462 ; CHECK-ERRORS: error: invalid operand for instruction
463 ; CHECK-ERRORS: frsqrte.4s v0, v1, v2
465 ; CHECK-ERRORS: error: too few operands for instruction
466 ; CHECK-ERRORS: frsqrte.2s v0
468 ; CHECK-ERRORS: error: too few operands for instruction
469 ; CHECK-ERRORS: frecpe.2d
472 ; And check that we do the same for non-NEON instructions.
477 ; CHECK-ERRORS: error: too few operands for instruction
480 ; CHECK-ERRORS: error: invalid operand for instruction
481 ; CHECK-ERRORS: b.eq 0, 0
484 ; Check that we give the proper "too few operands" diagnostic instead of
489 ; CHECK-ERRORS: error: too few operands for instruction